JPH029009A - Digital data detector - Google Patents

Abstract

PURPOSE:To eliminate the need of a time constant circuit, to facilitate the IC conversion, and also, to stabilize a temperature characteristic by providing first and second gate circuits and resetting first and second latching circuits. CONSTITUTION:The title detector is provided with a differentiation circuit 14 for differentiating an output signal S1 from a magnetic head, a comparing circuit 2 for comparing its output with the ground potential, and comparing circuits 3, 4 for comparing the output signal S1 with positive and negative thresholds, and only while the comparing circuits 3, 4 are in a logic level '1', a variation of a logic level of the comparing circuit 2 is made effective, and an unstable operation of the comparing circuit 2 is eliminated. Also, gate circuits 10a, 10b are provided, and when an output pulse signal S4 of the comparing circuit 3 and a signal S10 of a DFF circuit 5a are both in the logic level '1', a DFF circuit 5b is reset. Moreover, when an output pulse signal S5 of the comparing circuit 4 and a signal S11 of the DFF circuit 5b are both in the logic level '1', the DFF circuit 5a is reset. Subsequently, the signal S10 of the same waveform as that of a signal which has been recorded in a magnetic tape is outputted from an output terminal 11.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a digital data detection method for detecting digitally recorded data from a signal read from a magnetic head in a digital magnetic recording/reproducing device such as a magnetic disk or a digital VTR. Concerning vessels.

[Prior Art] FIG. 3 shows a circuit diagram of an example of a conventional digital data detector used in a magnetic recording/reproducing device.

In Fig. 3, the output signal of a magnetic head system (hereinafter abbreviated as "magnetic head J") 1 consisting of a magnetic head and a head amplifier of a magnetic recording/reproducing device automatically adjusts the gain to an appropriate level. automatic gain control amplifier (
(hereinafter abbreviated as "rAGC amplifier") 12.

The output signal of the AGC amplifier 12 is input to an equalization circuit 13 that converts its frequency characteristics to suit the reproduction system.The output signal S1 of the zero equalization circuit 13 is input to a digital data detector 17. The output signal S of the equalization circuit 13 is also input to a control voltage generation circuit 16 that generates a signal for controlling the operation of the AGC amplifier 12.

Equalization circuit 1 input to digital data detector 11
The output signal S1 of No. 3 is input to the differentiating circuit 14. The output signal S2 of the differentiating circuit 14 is input to the first comparing circuit 2, which compares the output signal level of the differentiating circuit 14 with a ground potential. Further, the output signal S1 of the equalization circuit 13 is the output signal S
It is also input to a second comparison circuit 3 which compares the level of 1 with a preset positive threshold. Furthermore, the output signal s1
is also input to the third comparison circuit 4, which compares the level of the output signal S1 with a preset negative threshold.

At the rising edge of this inverted output pulse signal (that is, at the falling edge of the non-inverted output pulse signal S3), the inverted output pulse signal s4 of the first comparison circuit 2 corresponds to the output pulse signal s4 of the second comparison circuit 3 at that time. is input to the first latch circuit 5a which outputs an output pulse signal S6 of the same logic level as . This latch circuit 5a is constituted by a D flip-flop circuit (hereinafter abbreviated as rD-FF circuit J), and the inverted output pulse signal of the first comparator circuit 2 is input to the tarock input terminal of the DF circuit 5a. Second comparison circuit 3
The output pulse signal S4 is input to the D input terminal of the D/FF circuit 5a.

The non-inverted output pulse signal s3 of the first comparator circuit 2 is the third
The second latch circuit 5b outputs an output pulse signal S1 having the same logic level as the output pulse signal S of the comparison circuit 4. This latch circuit 5b is constituted by a D-FF circuit, and the non-inverted output pulse signal S of the first comparator circuit 2
3 is input to the clock input terminal of the DFF circuit 5b, and the output pulse signal S5 of the third comparison circuit 4 is input to the D-FF circuit 5.
It is input to the D input terminal of b.

The output pulse signal s6 of the D/FF circuit 5a and the output pulse signal s1 of the D/FF circuit 5b are both output from the OR gate circuit 6.
is input. Output pulse signal S of OR gate circuit 6
8 is input to the T-FF circuit 7 and the time constant circuit 15.

The output pulse signal s9 of the T-FF circuit 7 is outputted from the output terminal 8 of the digital data detector 17.

The output pulse signal of the time constant circuit 15 is the D-FF circuit 5a.
and is input to the reset terminal CR of the D-FF circuit 5b.

Next, the operation of this conventional digital data detector 17 will be explained with reference to the time chart of FIG.

The reproduction signal detected by the magnetic head 1 is sent to the AGC amplifier 1.
2 and an equalization circuit 13 to a digital data detector 17 .

For example, if a pulse signal such as sO in Figure 4 is recorded on a magnetic tape, the reproduced signal reproduced by the magnetic head 1 will become output signal S1 in the figure due to the differential characteristics of the tape head system. It becomes a waveform.

This output signal S1 is differentiated by a differentiating circuit 14 and output as an output signal S2. The output signal S2 becomes a signal that crosses 0 at the peak position of the output signal S1. This output signal S
2 is input to the first comparator circuit 2, which outputs an output pulse signal S3 that is at logic level 1 only while the output signal S2 is positive.

At the same time, the output signal S1 is input to the second comparison circuit 3 and the third comparison circuit 4, and is compared with preset positive and negative threshold values, respectively. Then, each comparison circuit 3.4 outputs a pulse signal S4. It is output as S5.

The D input terminal of the D/FF circuit 5a receives the output pulse signal S4.
However, an inverted output pulse signal of the output pulse signal S3 is input to the clock input terminal. Therefore, while the output pulse signal s4 is at logic level 1, the output pulse signal S3
If changes from logic level 1 to logic level 0, D-F
The output pulse signal S6 of the F circuit 5a becomes logic level 1.

When the output pulse signal S6 becomes logic level 1, the output pulse signal S8 of the OR gate circuit 6 also becomes logic level 1, and T
-Converts the logic level of the output pulse signal S9 of the FF circuit 7, and starts the time measurement operation of the time constant circuit 15.

The time constant circuit 15 is connected to the data SO recorded on the magnetic tape.
After measuring a time somewhat shorter than half of the interval T, an output pulse signal of logic level 1 is output.

Since this output pulse signal is input to the reset terminal CR of the D-FF circuit 5a, the D-FF circuit 5a is reset and the output pulse signal S6 becomes logic level 0.

The D-FF circuit 5b is similarly controlled by the output pulse signal 5385 and the output pulse signal of the time constant circuit 15.

In this way, the output terminal 8 of the digital data detector 17 outputs an output pulse signal S9 having the same signal waveform as the signal S recorded on the magnetic tape.

In addition, in the digital data detector 17 of this conventional example,
D-FF circuits sa, sb, etc. are provided without immediately converting the inverted output pulse signal of the first comparison circuit 2 into the output pulse signal S9, but this is because the logic level 0 of the signal SO recorded on the magnetic tape is If the reversal between 1 and 1 is not frequent, the output signal S2 when regenerated will stay near the O level for a long time, causing unstable operation in the output pulse signal S3, as shown by diagonal lines in FIG. This is because there will be a portion. Therefore, while setting positive and negative thresholds, D-F
F circuits 5a, 5b, etc. are provided, and the output pulse signal S is output only while the output pulse signal S4 or S5 is at logic level 1.
Output pulse signal S3 with the logic level change of 3 as valid.
This is to remove the unstable operating part.

[Problems to be Solved by the Invention] In the conventional digital data detector described above, the problem of unstable operation of the output pulse signal S3 is solved, but since the time constant circuit 15 is used, when the entire circuit is unified. Another problem is that it is difficult to incorporate a time constant circuit into an IC. Furthermore, since the time constant circuit has unstable temperature characteristics, there is also the drawback that the operation of the digital data detector becomes unstable due to temperature.

The present invention has been made in order to eliminate the drawbacks of such conventional digital data detectors.

The object of the present invention is to provide a digital data detector that is easy to integrate into an IC and has stable temperature characteristics. C [Means for Solving the Problem] In order to achieve the above-mentioned object, the digital data detector of the present invention includes a second comparison circuit that compares the output signal from the magnetic head with a positive threshold value. a first gate circuit that resets the second latch circuit when the output pulse signal and the output pulse signal of the first latch circuit that operates at the falling edge of the output pulse signal of the first comparison circuit are both at logic level 1; , an output pulse signal of a third comparison circuit that compares the output signal from the magnetic head with a negative threshold, and an output pulse signal of a second latch circuit that operates at the rising edge of the output pulse signal of the first comparison circuit. A second gate circuit that resets the first latch circuit when both are at logic level 1 is provided, thereby eliminating the need for a time constant circuit.

That is, the digital data detector of the present invention includes a differentiating circuit that differentiates the output signal from the magnetic head, a first comparing circuit that compares the output signal level of the differentiating circuit with a ground potential, and a differential circuit that differentiates the output signal from the magnetic head. a second comparison circuit that compares the output signal with a positive threshold; a third comparison circuit that compares the output signal from the magnetic head with a negative threshold; and an output pulse of the first comparison circuit. a first latch circuit that outputs a pulse signal of the same logic level as the output pulse signal of the second comparator circuit at the falling edge of the signal; and a second latch circuit that outputs a pulse signal of the same logic level as the output pulse signal of the third comparison circuit when the output pulse signal of the second comparison circuit and a first gate circuit that generates a signal for resetting the second latch circuit when the output pulse signals of the first latch circuit are both at logic level 1; The present invention is characterized in that a second gate circuit is provided that generates a reset signal that resets the first latch circuit when both output pulse signals of the second latch circuit are at logic level 1.

[Function] In the digital data detector of the present invention, a differentiation circuit, first to third comparison circuits, and first and second latch circuits are provided, and the second to third comparison circuits have a logic level of 1. It is the same as the conventional digital data detector that the change in the logic level of the first comparator circuit is made valid only during the period of time, thereby eliminating unstable operation of the first comparator circuit.

However, in the digital data detector of the present invention, first and second gate circuits are provided, and the first and second gate circuits are provided.
This eliminates the need for a time constant circuit by resetting the latch circuit. Therefore, it is easy to integrate it into an IC, and the temperature characteristics of the entire digital data detector are stable.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a time chart of the embodiment of FIG.

In FIG. 1, the input terminal 9 of the digital data detector of this embodiment is connected to the magnetic recording
The output signal S1 of the equalization circuit, which is input to the digital data detector of this embodiment connected to the output terminal of the equalization circuit of the reproducing apparatus, is input to the differentiating circuit 14. Differential circuit 1
The output signal S2 of No. 4 is input to the first comparison circuit 2, which compares the output signal level of the differentiating circuit 14 with the ground potential. This output signal S1 is also input to a second comparison circuit 3 that compares the level of the output signal S1 with a preset positive threshold. Furthermore, the output signal S1 is
A third step that compares the level of
It is also input to the comparison circuit 4.

The inverted output pulse signal of the first comparator circuit 2 is the same as the output pulse signal S4 of the second comparator circuit 3 at the time of the rise of the inverted output pulse signal (that is, the fall of the non-inverted output pulse signal S3). The signal is input to the first latch circuit 5a which outputs an output pulse signal S10 having a logic level of . This latch circuit 5a is constituted by a D-FF circuit, and the inverted output pulse signal of the first comparison port 282 is D-FF circuit.
The output pulse signal S4 of the second comparator circuit 3 is input to the clock input terminal of the FF circuit 5a, and the output pulse signal S4 of the D-FF circuit 5a is input to the clock input terminal of the FF circuit 5a.
Input to input terminal. Further, the output terminal of the D-FF circuit 5a is connected to the output terminal 11 of the digital data detector.

The non-inverted output pulse signal S3 of the first comparator circuit 2 outputs the third signal at the time of the rise of the non-inverted output pulse signal S3.
A second latch circuit 5 outputs an output pulse signal S11 having the same logic level as the output pulse signal S5 of the comparison circuit 4.
b. This latch circuit 5b is constituted by a D-FF circuit, and the non-inverted output pulse signal S3 of the first comparator circuit 2 is input to the clock input terminal of the D-FF circuit 5b.

The output pulse signal S5 of the third comparison circuit 4 is input to the D input terminal of the D-FF circuit 5b.

The output pulse signal S4 of the second comparator circuit 3 is the first AND
It is also input to one input terminal of the gate circuit 10a, and the first
The output pulse signal Sh of the latch circuit 5a.

is also input to the other input terminal of the first AM[+ gate circuit 10a. The output pulse signal S13 of the first AND gate circuit 10a is input to the reset terminal CH of the second latch circuit 5b.

The output pulse signal S5 of the third comparator circuit 4 is the second AND
It is also input to one input terminal of the gate circuit 10b, and the second
The output pulse signal Si+ of the latch circuit 5b is the second AN
It is input to the other input terminal of the D gate circuit 10b. The output pulse signal 312 of the second AND gate circuit 10b is input to the reset terminal CR of the first latch circuit 5a.

The operation of this embodiment will be described below with reference to FIG.

In this embodiment as well, as in the conventional example described above, the reproduction signal detected by the magnetic head is sent to the AGC amplifier.

The signal is supplied to input terminal 9 via an equalization circuit. The output signal S1 of this equalizer circuit has a waveform as shown in FIG. 2 due to the differential characteristics of the tape head system, as in the conventional example.

The output signal S of the equalization circuit inputted to the input terminal 9 is differentiated by the differentiating circuit 14 and becomes the output signal S2 of the differentiating circuit 14. The output signal S2 becomes a signal that crosses 0 at the peak position of the output signal S1. This output signal S2 is supplied to the first comparator circuit 2.
, and outputs an output pulse signal S3 that is at logic level 1 only while the output signal S is positive.

At the same time, the output signal S1 is input to the second comparison circuit 3 and the third comparison circuit 4, and is compared with preset positive and negative threshold values, respectively. Then, each comparison circuit 3.4 outputs the output pulse signals S4 and S5.

The D input terminal of the D-FF circuit 5a receives the output pulse signal S4.
However, an inverted output pulse signal of the output pulse signal S3 is input to the clock input terminal. Therefore, while the output pulse signal S4 is at logic level 1, the output pulse signal S3
If changes from logic level 1 to logic level 0, D-F
The output pulse signal S10 of the F circuit 5a becomes logic level 1. At this time, the output pulse signal S4 of the comparison circuit 3, which is one input signal of the first AND gate circuit 10a, and the output pulse signal S10 of the D-FF circuit 5a, which is the other input signal, both become logic level 1. Set the positive threshold as follows. As a result, the first AND gate circuit 10a
The output pulse signal S13 becomes logic level 1, and D-F
The output pulse signal S of the F circuit 5b is reset.

Similarly, while the output pulse signal S5 of the comparison circuit 4 is at the logic level 1, the output pulse signal S3 of the comparison circuit 2 changes from the logic level O to the logic level 1.
The output pulse signal S11 of the D/FF circuit 5b becomes logic level 1. At this time, the output pulse signal S5 of the comparator circuit 4, which is one input signal of the second AND gate circuit 10b,
A negative threshold value is set so that the output pulse signal S11 of the D-FF circuit 5b, which is the other input signal, both have a logic level of 1. As a result, the output pulse signal S12 of the second NO gate circuit 10b becomes logic level 1,
The D-FF circuit 5a is reset and the output pulse signal S1
0 is the logic level 0.

In this way, the signal S recorded on the magnetic tape is output from the output terminal 11 of the digital data detector of this embodiment.
An output pulse signal SIO having the same signal waveform as O is output.

[Effects of the Invention] In the digital data detector of the present invention, since the latch circuit is reset by two gate circuits without using a time constant circuit, it is easy to integrate it into an IC, and the temperature characteristics are stable. Become something.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a time chart of the embodiment of Fig. 1, Fig. 3 is a circuit diagram of a conventional example, and Fig. 4 is a time chart of the conventional example of Fig. 3. It is a chart. 1... Magnetic head 2, 3.4... Comparison circuit 6.
・・OR gate circuit 5a, 5b・D-FF circuit 7...T・FF circuit 10a, 10b-AND gate circuit 12...AG
C amplifier 13... Equalization circuit 14... Differential circuit
15...Time constant circuit 16...Control voltage generation circuit Inventor: Yasuhiko Teranishi

Claims (1)

[Claims] a differentiation circuit that differentiates an output signal from the magnetic head; a first comparison circuit that compares the output signal level of the differentiation circuit with a ground potential; and a first comparison circuit that compares the output signal from the magnetic head with a positive threshold. a third comparison circuit that compares the output signal from the magnetic head with a negative threshold; and a third comparison circuit that compares the output signal from the magnetic head with a negative threshold; a first latch circuit that outputs a pulse signal of the same logic level as the output pulse signal of the comparison circuit; and an output pulse signal of the third comparison circuit when the output pulse signal of the first comparison circuit rises. and a second latch circuit that outputs a pulse signal of the same logic level.
a first gate circuit that generates a reset signal that resets the second latch circuit when the output pulse signal of the second comparison circuit and the output pulse signal of the first latch circuit are both at logic level 1; a second gate circuit that generates a reset signal that resets the first latch circuit when both the output pulse signal of the third comparison circuit and the output pulse signal of the second latch circuit are at logic level 1; A digital data detector characterized by: