JPH0724143B2 - Sampling AGC circuit - Google Patents

Description

The present invention relates to a sampling AGC circuit suitable for use in removing level fluctuations of reproduced signals including burst signals in optical discs.

[Prior art]

The reproduced signal from the recording medium has a level fluctuation, and it is necessary to remove this level fluctuation before subjecting the reproduced signal to a predetermined process. Therefore, the reproduction signal processing circuit has
A common AGC circuit is provided. By the way, as the AGC circuit, conventionally, an average value AGC circuit, a peak AGC circuit, a sampling (keyed) AGC circuit, etc. are known, but each has its advantages and disadvantages. If the digital signal is a digital signal, the digital signal is composed of data in which high and low level bits are sparsely and densely arranged. Since these bits have no periodicity, an average value AGC circuit or a peak AGC circuit is used. It is not possible.

On the other hand, when a digital signal is recorded on a recording medium such as an optical disk, the digital signal partially contains a sync signal having a constant level and a constant cycle. Therefore, the level fluctuation of the digital signal reproduced from the recording medium can be known from the reproduction level of the synchronizing signal.
The sampling AGC circuit is suitable for removing the level fluctuation of the reproduced digital signal with the level of the synchronizing signal as a reference.

By the way, the AGC circuit needs a detection circuit for detecting the level of a target signal, and this detection circuit is conventionally composed of a rectifier 101, resistors 102 and 104, and a capacitor 103, as shown in FIG. The resistor 102 and the capacitor 103 form a time constant circuit, and the resistor 104 acts as a bias resistor of the rectifier 101. Here, this time constant circuit contributes as the time constant of the AGC loop and also affects the detection efficiency. For this reason, the resistor 102 and the capacitor 103 are considered in consideration of the AGC loop gain and response. Is set to an appropriate value.

In the sampling AGC circuit provided with such a detection circuit, there are a method of sampling at the front stage of the detector 101 and a method of sampling at the subsequent stage of the detector 101, but the latter is susceptible to disturbance, whereas the former For this reason, as shown in FIG. 5, a stable AGC operation can be obtained by providing the sampling switch 105 in the preceding stage of the rectifier 101 and performing sampling as shown in FIG.

[Problems to be solved by the invention]

By the way, the period of the sync signal included in the digital signal is very short. For this reason, when the synchronizing signal is separated by the sampling switch 105 and is supplied to the time constant circuit by the resistor 102 and the capacitor 103 through the rectifier 101, the time constant circuit can hold the detection output between the synchronizing signals constant. However, since it is necessary to set the time constant sufficiently large, it is not possible to obtain a detection output representing the level of this synchronizing signal by the time constant circuit within a very short synchronizing signal period.

Thus, even if the conventional sampling AGC circuit is used,
There is a problem that AGC cannot be applied sufficiently as the sampling period becomes shorter. This is generally true of AGC regardless of the reproduction signal of the optical disk.
This is true for signals with a very short burst signal period that can be used as a reference for multiplication.

An object of the present invention is to provide a sampling AGC circuit that solves the above-mentioned problems of the prior art and can sufficiently perform AGC even on a signal whose burst signal period that can be used as a reference is extremely short. It is in.

[Means for solving problems]

Therefore, the present invention separates a burst signal from a target signal, temporarily stores it in a memory, and repeatedly reads this to make a continuous signal, and supplies this continuous signal to a detection circuit to output an AGC detection output signal. By this, the time constant of the detection circuit can be set to an appropriate value in consideration of AGC loop gain and responsiveness.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a sampling AGC circuit according to the present invention, in which 1 is a variable gain circuit, 2 is an analog / digital converter, 3 is a sampling switch, 4 is a digital / analog converter, 5 Is an address counter, 6 is a memory, 7 is a detection circuit, 8 is a low-pass filter, 9 is a control signal generation circuit, 10 is a signal input terminal, 11 is an external control signal input terminal, 12
Is a signal output terminal.

In the figure, for example, a reproduction signal a from an optical disk (not shown) is supplied from the input terminal 10 to the variable gain circuit 1, and the gain of the variable gain circuit 1 is controlled by the AGC detection output signal from the low-pass filter 8. , Output terminal 12
An output signal e having a constant burst signal level is obtained.

On the other hand, the output signal e of the variable gain circuit 1 is converted into a digital signal by the analog / digital converter 2, and the sampling switch 3 which is turned on and off by the switching pulse b generated by the control signal generation circuit 4 from this digital signal. Thus, the burst signal c is extracted. The burst signal c is written in the addresses sequentially designated by the address counter 5 of the memory 6.

When the writing of the burst signal c to the memory 6 is completed,
The memory 6 is switched to the read mode by the mode switching signal h from the control signal generation circuit 9, and the burst signal c is repeatedly read from the memory 6 by the sequential addressing by the address counter 5. As a result, a continuous signal is obtained from the memory 6, and this is converted into an analog signal by the digital-analog converter 4, so that the continuous signal d having a level matching the burst signal level of the output signal e of the variable gain circuit 1 is obtained. Is obtained.

The continuous signal d is detected by the detection circuit 7 having the configuration shown in FIG. 4, and the output signal of the detection circuit 7 is supplied to the variable gain circuit 1 as the AGC detection output signal via the low pass filter 8. .

Next, the operation of this embodiment will be described in more detail with reference to FIG. 2 showing the signals of the respective parts in FIG.

Now, a series of partial signals A to D of the signal a from the input terminal 10
Among them, the partial signal C is assumed to be a burst signal, and the signal a is subjected to AGC so that its level becomes V ₀ . The signal a is supplied to the sampling switch 3 via the variable gain circuit 1 and the analog-digital converter 2, and the sampling switch 3 is closed for the period T of the sampling pulse b from the control signal generating circuit 9. Here, the control signal generating circuit 9 is supplied with the external control signal f from the input terminal 11. The external control signal f is a pulse signal having a time width T and supplied every period of the burst signal C. The control signal generation circuit 9 generates the reset pulse g of the address counter 5 which is phase-synchronized with the burst signal C of the signal a from the external control signal f, and also switches the time width T within the period of the burst signal C. A pulse b and a mode switching signal h for setting the memory 6 in the write mode during this period T and setting the memory 6 in the read mode during other periods are output. Therefore, the address counter 5 is synchronized with the burst signal C, repeats counting of a clock having a frequency equal to the sampling frequency in the analog-digital converter 2 with the period T as a cycle, and is separated by the sampling switch 3 in the memory 6. A sequential write address of the burst signal C of T is designated, and after this writing is finished, a repeated read address having the period T of the burst signal C in the memory 6 as a cycle is designated.

In this way, a continuous signal d is obtained from the digital-analog converter 4, but the level of this continuous signal d in the period Tm starting from this burst signal C is equal to the level of this burst signal C, The level of the continuous signal d in the period Tm ₋₁ before the period Tm is equal to the level of the immediately preceding burst signal C. That is, every time the burst signal C is extracted by the sampling switch 3, the continuous signal d
Is equal to the level of this burst signal C.
In FIG. ₂ , the burst signal C obtained by the repeated reading in the memory 6 during the period Tm is the burst signal C separated by the sampling switch 3 immediately before the bursts ▲ C ^m ₁ ▼, ▲ C ^m ₂ ▼ ,.
Burst signal ▲ C which has a level equal to and is obtained by repeated reading in the memory 6 during the period Tm _-1.
^m-1 _N-3 ▼, ▲ C ^m-1 _N-2 ▼, ▲ C ^m-1 _N-1 ▼, ▲ C ^m-1 _N-1 ▼
Has a level equal to the burst signal immediately preceding the burst signal C shown.

In this case, the period T during which the sampling switch 3 is closed and the burst signal C is extracted is equal to the period of the burst signal C of the signal a in FIG. 2, but if it is 1 cycle or more of the burst signal C, It may be equal to or less than the length of the period of the burst signal C. Further, during this period T, the signal extracted by the sampling switch 3 is also supplied to the detection circuit 7 via the D / A conversion circuit 4.

The continuous signal d is detected by the detection circuit 7, and its output signal is supplied to the variable gain circuit 1 via the low-pass filter 8.

FIG. 3 is a block diagram showing a specific example of the control signal generating circuit 9 in FIG. 1, in which 13 is an input terminal of the clock φ, 14 is a counter, 15 is a comparison circuit, 16 is an inverter, and 17 is an AND gate. Therefore, the same reference numerals are attached to the portions corresponding to FIG.

In FIG. 3, the high-level external control signal f input to the input terminal 11 is a desired signal to be extracted by the sampling switch 3 in the signal a (FIG. 2) (here, referred to as signal C, which is a burst signal). Signal) and has a time width equal to the period T of the burst signal C to be extracted. Such an external control signal f
Can be generated by, for example, a system controller (not shown) that controls the entire system, or can be formed by using a synchronization signal included in the signal a. The time width T of the external control signal f can be arbitrarily set in consideration of the extraction period of the burst signal C based on the AGC operation accuracy.

This external control signal f is supplied to the sampling switch 3 as the sampling pulse b, and the inverter 16
Is supplied to the memory 6 as a mode switching signal h via. During the period T of the external control signal f, the sampling switch 3 is closed and the burst signal C is extracted, and the memory 6 is in the write mode. In the other periods, the sampling switch 3 is open and the memory 6 is in the read mode.

The address counter 5 and the counter 14 are up counters. The address counter 5 is supplied with the clock φ from the input terminal 13 and reset by the reset pulse g from the comparison circuit 15. The comparator circuit 15 compares the count value of the address counter 5 with the count value of the counter 14, and generates a reset pulse g when the former exceeds the latter. The counter 14 is reset at the rising edge of the external control signal f and counts the clock φ supplied via the AND gate 17 which uses the external control signal f as a gate signal.

Therefore, when the external control signal f is input from the input terminal 11, the sampling switch 3 is closed, the burst signal C is extracted, and the memory 6 is in the write mode.

At the same time, the counter 14 is reset to the value 0 at the rising edge of the external control signal f, and the AND gate 17 is turned on to pass the clock φ to the counter 14. When the counter 14 is reset to the value 0, the comparator circuit 15 resets the reset pulse g when the count value of the address counter 5 is other than 0.
And the address counter 5 is reset to the value 0. In this way, when the count value of the counter 14 is 0, the count value of the address counter 5 is always 0.

The counter 14 is supplied with the clock φ for the period T of the external control signal g, that is, the sampling pulse b, and counts, and in synchronization with this, the address counter 5 also counts the clock φ. Therefore, during this period T, the count values of the address counter 5 and the counter 14 are equal, and the count value of the address counter 5 is supplied to the memory 6 as a write address.

After the period T of the sampling pulse b has elapsed, the sampling switch 3 is opened and the memory 6 is in the read mode. Along with this, the AND gate 17 is turned off and the counter
14 stops counting and holds the count value as it is. However, the address counter 5 counts the clock φ because it is continuously supplied. Therefore, when the count value of the address counter 5 exceeds the count value of the counter 14, the comparison circuit 15 generates a reset pulse g,
The address counter 5 is reset and counts up the clock φ again.

After that, the counter 14 displays the period T of the sampling pulse b.
The counter φ holds the count value obtained by counting the clock φ, and the address counter 5 counts the clock φ while resetting each time the count value exceeds the count value held in the counter 14. Therefore,
The count value of the address counter 5 repeats from 0 to the count value held in the counter 14, and is supplied to the memory 6 as a read address. As a result, the stored burst signal C is repeatedly read from the memory 6 in the order in which it was written, and a continuous signal is obtained.

As described above, in this embodiment, a continuous signal having a level equal to the level is formed from the burst signal C included in the signal a and the continuous signal is detected to generate an AGC detection output signal. This means that the period of the burst signal C is extended to generate the AGC detection output signal. Therefore, the time constant of the detection circuit 7 is set to that of the burst signal C of the signal a in consideration of the AGC loop gain and response. Even if it is set to be sufficiently longer than the period, it is possible to obtain the AGC detection signal having a level accurately corresponding to the level of the burst signal C. In other words, the time constant of the detection circuit 7 can be set independently of the sampling time constant of the input signal a, and the AG
C can be applied, and the degree of freedom in designing the detection circuit 7 increases.

〔The invention's effect〕

As described above, according to the present invention, since the time constant of the detection circuit can be set independently of the sampling time constant of the target signal, the period of the burst signal to be sampled from the target signal Even if is very short, the time constant of the detection circuit can be set so that the optimum AGC loop gain and responsiveness can be obtained, and excellent AGC characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a sampling AGC circuit according to the present invention, FIG. 2 is an operation explanatory diagram thereof, and FIG. 3 is a block diagram showing a concrete example of the control signal generating circuit in FIG. FIG. 4 is a circuit diagram showing a detection circuit in the AGC circuit, and FIG. 5 is a circuit diagram showing a detection circuit of the conventional sampling AGC circuit. 1 ... Variable gain circuit, 2 ... Analog / digital converter, 3
...... Sampling switch, 4 ...... Digital-to-analog converter, 5 ...... Address counter, 6 ...... Memory, 7 ...... Detection circuit, 8 ...... Low pass filter, 9 ...... Control signal generation circuit, 10
…… Signal input terminal, 11 …… External control signal input terminal, 12 ……
Signal output terminal.

Claims (2)

[Claims] 1. A variable gain circuit having an analog signal including a burst signal having a constant period and a reference level as an input signal, and detecting a level of the burst signal included in an output signal of the variable gain circuit, And a gain control means for forming a gain control signal of the variable gain circuit according to the detected level, and a sampling AGC circuit for controlling the output signal of the variable gain circuit so that the level of the burst signal becomes constant. In the gain control means, means for converting a part of the input signal from an analog signal to a digital signal, means for extracting the burst signal from the signal digitally converted by the means, and extraction by the means Means for recording the digitized digitized burst signal in a memory, and controlling the reading of the burst signal from the memory, Sampling the AGC circuit, characterized means for obtaining repeatedly read continuously signal the door signal, that is configured to include a means for converting the analog signal to consecutive reproduced signal by said means. 2. A variable gain circuit according to claim 1, wherein an input signal of the variable gain circuit is a reproduction signal from an optical disk, and a burst signal is detected with reference to a synchronization signal included in the reproduction signal. Sampling AGC circuit.