JPH0119657B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase comparator, which detects the center of the dynamic range of a sampled signal created from a reference signal by detecting a position detection signal (hereinafter referred to as a PG signal) from a rotating body. It is highly effective to use as a phase comparator used in a rotation control system that samples the rotating body by the reference signal and uses the sampled error signal to phase-synchronize the rotating body with the reference signal. In a magnetic recording/reproducing device (VTR), the PG signal detected from the rotating head cylinder is used as a head switching signal, so it is necessary to position the screen junction, which tends to be disturbed when switching two heads, at the bottom of the screen. There is a need for the PG signal to have a certain phase difference with respect to the reference signal.

Figure 1 is a block diagram showing the configuration of a phase comparator for a VTR that has already been proposed, where 1 is a monostable multivibrator (hereinafter referred to as mono-multi), 2 is a trapezoidal wave generating circuit, and 3 is a sample hold. It is a circuit. FIG. 2 is a waveform diagram of each part of the phase comparator shown in FIG. 1, and the operation of the conventional phase comparator shown in FIG. 1 will be explained with reference to FIG.

The reference signal, that is, the vertical synchronizing signal _S3 separated from the video signal during recording, is input to the trapezoidal wave generation circuit 2, which generates a trapezoidal wave-shaped sampled signal _S4 (30Hz).
is created and input to the sample hold circuit 3. On the other hand, PG signal S ₁ that detects the rotational phase of the rotating body
triggers the monomulti 1, and the falling output of the monomulti 1 samples the center of the slope of the sampled signal _S4 .
Obtain the error signal _S5 . In other words, the operating point of the drive circuit (not shown) that receives the output of the phase comparator in FIG. 1 and drives the rotating body is generally set at the center of the dynamic range of the output of the phase comparator. The phase pull-in position is near the center of the slope of the sampled signal _S4 . The phase difference α between the PG signal S ₁ and the vertical synchronization signal S ₃ at this time is α=τ ₁ −τ ₂ /2. Here, τ ₁ is the delay amount of the monomulti 1, and τ ₂ is the slope period of the sampled signal S ₄ .

In order to keep the phase difference α constant, this conventional phase comparator has the following drawbacks.

1 Since the slope period τ ₂ of the sampled signal S ₄ varies depending on the resistor and capacitor that make up the trapezoidal wave generation circuit 2, it is necessary to adjust the delay amount τ ₁ of the monomulti 1 in order to keep the phase difference α constant. .

2. Since resistors and capacitors have temperature characteristics, the above τ ₁ and τ ₂ change with temperature changes, and therefore α changes.

3. It is not suitable for integrated circuits because it requires a resistor, capacitor, and volume.

The present invention provides a phase comparator that can solve the drawbacks of the conventional example.

FIG. 3 shows an embodiment of the phase comparator according to the present invention, where 4 is a timing pulse generation circuit, 5 is an m-bit binary counter, 6 is a count value detection circuit 61, and 2 is an m-bit binary counter.
A count detection block consisting of two RS flip-flops 62 and 63; 7 is an n-stage gate group in which two NAND gate circuits (for example, 71 and 72 in the figure) are connected in series to form one bit; 8; is an n-bit register.

FIG. 4 is an operational waveform diagram of each part of the digital phase comparator shown in FIG. 3, where _S8 represents the counting operation of the m-bit binary counter 5, _S10 represents the output of the n-stage gate group,
_S11 is an analog representation of the output of the n-bit register 8.

Timing pulse generation circuit 4 is a clock pulse
_S6 is used to generate a signal _S7 synchronized with the reference signal (vertical synchronization signal) _S3 . That is, a signal synchronized with the first clock pulse _S6 after the reference signal _S3 is input is generated every other pulse. Therefore, the relationship between the frequency _v (Hz) of the vertical synchronization signal _S3 ) and the signal _S7 (referred to as _REF (Hz)) serving as a reference signal for phase comparison is _REF = _v /2. The signal _S7 is a preset pulse for presetting the m-bit binary counter 5 to a predetermined count value No. (No. is an integer value including 0).
In the counting operation of the m-bit binary counter 5, as shown in FIG. 4, the count value is set to No by the preset pulse _S7 , and immediately thereafter counting is started by the clock pulse _S6 . The counting operation is performed until the next preset pulse _S7 is input, and the above operation is repeated. The count value detection block 6 detects whether the count value of the m-bit binary counter 5 is determined by the count value detection circuit 61 to a predetermined count value No.
It detects that Na and Nb have become Na and Nb, generates detection signals S ₉₃ , S ₉₄ , and S ₉₅ in response to each detection, and generates a gate signal by two RS flip-flops 62 and 63 that receive these signals as input. Create S ₉₁ and S ₉₂ . In the n-stage gate group 7, the low level (hereinafter referred to as L level) of the gate signal _S92 causes the n NAND gate circuits 72, 7 to
The outputs of 4, . . . , 76 all become L level, that is, 0 (zero), and due to the L level of the gate signal S ₉₁ and the high level (hereinafter referred to as H level) of the gate signal S ₉₂ , n NAND The outputs of the gate circuits 71, 73, . . . 75 are all at L level, and the n NAND gate circuits 72, 74, .
All outputs of 76 are at H level, that is,
2 ^(n-1) , and due to the H level of the gate signal S ₉₁ and the H level of the gate signal S ₉₂ , n
The count value of the lower n bits of the m-bit binary counter 5 is outputted from _the NAND gate circuits 72, 74, .

That is, between the pulse of the signal S ₉₃ corresponding to the count value No. and the pulse of the signal S ₉₄ corresponding to the count value Na, the n-stage gate group 7 is shut off and 0 is output, corresponding to the count value Na. Between the pulse of the signal S ₉₄ and the pulse of the signal S ₉₅ corresponding to the count value Nb, the above n
The m-bit binary counter 5 is connected to the gate group 7 of the stage.
The count value from 0 to 2 ^(n-1) is output as the count value of the lower n bits, and the signal corresponding to the count value Nb is output.
Between the pulse of S ₉₅ and the pulse of signal S ₉₃ corresponding to the count value No., the n-stage gate group 7 is shut off.
2 ^(n-1) is configured to be output. The reason why the sampled signal is a trapezoidal wave is that the gain required for the phase comparator is determined by the gain distribution of the entire control system, and there is also a limit to the dynamic range allowed for the output of this phase comparator. It's for a reason.

By sampling this trapezoidal wave, that is, the sampled signal S ₁₀ , near the center of the inclined part, that is, near the center of the dynamic range, using the PG signal S ₁ detected from the rotating body, an error signal S ₁₁ is obtained. control. In other words,
The operating point of a drive circuit (not shown) that receives the output of this phase comparator and drives the rotating body is generally set at the center of the dynamic range of the output of this phase comparator, and the phase pull-in position is This is near the center of the slope of the sampled signal _S10 .

At this time, the period τ _a from the preset pulse S ₇ to the center of the dynamic range of the sampled signal S ₁₀ in the sampled signal S ₁₀ is set to τ _a = 1/ _V − α, and the period τ a from the center of the dynamic range to the next If the period τ _b up to the preset pulse S7 is set to τ _b =1/ _V + α, the PG signal S ₁ and the reference signal, that is, the vertical synchronizing signal S ₃ can be set to have a constant phase difference α (sec).

Regarding the setting method of τ _a and τ _b , for example, the count value Nc of the m-bit binary counter 5 corresponding to the center of the dynamic range of the sampled signal S ₁₀ is calculated as follows: Nc = _CK (1/ _V - α) + No If so, the above purpose can be achieved.

As explained above, according to the present invention, all the configurations are digitalized, so there is no need to adjust the phase difference α as in the conventional method, and the disadvantage that the phase difference α changes due to temperature changes can also be eliminated. It has features such as no need for a volume and is suitable for integrated circuits, and the expected effects are tremendous.

[Brief explanation of drawings]

Figure 1 is a block diagram showing a conventional phase comparator.
FIG. 2 is an operating waveform diagram of each part, and FIG. 3 is a block diagram showing an embodiment of the phase comparator according to the present invention.
FIG. 4 is a diagram of its operating waveforms. 4... Timing pulse generation circuit, 5... m-bit binary counter, 6... Count value detection block,
7...n-stage gate group, 8...n-bit register.

Claims (1)

[Claims] 1. Counting means for sequentially counting clock signals of a constant frequency ( _CK (Hz)) and a clock signal of a constant frequency ( _REF (Hz))
means for presetting the count value of the counting means to a predetermined first count value No. by a reference signal;
Second count value Na, third count value Nb (No<Na<
count value detection means that generates first, second, and third pulses when reaching Nb), and count value detection means that corresponds to the second count value Na from generation of the first pulse to generation of the second pulse. generates an output, generates a numerical output of the counting means from the second pulse generation to the third pulse generation time, and generates the third counted value from the third pulse generation to the first pulse generation time;
It has gate means for generating an output corresponding to Nb, and means for sampling the output of the gate means with a signal to be compared, and outputs the output of the sampling means as a phase difference between the signal to be compared and the reference signal. A phase comparator having the first count value No, the second count value Na, and the third count value Nb.
The phase difference between the reference signal and the signal to be compared is set to α (sec) by setting the relationship as |No−(Na+Nb)/2| = _CK (1/2 _REF −α). phase comparator.