JPH03136254A - Die bonding - Google Patents
Die bondingInfo
- Publication number
- JPH03136254A JPH03136254A JP27410589A JP27410589A JPH03136254A JP H03136254 A JPH03136254 A JP H03136254A JP 27410589 A JP27410589 A JP 27410589A JP 27410589 A JP27410589 A JP 27410589A JP H03136254 A JPH03136254 A JP H03136254A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- heat sink
- molten solder
- collet
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 230000000694 effects Effects 0.000 description 3
- 238000005201 scrubbing Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000003028 elevating effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/75301—Bonding head
- H01L2224/75302—Shape
- H01L2224/75303—Shape of the pressing surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、熱的影響を受けやすいパワーモジニールなど
の製造過程において、半導体チップなどをヒートシンク
上にダイボンディングする方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for die bonding semiconductor chips and the like onto a heat sink during the manufacturing process of power modules and the like which are susceptible to thermal effects.
従来の技術
従来から、熱的影響を受けやすいチップのダイボンディ
ングにおいては、ヒートシンクとの接合に高温はんだが
必要であった。そして材料の酸化を防ぐために還元雰囲
気中ではんだを溶融させた状態でヒートシンクに滴下し
、コレットに吸着させた半導体チップをはんだ上でスク
ラブすることによりヒートシンクとチップを接合してい
た。BACKGROUND OF THE INVENTION Conventionally, die bonding of chips that are susceptible to thermal effects has required high-temperature solder to bond them to a heat sink. To prevent oxidation of the material, melted solder was dropped onto the heat sink in a reducing atmosphere, and the semiconductor chip adsorbed to the collet was scrubbed over the solder to join the heat sink and the chip.
以下図面を参照しながら説明する。第３図ａ。This will be explained below with reference to the drawings. Figure 3a.
ｂにおいて、１１はヒートシンク、１２は前工程におい
てヒートシンク１１上に滴下された溶融はんだ、１３は
半導体チップ、１４はチップ１３を吸着するための貫通
孔１５を備え、かつ昇降機能およびスクラブ機能を持つ
コレットである。溶融はんだ１２が滴下され、チップ１
３がダイボンディングされる工程は３００℃〜４００℃
の高温となっている。そして材料の酸化を防ぐため、こ
れらの工程はすべて還元雰囲気中で行われる。第３図ａ
、ｂに示したように吸着されたチップ１３は、溶融はん
だ１２が滴下されたヒートシンク１１の上方から降下し
、はんだ１２がチップ１３の裏面全体に広がるように、
また気泡などを巻きこまないようにはんだ１２上で第３
図すに矢印で示した方向にスクラブし接合するものであ
る。In b, 11 is a heat sink, 12 is molten solder dropped onto the heat sink 11 in the previous process, 13 is a semiconductor chip, 14 is equipped with a through hole 15 for adsorbing the chip 13, and has an elevating function and a scrubbing function. It's Colette. Molten solder 12 is dropped onto chip 1.
3 is die bonded at 300°C to 400°C
The temperature is high. All of these steps are performed in a reducing atmosphere to prevent oxidation of the materials. Figure 3a
, b, the adsorbed chip 13 descends from above the heat sink 11 onto which the molten solder 12 has been dropped, so that the solder 12 spreads over the entire back surface of the chip 13.
Also, place the third layer on the solder 12 to prevent air bubbles from being drawn in.
The bonding is performed by scrubbing in the direction shown by the arrow in the figure.
発明が解決しようとする課題
しかしながら、上記に示した従来の方法ではスクラブの
方向が一方向であるため、チップ裏面全体にはんだがま
わりにくく、とくに気泡を巻こんだ場合チップの駆動時
にこの部分が異常の高温となり最終的にはチップ破壊と
なるという問題があった。Problems to be Solved by the Invention However, in the conventional method shown above, the direction of scrubbing is unidirectional, so it is difficult to spread the solder over the entire back surface of the chip, and especially if air bubbles are involved, this area may be damaged when the chip is driven. There was a problem that the temperature would become abnormally high and eventually the chip would break.
課題を解決するための手段
本発明は上記課題を解決するため、ヒートシンクに滴下
された溶融はんだ上で、コレットに吸着されたチップを
回転させることにより接合するものとした。Means for Solving the Problems In order to solve the above problems, the present invention is designed to join chips by rotating a chip attracted to a collet over molten solder that has been dropped onto a heat sink.
作 用
本発明は上記方法においてヒートシンクの溶融はんだを
半導体チップの裏面全体にはんだをまわすことができ、
気泡等を巻こみにくく完全な接合ができる。Function The present invention can spread the molten solder of the heat sink over the entire back surface of the semiconductor chip in the above method,
Perfect bonding is possible without the inclusion of air bubbles, etc.
実 施 例
以下、本発明の一実施例におけるダイボンディング方法
について、図面を参照しながら説明する。EXAMPLE Hereinafter, a die bonding method in an example of the present invention will be described with reference to the drawings.
第１図は、本発明実施例におけるダイボンディングの様
子を示したものである。第１図において、ｌは半導体チ
ップ、２はこのチップ１を吸着するコレット、３は溶融
はんだ、４はヒートシンクである。コレット２は、昇降
機能および回転機能をもっている。また、これらの工程
はすべて還元雰囲気中で行われるものである。FIG. 1 shows the state of die bonding in an embodiment of the present invention. In FIG. 1, 1 is a semiconductor chip, 2 is a collet that attracts the chip 1, 3 is molten solder, and 4 is a heat sink. The collet 2 has a lifting function and a rotating function. Furthermore, all of these steps are performed in a reducing atmosphere.
このような構成のもとて工程を模式的に示した第２図ａ
−ｅを用いて説明する。溶融はんだ３がヒートシンク４
に滴下された後、チップ１がコレット２に吸着された状
態で前記ヒートシンク４上に下降する。チップ１が溶融
はんだ３に接した状態でコレット２が回転（第２図ｄ）
することにより、はんだ３がチップ１の裏面全体にいき
わたり十分な接合が完了する。Figure 2a schematically shows the process with such a configuration.
This will be explained using -e. Molten solder 3 is heat sink 4
After being dropped, the chip 1 is lowered onto the heat sink 4 while being attracted to the collet 2. Collet 2 rotates with chip 1 in contact with molten solder 3 (Figure 2 d)
By doing so, the solder 3 spreads over the entire back surface of the chip 1, and sufficient bonding is completed.
発明の効果
本発明によれば、ダイボンディング時チップが回転しな
がらはんだをまきこむため、はんだがチップ裏面全体に
まわり、気泡を巻きこむことがなく十分に安定した接合
を行うことができる。Effects of the Invention According to the present invention, since the solder is applied while the chip rotates during die bonding, the solder covers the entire back surface of the chip, and a sufficiently stable bond can be achieved without entraining air bubbles.
はそのダイボンディング方法を示す工程図、第３図ａ、
ｂは従来例の説明図である。
１・・・・・・半導体チップ、２・・・・・・コレット
、３・・・・・・溶融はんだ、４・・・・・・ヒートシ
ンク。are process diagrams showing the die bonding method, FIG. 3a,
b is an explanatory diagram of a conventional example. 1... Semiconductor chip, 2... Collet, 3... Molten solder, 4... Heat sink.
Claims (1)
ング時、ヒートシンク上に滴下された溶融はんだ上で、
コレットに吸着されたチップを回転させてこのチップを
前記ヒートシンクに接合することを特徴とするダイボン
ディング方法。When die bonding onto a heat sink such as a semiconductor chip, the molten solder dripped onto the heat sink
A die bonding method characterized in that the chip adsorbed by the collet is rotated and the chip is joined to the heat sink.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27410589A JP2738070B2 (en) | 1989-10-20 | 1989-10-20 | Die bonding method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27410589A JP2738070B2 (en) | 1989-10-20 | 1989-10-20 | Die bonding method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03136254A true JPH03136254A (en) | 1991-06-11 |
| JP2738070B2 JP2738070B2 (en) | 1998-04-08 |
Family
ID=17537074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27410589A Expired - Fee Related JP2738070B2 (en) | 1989-10-20 | 1989-10-20 | Die bonding method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2738070B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5770468A (en) * | 1993-01-12 | 1998-06-23 | Mitsubishi Denki Kabushiki Kaisha | Process for mounting a semiconductor chip to a chip carrier by exposing a solder layer to a reducing atmosphere |
-
1989
- 1989-10-20 JP JP27410589A patent/JP2738070B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5770468A (en) * | 1993-01-12 | 1998-06-23 | Mitsubishi Denki Kabushiki Kaisha | Process for mounting a semiconductor chip to a chip carrier by exposing a solder layer to a reducing atmosphere |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2738070B2 (en) | 1998-04-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |