JPS60160623A - Method and apparatus for manufacturing semiconductor device - Google Patents
Method and apparatus for manufacturing semiconductor deviceInfo
- Publication number
- JPS60160623A JPS60160623A JP1564284A JP1564284A JPS60160623A JP S60160623 A JPS60160623 A JP S60160623A JP 1564284 A JP1564284 A JP 1564284A JP 1564284 A JP1564284 A JP 1564284A JP S60160623 A JPS60160623 A JP S60160623A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- temperature
- semiconductor
- heater block
- melting material
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ）、発明の技術分野
本発明はＰ ＨＳ （Ｐｌａｔｅ Ｈｅａｔ ５ｉｎｋ
）構造の半導体チップを搭載した高電力の半導体装置
の製造方法および製造装置に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to PHS (Plate Heat 5ink)
The present invention relates to a method and apparatus for manufacturing a high-power semiconductor device equipped with a semiconductor chip having the above structure.
（ｂ）、技術の背景
ＰＨ５構造の半導体チップは熱抵抗の減少を目的として
考えられたものであり、小電力用の半導体装置では、既
に実用化されているが、長辺３〜４ｍｍ以上の大型半導
体チップでは反りが問題になり、マウントの際のハンド
リングが難しり、熱抵抗は半導体チップ内でバラツキを
生じた。そのため目的とした熱抵抗の減少は著しく阻害
される。(b), Background of the technology Semiconductor chips with a PH5 structure were designed to reduce thermal resistance, and have already been put into practical use in low-power semiconductor devices. Warping became a problem with large semiconductor chips, making them difficult to handle during mounting, and thermal resistance varied within the semiconductor chip. Therefore, the intended reduction in thermal resistance is significantly hindered.
（Ｃ）、従来技術と問題点
第１図はＰＨ５構造の半導体チップが温材によりパンケ
ージ上に溶着された状態を示す断面図である。図におい
て１は半導体薄層、２は金属プレート、３は温材、４は
パッケージを示す。(C), Prior Art and Problems FIG. 1 is a sectional view showing a state in which a PH5 structure semiconductor chip is welded onto a pan cage using a hot material. In the figure, 1 is a semiconductor thin layer, 2 is a metal plate, 3 is a hot material, and 4 is a package.
ＰＨ３構造の半導体チッブは、例えば半導体薄層として
厚さ２５〜３０μｍの珪素層を用い、金属プレートとし
て厚さ３５〜４０μｍの銀層を鍍金して構成される。こ
の場合被着をよくするためにニクロム等の薄層を介在さ
せる。銀層は半導体薄層より３５〜４５μｍ内側に形成
されている。A semiconductor chip having a PH3 structure is constructed by using, for example, a silicon layer with a thickness of 25 to 30 μm as a semiconductor thin layer and plating a silver layer with a thickness of 35 to 40 μm as a metal plate. In this case, a thin layer of nichrome or the like is interposed to improve adhesion. The silver layer is formed 35 to 45 μm inside the semiconductor thin layer.
これは、半導体ウェハを賽の目切断して半導体チップに
するときのスクライブ領域を見込んでいるためである。This is because the scribe area is taken into consideration when cutting the semiconductor wafer into dice to form semiconductor chips.
温材として金−珪素の共晶を用い、４００℃程度で溶融
させる。Gold-silicon eutectic is used as a hot material and melted at about 400°C.
図示されるように、温材の溶融温度より冷却されるとき
、珪素と銀の熱膨張係数の差により半導体チップは上方
に凹に反り、周辺に形成される素子の熱抵抗は大きくな
る。As shown in the figure, when cooled below the melting temperature of the hot material, the semiconductor chip warps upward due to the difference in thermal expansion coefficients between silicon and silver, and the thermal resistance of elements formed around it increases.
珪素は加熱されると電流増幅率、漏洩電流が増大して暴
走する方向に向かう。そのため定謬的な熱抵抗を下げる
外、熱による電流集中を避けなければならない。そのた
めエミッタに安定化抵抗を入れている。このような対策
を施していても、半導体チップの反りによる熱抵抗の増
加は、熱抵抗の減少を目的としたＰＨ３構造の半導体装
置にとっては大きな障害になっている。When silicon is heated, the current amplification factor and leakage current increase, leading to runaway. Therefore, in addition to lowering the conventional thermal resistance, it is necessary to avoid current concentration due to heat. Therefore, a stabilizing resistor is installed in the emitter. Even if such measures are taken, the increase in thermal resistance due to warpage of the semiconductor chip is a major obstacle for semiconductor devices with a PH3 structure whose purpose is to reduce thermal resistance.
（ｄ）８発明の目的
本発明の目的は従来技術の有する上記の欠点を除去し、
ＰＨ３構造の半導体チップの反りを防止して、ハンドリ
ングが容易で、かつ熱抵抗の増加のない半導体装置の製
造方法およびその装置を提供することにある。(d) 8 Objectives of the Invention The objectives of the present invention are to eliminate the above-mentioned drawbacks of the prior art;
It is an object of the present invention to provide a method and apparatus for manufacturing a semiconductor device that prevents warping of a semiconductor chip having a PH3 structure, is easy to handle, and does not increase thermal resistance.
（ｅ）０発明の構成
上記の目的は本発明によれば、
１）半導体薄層上に金属プレートを被着してなるＰＨ３
構造の半導体チップを、該半導体チップが平坦になるよ
うな温度に保持された第１のヒータブロック上に載せて
加熱する工程と、該半導体チップをパンケージにマウン
トするための温材の溶融温度より低い温度に設定された
第２のヒータブロック上に、パッケージと温材を載せ熱
ガスを吹きつけて該温材を溶融させ、該半導体チップを
金属プレート側を密着して該温材上に載せる工程と、該
半導体チップを平坦な板で圧しつけながら冷ガスを吹き
つけて温材を溶着させる工程を有することを特徴とする
半導体装置の製造方法。(e) 0 Structure of the Invention According to the present invention, the above objects are as follows: 1) PH3 formed by depositing a metal plate on a semiconductor thin layer;
heating the semiconductor chip by placing it on a first heater block maintained at a temperature such that the semiconductor chip becomes flat; Place the package and hot material on a second heater block set at a low temperature, blow hot gas to melt the hot material, and place the semiconductor chip on the hot material with the metal plate side in close contact. 1. A method of manufacturing a semiconductor device, comprising: a step of pressing the semiconductor chip with a flat plate and blowing cold gas to weld the hot material.
２）ＰＨ３構造の半導体チップが平坦になるような温度
に保持された第１のヒータブロックと、温材の溶融温度
より低い温度に設定された第２のヒータブロックと、該
第２のヒータブロックにガスを吹きつけるノズルと、半
導体チップを吸着するグイ・コレットと、半導体チップ
を圧しつけるグイ・コレットとを設けてなることを特徴
とする半導体装置の製造装置。2) A first heater block maintained at a temperature such that a semiconductor chip with a PH3 structure becomes flat, a second heater block set at a temperature lower than the melting temperature of the hot material, and the second heater block. 1. A device for manufacturing a semiconductor device, comprising: a nozzle for blowing gas onto a semiconductor chip; a gouie collet for adsorbing a semiconductor chip; and a gooey collet for pressing a semiconductor chip.
を提供することによって達成される。This is achieved by providing
ＰＨ３構造の半導体チップは、その形成過程の熱経歴に
より普通當温では上方に凸となっている。A semiconductor chip with a PH3 structure normally has an upward convex shape at a normal temperature due to the thermal history during its formation process.
そのため半導体チップの吸着−が難しくなる。半導体チ
ップの温度を上げてゆくと、ある温度で半導体チップは
平坦になり、それ以上の温度では上方に凹となる。この
半導体チップが平坦になる温度は一般に温材の固化温度
より低いため、半導体チップは上方に凹となった状態で
パンケージに溶着される。This makes it difficult to adsorb semiconductor chips. As the temperature of the semiconductor chip is increased, the semiconductor chip becomes flat at a certain temperature, and becomes concave upward at higher temperatures. Since the temperature at which the semiconductor chip becomes flat is generally lower than the solidification temperature of the hot material, the semiconductor chip is welded to the pan cage in an upwardly concave state.
本発明は半導体チップの反りの温度依存を調べ、半導体
チップが平坦になるような温度で、半導体チップを吸着
してハンドリングを行い、パンケージに半導体チップを
溶着する際、半導体装ノブを強制的に圧着したまま冷却
溶着することにより、半導体チップの反りを防止するも
のである。The present invention investigates the temperature dependence of semiconductor chip warpage, suctions and handles the semiconductor chip at a temperature that makes the semiconductor chip flat, and forces the semiconductor mounting knob when welding the semiconductor chip to the pancage. By cooling and welding the semiconductor chip while it is being crimped, warping of the semiconductor chip is prevented.
（ｆ）０発明の実施例 第２図は本発明の実施例を模式的に示す工程図である。(f) 0 Examples of the invention FIG. 2 is a process diagram schematically showing an example of the present invention.
図で２１は第１のグイ・コレット、２２はＰＨ３構造の
半導体チップ、２３は鏡面板、２４は第１のヒータブロ
ック、２５はパンケージ、２６は第２のヒータブロック
、２７は温材、２８はノズル、２９は第２のグイ・コレ
ットを示す。In the figure, 21 is the first Gouy colette, 22 is a PH3 structure semiconductor chip, 23 is a mirror plate, 24 is the first heater block, 25 is the pan cage, 26 is the second heater block, 27 is the hot material, 28 indicates a nozzle, and 29 indicates a second Goui collet.
第２図（ａ）において、ＰＨ３構造の半導体チップ２２
が、その形状が平坦になるような温度に設定された第１
のヒータブロック２４の上に載せられた鏡面板２３の上
に置かれる。この温度はＰＨ３構造の材質と寸法によっ
て異なるが、例えば１００±１５℃に設定する。同じ温
度に加熱された真空吸引型の第１のグイ・コレット２１
により半導体チ・２プ２２を吸着する。この際半導体チ
ップ２２は平坦になっているため容易に、確実に吸着で
きる。In FIG. 2(a), a semiconductor chip 22 with a PH3 structure
The first temperature is set at such a temperature that the shape becomes flat.
It is placed on a mirror plate 23 placed on a heater block 24 of. This temperature varies depending on the material and dimensions of the PH3 structure, but is set to, for example, 100±15°C. Vacuum suction type first goui colette 21 heated to the same temperature
The semiconductor chip 22 is attracted by the semiconductor chip 22. At this time, since the semiconductor chip 22 is flat, it can be easily and reliably attracted.
つぎに第２図ｆｂｌにおいて、温材として金−珪素の共
晶を用い、温材の溶融温度より低い温度３５０℃に設定
された第２のヒータブロック２６上にパッケージ２５と
温材２７を載せ、熱窒素をノズル２８より吹きつけて約
４００℃に加熱し該温材を溶融させる。Next, in FIG. 2fbl, the package 25 and the hot material 27 are placed on the second heater block 26, which uses gold-silicon eutectic as the hot material and is set at a temperature of 350°C lower than the melting temperature of the hot material. , hot nitrogen is blown from the nozzle 28 and heated to about 400° C. to melt the hot material.
第２図（Ｃ１において、第２図（ａｌで第１のグイ・コ
レット２１により吸着された半導体チップ２２を、第２
図Ｔｂ）で温材を溶融させた状態のパンケージ２５上の
所定の位置に持ってきて金属プレート側を温材に密着し
て擦りつける。この工程中も第２のヒータブロック２６
は３５０℃に保たれ、温材に熱窒素を吹きつけて約４０
０℃に加熱し度１さ廿ておく。In FIG. 2 (C1), the semiconductor chip 22 adsorbed by the first Goui collet 21 in FIG.
In Figure Tb), the hot material is brought to a predetermined position on the molten pan cage 25, and the metal plate side is rubbed against the hot material in close contact with it. During this process, the second heater block 26
was kept at 350℃, and hot nitrogen was blown onto the heated material for about 40℃.
Heat to 0℃ and leave for 1 degree.
第２図（ｄｌにおいて、第２のグイ・コレット２９が、
第１のグイ・コレット２１に代わって半導体チップ２２
全面を上方より一定圧力で圧さえつけると同時に、ノズ
ル２８より冷窒素を送りこみ冷却する。この工程中も第
２のヒータブロック２６は３５０℃に保っておく。In Figure 2 (dl), the second Gouy Colette 29 is
Semiconductor chip 22 replaces first Gouy colette 21
While applying constant pressure to the entire surface from above, cold nitrogen is sent in from the nozzle 28 to cool it down. The second heater block 26 is maintained at 350° C. during this step as well.
このようにすると、半導体チップ２２は極めて平坦な状
態で溶着できる。In this way, the semiconductor chip 22 can be welded in an extremely flat state.
本発明の実施例では半導体として珪素、金属プレートと
して銀、ノズルより吹きつけるガスに窒素を用いたが、
これらを他の材料に変えても発明の要旨は変わらない。In the embodiment of the present invention, silicon was used as the semiconductor, silver was used as the metal plate, and nitrogen was used as the gas blown from the nozzle.
Even if these materials are replaced with other materials, the gist of the invention does not change.
ｔｇ＞、発明の効果
以上詳細に説明したように本発明によれば、ＰＨ５構造
の半導体チップの反りを防止して、ハンドリングが容易
で、かつ熱抵抗の増加のない半導体装置の製造方法およ
びその装置を提供することができる。tg>, Effects of the Invention As described in detail above, the present invention provides a method for manufacturing a semiconductor device that prevents warping of a semiconductor chip having a PH5 structure, is easy to handle, and does not increase thermal resistance, and the method thereof. equipment can be provided.
即ちＰＨ３構造のもつ有利性を生かし、低熱抵抗の半導
体装置が得られる。That is, by taking advantage of the advantages of the PH3 structure, a semiconductor device with low thermal resistance can be obtained.
第１図はＰＨ３構造の半導体チーツブがパッケージ上に
溶着された状態を示す断面図、第２図は本発明の実施例
を模式的に示す工程図である。
図において１は半導体薄層、２は金属プレート、３は温
材、４はパッケージ、２１は第１のグイ・コレット、２
２はＰＨ３構造の半導体チップ、２３は鏡面板、２４は
第１のヒータブロック、２５はパンケージ、２６は第２
のヒータブロック、２７は溶料、２８はノズル、２９は
第２のグイ・コレットを示す。
第２図 ′FIG. 1 is a sectional view showing a state in which a semiconductor chip having a PH3 structure is welded onto a package, and FIG. 2 is a process diagram schematically showing an embodiment of the present invention. In the figure, 1 is a semiconductor thin layer, 2 is a metal plate, 3 is a hot material, 4 is a package, 21 is a first Gouy collet, 2
2 is a semiconductor chip with PH3 structure, 23 is a mirror plate, 24 is a first heater block, 25 is a pan cage, and 26 is a second
, 27 is a solvent, 28 is a nozzle, and 29 is a second Gouy collet. Figure 2 ′
Claims (1)
構造の半導体チップを、該半導体チップが平坦になるよ
うな温度に保持された第１のヒータブロック上に載せて
加熱する工程と、該半導体チップをパッケージにマウン
トするための博打の溶融温度より低い温度に設定された
第２のヒータブロソ″り上に、パンケージと博打を載せ
熱ガスを吹きつけて該温材を溶融させ、該半導体チップ
を金属プレート側を密着して該温材上に載せる工程と、
該半導体チップを平坦な板で圧しつけながら冷ガスを吹
きつけて博打を溶着させる工程を有することを特徴とす
る半導体装置の製造方法。 ２）ＰＨ３構造の半導体チップが平坦になるような温度
に保持された第１のヒータブロックと、博打の溶融温度
より低い温度に設定された第２のヒータブロックと、該
第２のヒータブロックにガスを吹きつけるノズルと、半
導体チップを吸着するグイ・コレットと、半導体チップ
を圧しつけるグイ・コレットとを設けてなることを特徴
とする半導体装置の製造装置。[Claims] 1) PH3 formed by depositing a metal plate on a semiconductor thin layer
placing and heating a semiconductor chip of the structure on a first heater block maintained at a temperature such that the semiconductor chip is flattened; A process of placing the pan cage and gambling machine on the second heater broth set at a certain temperature, blowing hot gas to melt the heating material, and placing the semiconductor chip on the heating material with the metal plate side in close contact. and,
A method for manufacturing a semiconductor device, comprising the step of welding the semiconductor chip by blowing cold gas while pressing the semiconductor chip with a flat plate. 2) A first heater block maintained at a temperature such that a semiconductor chip with a PH3 structure becomes flat; a second heater block set at a temperature lower than the melting temperature of the gambling; A device for manufacturing a semiconductor device, comprising a nozzle for blowing gas, a gouly collet for adsorbing a semiconductor chip, and a gouly collet for pressing the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1564284A JPS60160623A (en) | 1984-01-31 | 1984-01-31 | Method and apparatus for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1564284A JPS60160623A (en) | 1984-01-31 | 1984-01-31 | Method and apparatus for manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60160623A true JPS60160623A (en) | 1985-08-22 |
Family
ID=11894367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1564284A Pending JPS60160623A (en) | 1984-01-31 | 1984-01-31 | Method and apparatus for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60160623A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5770468A (en) * | 1993-01-12 | 1998-06-23 | Mitsubishi Denki Kabushiki Kaisha | Process for mounting a semiconductor chip to a chip carrier by exposing a solder layer to a reducing atmosphere |
| US6133071A (en) * | 1997-10-15 | 2000-10-17 | Nec Corporation | Semiconductor device with plate heat sink free from cracks due to thermal stress and process for assembling it with package |
| CN107316820A (en) * | 2017-06-22 | 2017-11-03 | 中科迪高微波系统有限公司 | A kind of process of microwave chip eutectic welding |
-
1984
- 1984-01-31 JP JP1564284A patent/JPS60160623A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5770468A (en) * | 1993-01-12 | 1998-06-23 | Mitsubishi Denki Kabushiki Kaisha | Process for mounting a semiconductor chip to a chip carrier by exposing a solder layer to a reducing atmosphere |
| US6133071A (en) * | 1997-10-15 | 2000-10-17 | Nec Corporation | Semiconductor device with plate heat sink free from cracks due to thermal stress and process for assembling it with package |
| CN107316820A (en) * | 2017-06-22 | 2017-11-03 | 中科迪高微波系统有限公司 | A kind of process of microwave chip eutectic welding |
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