JPH03134753A - Multistage data buffer transfer circuit - Google Patents

Abstract

PURPOSE:To execute the data transfer at a high speed by processing the data of a buffer having a dead part on an output side so that the data can be transferred simultaneously to order buffers. CONSTITUTION:The above circuit is provided with a first logical gate 3 for displaying whether a dead part exists in a buffer 2 position in an output side from its buffer 2 or not with respect to the buffer 2 of each stage, a second logical gate 4 for generating a data transfer signal for instructing a transfer to an order buffer of data of the buffer 2 having a dead part on the output side. Accordingly, the transfer to the order buffer 2 of the data of the buffer 2 having the dead part on the output side can be executed simultaneously. In such a way, in a multistage data buffer transfer circuit 1, the data transfer can be executed in a short transfer time.

Description

[Detailed Description of the Invention] [Summary] An object of the present invention is to enable data transfer in a short transfer time, regarding a multi-stage data buffer transfer circuit that processes manually input data by sequentially launching it and transferring it to the output side. and a first logic gate that displays for each stage of buffer whether or not there is an empty buffer located on the output side of the buffer; , and a second logic gate that generates a data transfer signal that instructs the transfer of data in a buffer with an empty space on the output side to the next stage buffer.

[Industrial application field]

The present invention relates to a multi-stage data buffer transfer circuit that sequentially latches manually input data and transfers it to an output side, and particularly relates to a multi-stage data buffer transfer circuit that can perform data transfer in a short transfer time. It is something.

In order to synchronize devices, a computer system is equipped with a multi-stage data buffer transfer circuit that is composed of multi-stage buffers and processes input data so that it is sequentially launched and transferred to the output side.

In this multi-stage data buffer transfer circuit, in order to improve the efficiency of data processing, it is necessary to take measures to realize data transfer in a short transfer time.

[Conventional technology]

Conventional multi-stage data buffer transfer circuits have adopted a configuration in which data transfer to the next-stage buffer is started after confirming that the next-stage buffer is empty.

That is, when the multi-stage data buffer transfer circuit 1 is composed of four buffers 2 (i-1 to i-4) as shown in FIG. 5, for example, as shown in the time chart of FIG. Assuming that buffer 2-L 2-2.2-3 is in use and buffer 2-4 is empty, first, time A is synchronized with the reference clock.
When the empty state of the buffer 2-4 is detected, a data transfer pulse ■ instructing data transfer from the buffer 2-3 to the buffer 2-4 is generated, and in accordance with this, the data transfer pulse is transferred from the buffer 2-3 to the buffer 2-4. When the data transfer is executed, the buffer 2-3 becomes empty, and then, when the empty state of the buffer 2-3 is detected at time B in synchronization with the reference clock, the data is transferred from the buffer 2-2. Buffer 2-3
A data transfer pulse ■ instructing data transfer to the buffer 2-2 is generated, and data transfer from the buffer 2-2 to the buffer 2-3 is executed in accordance with this pulse, so that the buffer 2-2 becomes empty, and then, Time C in synchronization with the reference clock
When the empty state of buffer 2-2 is detected, a data transfer pulse ■ instructing data transfer from buffer 2-1 to buffer 2-2 is generated, and in accordance with this, the data transfer pulse is transferred from buffer 2-1 to buffer 2-2. The processing was such that the buffer 2-1 becomes empty when the data transfer is executed.

FIG. 7 diagrammatically shows the data transfer procedure of the example explained in FIG. 6.

The purpose of the present invention is to provide a new multi-stage data buffer transfer circuit that allows the data transfer circuit to be used in a multi-stage data buffer transfer circuit.

[Problems to be Solved by the Invention] However, in the conventional technology that uses such a data transfer method, when performing data transfer, it is confirmed that the next stage's buffer is empty and the buffer of that stage is transferred. Since data transfer is performed sequentially, there is a problem in that it takes too much time to transfer data when the buffer is full of data. In other words, using the above example, it takes 3 steps to transfer the data in buffer 2-1 to the adjacent buffer 2-2 (if the data transfer time to the next stage is L, then 3 is the time). ) must also be followed. This problem becomes more serious as the number of buffer stages of the multi-stage data buffer transfer circuit 1 increases.

The present invention has been made in view of the above circumstances, and is capable of performing data transfer in a short transfer time.

In the figure, 1 is a multi-stage data buffer transfer circuit, 2-4 is a multi-stage buffer that constitutes the multi-stage data buffer transfer circuit 1 (2-1 is an input stage buffer, 2-n is an output stage buffer), and 3 is a multi-stage buffer. a first logic gate that indicates, for each stage of buffers 2-i, whether or not there is an empty buffer in the buffer 2-i located on the output side from the buffer 2-4; is a second logic gate, and in accordance with the display output of the first logic gate 3, data transfer is performed to instruct the transfer of the data of the buffer 2-4 which has free space on the output side to the next stage buffer 2-]. It generates a signal.

[Function] For example, as described above, when the multistage data buffer transfer circuit 1 is constituted by four bumps 72-i (i=1 to 4), for example, the buffer 2-1゜2-2.2- 3
Assuming that the buffer 2-4 is in use and the buffer 2-4 is free, in the present invention, three buffers 2-1.2-2.2-3 are connected to the output side according to the first logic gate 3. It is displayed that the buffer has free space. In response to this display output, the second logic gate 4 sends a data transfer instruction from the buffer 2-3 to the buffer 2-4, a data transfer instruction from the buffer 2-2 to the buffer 2-3, and a data transfer instruction from the buffer 2-1 to the buffer 2-1. A data transfer signal is generated to give a data transfer instruction to buffer 2-2. According to this data transfer signal, data is transferred from buffer 2-3 to buffer 2-4 and from buffer 2-2 to buffer 2-2, as shown in FIG. 3 and from buffer 2-1 to buffer 2-2.

As described above, according to the present invention, since the data in the buffer 2-4 with empty space on the output side is processed to be transferred to the next stage buffer 2-4 at once, the multi-stage data buffer transfer circuit 1, it becomes possible to execute data transfer at a significantly higher speed than before.

〔Example] Hereinafter, the present invention will be explained in detail according to examples.

FIG. 3 illustrates one embodiment of the present invention. This embodiment assumes a multistage data buffer transfer circuit 1 consisting of four stages of buffers, and the same components as those explained in FIG. 1 are indicated by the same symbols. Each buffer 2
-i (i=1 to 4) is composed of flip-flop circuits corresponding to the number of bits of data to be transferred.

The OR gate 5-1 is connected to the buffer 2- arranged in the output stage.
The operation flag 4 (represented by 84 F/E in the figure) is set to "0" when the buffer 2-4 is in the used state (FULL), and set to "1" when it is in the empty state (EMPTY). ) and the operation flag of the buffer 2-3 located adjacent to the buffer 2-4 (B in the figure).
3 F/E) and outputs the result, and the OR gate 5-2 outputs the operation flag of the buffer 2-2 arranged adjacent to the output of the OR gate 5-1 and the buffer 2-3. (82 F/E in the figure) and outputs the OR gate 5-3.
2 and the operation flag (BIF/E in the figure) of the input stage buffer 2-1 disposed adjacent to the buffer 2-1 and outputs the result.

Since it is configured in this way, buffer 2
-4 operation flag (B 4 F/E) is "1", that is, indicates an empty state, all OR gates 5-1.
5-2.5-3 outputs 1'', and buffer 2-3
When the operation flag (83F/E) represents “1”,
All the OR gates 5-1.5-25-3 output 1'', and the operation flag (B 2 F/
When E) represents °“1”, OR gate 5-2.5
-3 outputs "1" and when the operation flag (BI F/E) of buffer 2-1 indicates "1", only OR gate 5-3 operates to output "1". become.

On the other hand, the NAND gate 6-1 calculates the AND of the operation flag (84F/E) of the buffer 2-4 and the clock signal, and sends a clock signal (“0”) to the buffer 2-4 to instruct data transfer. NAN
The D gate 6-2 calculates the logical product of the output of the OR gate 5-1 and the clock signal, provides a clock signal for instructing data transfer to the buffer 2-3, and operates the NAND gate 6-2.
3 calculates the logical product of the output of the OR gate 5-2 and the clock signal to provide a clock signal for instructing data transfer to the buffer 2-2. The logical product of the output and the clock signal is calculated to provide a clock signal instructing data transfer to the buffer 2-1.

Preferably, a delay means 7-1 is provided to ensure that the clock signal for the data transfer instruction given to the buffer 2-3 lags behind the clock signal for the data transfer instruction given to the buffer 2-4; Buffer 2-
A delay means 7-2 is provided to ensure that the clock signal for the data transfer instruction given to the buffer 2-2 lags behind the clock signal for the data transfer instruction given to the buffer 2-3. Delay means 7-3 is provided to ensure that the transfer instruction clock signal lags behind the data transfer instruction clock signal applied to buffer 2-2.

Next, the operation processing of the embodiment of the present invention configured as described above will be explained.

For example, suppose buffer 2-1.2-2.2-3 is in use and buffer 2-4 is free.
Since the operation flag CB 4 F/E) of buffer 2-4 is in the empty state °1', all OR games) 5-1
．． 5-2.5-3 operates to output "1", and accordingly, when the clock signal (CLK in the figure) becomes "1", all NAND gates 6-1.6- 2.6
-3.6-4 outputs "0" at the same time.

When 0° is output from the NAND gate, buffer 2
-4 receives the "0" output from this NAND gate 6-1 and reads the launched data of the buffer 2-3, and the buffer 2-3 receives the "0" output from this NAND gate 6-2. Upon receiving the output, the data latched in buffer 2-2 is read, and buffer 2-2 reads this NAND
Buffer 2-1 receives “0” output from gate 6-3
Executes the process of reading the latched data. In this way, as shown in FIG.
Data transfer from -2 to buffer 2-3 and buffer 2-
Data transfer from buffer 1 to buffer 2-2 will be performed.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to transfer data in a buffer with free space on the output side to the next stage buffer all at once, and therefore, in a multi-stage data buffer transfer circuit, the data is significantly more efficient than the conventional one. This allows data transfer to be performed in a short transfer time.

[Brief explanation of the drawing]

Fig. 1 is a diagram of the principle configuration of the present invention, Fig. 2 is an explanatory diagram of the data transfer procedure of the present invention, Fig. 3 is an embodiment of the present invention, Fig. 4 is a time chart of data transfer of the present invention, FIG. 5 is an explanatory diagram of the prior art, FIG. 6 is a time chart of the conventional data transfer method, and FIG. 7 is an explanatory diagram of the data transfer procedure explained in FIG. 1 is a multi-stage data buffer transfer circuit, 2 is a -buffer, 3
is the first logic gate, 4 is the second logic gate, 5 is OR
6 is a NAND gate, and 7 is a delay means.

Claims (1)

[Claims] In a multi-stage data buffer transfer circuit that includes a multi-stage buffer and processes input data by sequentially latching it according to the multi-stage buffer and transferring it to the output side, , a first logic gate (3) that displays whether or not there is an empty buffer in the buffer located on the output side of the buffer; 1. A multi-stage data buffer transfer circuit comprising: a second logic gate (4) that generates a data transfer signal instructing the transfer of data in a buffer with space to a next-stage buffer.