JPH03129741A - Manufacture of mos-type semiconductor device - Google Patents

Abstract

PURPOSE:To accurately control a spread of a diffusion layer into a part directly under a gate and to form an effective channel length of high accuracy by a method wherein an insulating film with which a side face of the gate is covered is left as an insulating-film pattern, impurities are introduced into the surface of a substrate by making use of the gate and the insulating-film pattern as a mask and a source and a drain are formed. CONSTITUTION:A field oxide film 2 and a gate oxide film 3 are formed in desired positions of a silicon substrate. A polycrystalline silicon film 4 is deposited on them; a photoresist pattern 5 used to form a gate pattern is formed. The polycrystalline silicon film 4 is etched by making use of the photoresist pattern 5 as a mask. A silicon oxide film 6 is deposited on it. Then, an etching gas 50 is made incident nearly perpendicularly to the surface of the substrate 1; the oxide film 6 is removed selectively. After that, phosphorus or arsenic is introduced by making use of a gate 4' and an insulating-film pattern 6' as a mask; a source diffusion layer and a drain diffusion layer 7, 8 are formed. At this time, a junction depth is adjusted in such a way the a spread in a transverse direction of the diffusion layers 7 and 8 becomes larger than a width W of the oxide film pattern 6'.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a MOS type semiconductor device, and an object of the present invention is to provide an improved method of self-alignment process such as a silicon gate, and a novel structure based thereon.

In a normal self-alignment process, a gate pattern of, for example, polycrystalline silicon is formed on a semiconductor substrate via a gate insulating film, and impurities are introduced using the gate turn itself as a diffusion mask to form source/drain diffusion layers. The upper surface of the gate insulating film is covered with polycrystalline silicon, but the side surfaces are exposed to high concentrations of impurities. Although it is known that this causes a drop in the withstand voltage of the gate insulating film, this can be avoided by lowering the concentration of the diffusion layer.8 Doing so will cause other problems such as an increase in resistance.

If the width of the gate pattern in the source/drain direction, that is, the gate length, is LC, and the lateral extent of the source/drain diffusion layer is IJ, then the effective channel length L·11 between the source and drain is expressed by the following equation.

L-tt=Lc-2・lJ
(1) It goes without saying that the characteristics of a MOS field effect transistor are determined by the effective channel length L and t, and in order to make the characteristics uniform, it is necessary to form the effective channel length with high precision. (It is preferable to have a structure and manufacturing method that allows the effective channel length to be determined by as few factors as possible.) Formula (1)
- lJ<, 1. which means that ++ depends on two factors LC and IJ. It is better to reduce its contribution by reducing + to make it a one-factor type that depends almost only on Lc. However, when the source/drain diffusion layer is made shallow, electrode wiring penetration occurs and diffusion To prevent short circuits between layers and substrates, a method is used to form source/drain diffusion layers shallowly near the gate and deeply in the contact formation region with the electrode wiring. ) is required, and the relative position between the deep diffusion layer and the gate is determined by mask alignment, so it is necessary to leave some margin in the mask design. One solution that has been proposed in the past is to form a polycrystalline silicon gate pattern and then grow a thermal oxide film over the entire surface.The oxide film grows thicker on polycrystalline silicon than on a single crystal substrate. JP-A No. 52-22481 discloses a method that takes advantage of the fact that the polycrystalline silicon gate It is also possible to leave the oxide film only on the top of the gate.In this way, it is possible to cover the sides of the gate with the oxide film.It is also possible to protect the gate insulating film directly under the gate from being directly exposed to high concentration impurities. The thickness of the oxide film is determined by two factors: the growth conditions of the oxide film and the etching conditions, so it is difficult to form it precisely.Also, in thermal oxidation of polycrystalline silicon, the oxide film expands during growth. If the oxide film on the side of the gate is too thick, strain will be added to the vicinity of the gate, which is undesirable (~
On the other hand, if the gate is made thinner, the withstand voltage between the gate and the source/drain is too low to be of practical use. It is an object of the present invention to provide a method for easily manufacturing a semiconductor device with high accuracy and obtaining a high-density L-RI thin MOS transistor.

In order to achieve these objects, the method of the present invention (MOS on a semiconductor substrate) after providing a gate in the transistor formation area via a gate insulating film, the thickness of the film in the direction perpendicular to the substrate in the part covering the side surface of the gate is An insulating film that is thicker than the same film thickness in other parts is deposited on the surface where the M*S transistor type is formed.An etching agent is applied almost perpendicularly to the substrate to cover the entire surface of the insulating film in the formed part in a vertical direction. By dry etching a predetermined amount, the insulating film covering the side surface of the gate remains as an insulating film pattern, and using the gate and the insulating film pattern as a mask, impurities are introduced into the surface of the substrate to form a drain. This invention provides a method for forming a source or drain electrode on a source or drain adjacent to the above-mentioned insulating film pattern. First, FIG. show. As an example, an N-channel will be explained.<A) A field oxide film 2 for isolation between elements is formed at a desired position of a p-type (100) plane silicon substrate by a well-known selective oxidation method. is oxidized again to grow a gate oxide H3 with a thickness of approximately 1000 nm on the MOS transistor formation area.

(B) A polycrystalline silicon film 4 with a thickness of about 5 mm is deposited on this by a well-known vapor phase growth method.A photoresist pattern 5 for forming a gate pattern is formed by a photolithography method. C) Etch polycrystalline silicon 4 using photoresist pattern 5 as a mask. In this process, either dry etching using Freon-based gas or nitric-hydrofluoric acid-based chemical solution may be used. A gate 4' is formed from the polycrystalline silicon film 4, and the side surface 4°b of the gate 4' is a steep surface almost perpendicular to the surface of the substrate 1. Before proceeding, the gate oxide film 3 may be selectively removed using the gate 4' as a mask.Here, it is left as is.

(D) Insulating wind from above For example, silicon oxide film 6 is grown to a desired thickness by vapor phase growth, and as shown in the figure, the film thickness in the vertical direction of the substrate in the part covering the side of the gate is thicker than in the same part. The method of selecting conditions is such that the film thickness on horizontal surfaces such as the upper surface 4°a of the gate 4' and the gate oxide film 3 and the film thickness on the gate side surfaces 4'b are as similar as possible. For that purpose, low-pressure vapor-phase epitaxy using a gas pressure of about 1 torr is more suitable than atmospheric vapor-phase epitaxy. Etching gas 50 is introduced as an etching agent to oxidize IIl.
! 6 is selectively removed by dry etching, and this situation is shown in Figure 2 with an enlarged view of only the 4° gate area. - There are methods such as beam etching and sputtering, and methods such as reactive sputtering and plasma etching that mainly utilize the chemical reaction of Freon gas.The former method has low etching selectivity and is limited in its application. In plasma etching, which has no directivity in the direction of gas movement and etching proceeds in the same direction, in reactive sputtering, in which the sample is placed between two parallel electrodes (depending on the conditions, the surface of the substrate 1 is approximately Freon CF4 is used as the L1 gas, which is convenient for the present invention because it allows the etching gas to be incident vertically and has etching selectivity.
When the high-frequency power is 400 W with Teflon placed on the electrode at a gas pressure of about rr, the etching rate of the oxide film is about 900 people/min. The force t with which the etching gas is incident perpendicularly to the upper surface 4'a and the surfaces 6a and 6C of the oxide film 6 on the gate oxide film 3 is 4'. The inclined surface 6b, which is almost parallel to the side surface 4'b, is close to parallel to the direction of gas incidence, and the amount of gas incident per unit area is extremely small, resulting in a slow etching rate. Since the etching is slow, it almost moves to the right in the figure.Although the initial shapes of surfaces 6a, 6b, and 6c are almost maintained, they move in parallel downward. At the same time, etching progresses as shown by the dotted line, and if t3 is the time when the oxide film 6 is almost removed from the upper surface 4°a of the gate 4'', then the time when the oxide film 6 is left in the shape shown by 6' is t3. At or after t3, the dry etching is stopped to form a fine insulating film pattern 6° of oxide film that covers only the side surface 4'b of the gate 4' and the gate insulating film 3 in the vicinity thereof. The width W of the pattern 6' thus formed is approximately equal to the thickness of the oxide M6 on the gate side surface 4'b (°C (F)) After that, using the gate 4' and the insulating film pattern 6' as a mask, ion implantation or heat treatment is performed. The source/drain diffusion layers 7 and 8 are formed by introducing phosphorus or arsenic by a diffusion method. Adjust the welding depth so that it is larger than % l J.
＞W.

However, although contact electrodes are formed on the source/drain, the oxide film 6 is about 1 to 20% thinner on the gate side surface 4'b (as compared to that on the horizontal plane such as the gate upper surface 4'a). is almost fixed if the growth conditions of the oxide film are constant, so the width W of the fine pattern 6' can be controlled to a desired value by monitoring the film thickness on the horizontal plane. As is clear from the above, when forming the source/drain diffusion layers 7 and 8, the side surface 4' of the gate 4° is
Since b is covered by the oxide film pattern 6', the gate oxide film 3 is not directly exposed to high concentration impurities directly under the gate 4°. (1)
On the other hand, in the structure shown in Fig. 1, the following relationship is obtained: L-+ 2 ・W=L*+++ 2 ・I W) (
2) As mentioned above, IJ>W must be satisfied t,%. Otherwise, the gate 4'' and the diffusion layer 7.8 will be offset and normal characteristics will not be obtained (
1 Now, if we compare equation (2)′ with equation (1), we can see that it has a form in which (IJ-W) is substituted for IJ. Therefore, even if IJ is slightly larger than W, (IJ-W) is sufficiently small compared to the burr, and Llr is a one-factor type that depends almost only on l and o, and is highly accurate. This is especially important when the gate length 1.o is shortened. Since it is necessary to obtain L·tf with high precision because it depends on 2 as a mask, an impurity with a diffusion coefficient as small as possible, such as arsenic A1 or antimony Sb, is introduced into the substrate 1. This can be done by thermal diffusion, doped oxide, or ion implantation, as is well known. If high precision is required, the ion implantation method is preferable.The impurity concentration is about 1O''~101@cm-S, which is slightly lower than the source/drain diffusion layer that will be formed later. Shallow diffusion layer 1 that becomes part of the drain
3.13' is formed. This state is shown in Figure 2A.

Next, according to the steps of No. 1, E, and F in FIG. Since the shallow diffusion layer 13 contains impurities of the same conductivity type, they are electrically connected. The diffusion conditions are selected so that the lateral expansion of the diffusion layer 7.8 is smaller than the width W of the fine pattern 6' of the oxide film.The shallow diffusion layer 13.13' is also subjected to heat treatment in this process, so it is difficult to diffuse. As the depth increases, the diffusion coefficient of the impurity is small, so the downward spread I'J of the gate 4 is extremely small (1) This state is shown in FIG. 2B.

In this case, ler+ is expressed by the following equation.

L-tt= Lo-21'J (3
)Here, BiJ can be made extremely small, and L-++ is almost always Lo.The junction depth XJ of the drain diffusion layer 7.8 is shallower than that shown in Fig.
It is possible to make it as deep as possible to prevent the alloy reaction during electrode formation by making it as close to W as possible. For example, doped oxide containing arsenic at least in part may be used as the oxide film 6.
In that case, the shallow diffusion layer 13.13' is formed simultaneously with the formation of the drain diffusion layer 7.8.

In addition, in the above explanation, source and drain diffusion layers 7.8
is made of phosphorus, and the shallow diffusion layer 13 is made of an impurity with a diffusion coefficient smaller than that of phosphorus, such as arsenic or antimony. In this case, both diffusion layers may be formed with the same impurity (for example, shallow diffusion layer 1
The impurity concentration of the source/drain diffusion layer 7.8 was controlled to be lOL@~10"cm-", while the impurity concentration of the source/drain diffusion layer 7.8 was 10
For example, when using phosphorus, changing the concentration in this way can change the diffusion coefficient by a factor of 4 to 6. Therefore, it is possible to change the junction depth by more than 2 times. FIG. 3 shows an example of manufacturing a MOS transistor of the present invention using the above method.

(A) A first insulating film 14 such as an oxide film is further deposited on top of the polycrystalline silicon 4 deposited as shown in FIG. Using this as a mask, the first insulating film is etched, and then the cyst pattern 5 is removed, and then the polycrystalline silicon 4 is etched to form a first insulating film 14 covering the gate 4° and its upper surface. . At this time, the gate oxide film 3 is also etched to expose the surface of the substrate 1 (C). Similar to step E in the first drawing: , :, Although the second insulating film 6 is formed to cover the side surface of the gate 4, it is not necessary that all of the second insulating film 6 is doped with impurities. A close-up image of the surface of the substrate 1, that is, the first layer of film deposition For example, it may be sufficient if it is added to the first 0.1 μb (D) Next, the source/drain diffusion layer 7 has a high concentration necessary for contact formation. However, due to the heat treatment at this time, the impurities in the film are diffused into the region below the second insulating film 6', forming a shallow diffusion layer 13.13''. 7,8 depth gate 4
'The width W of the second insulating film 6' is set so that it does not reach the area directly below.
Please make it slightly smaller (.

By doing so, a structure similar to that shown in FIG. 2B can be obtained, but (E) the contact opening to the gate 4° is formed in a region slightly distant from the source/drain diffusion layer 7.8. In Figure 3, only the source and drain electrodes 10 and 11 are shown.The gate 4' is completely covered with the insulation WA14 and 6' on the top and side surfaces.As shown in this figure, the source and drain electrodes 10 .11 extends above the gate 4', there will be no short circuit between the gate and the source or drain. Therefore, it is not necessary to take into account the mask alignment error when forming the contact openings 20 and 21 by photolithography as shown in FIG. Even if it is shortened, the contact formation to the gate 4' is the same, so the substrate 1 necessary for element formation is
Therefore, this embodiment is particularly effective for increasing the density of semiconductor devices.However, as the insulating film 6 on the gate side surface, not only an oxide film but also a nitride film or other insulating film can be used as appropriate. be. Now, as described above, the source and drain diffusion layers 7 and 8 have a high concentration of force t in order to form good contact with the electrode wiring.
Since the present invention has a structure in which an insulating film mask is formed on the side surface of the gate pattern, the gate insulating film directly under the gate is directly exposed to the high concentration impurities.1 Therefore, the withstand voltage of the gate insulating film is The film is maintained at its original value. Since breakdown voltage defects in the gate insulating film account for a large proportion of failures in MOS type semiconductor devices,
The present invention contributes to improving the quality and reliability of MOS type semiconductor devices.
By forming the junction depth XJ of the source/drain diffusion layer as deep as desired for forming contact with the electrode wiring, the lateral expansion directly under the gate can be made sufficiently small. Since the structure depends almost only on the gate length L0, by forming the gate pattern with high precision, the desired effective channel length can be obtained with high precision.4 The characteristics of a MOS semiconductor device depend on the effective channel length. Therefore, it becomes easy to match the characteristics between the elements, and it becomes easier to obtain the characteristics according to the designed values, which improves the yield rate in the manufacturing process. This effect (
Tomo: This is especially important when the gate length is shortened due to miniaturization to achieve higher density.

Furthermore, by forming a shallow diffusion layer in the vicinity of the insulating film pattern on the side surface of the gate, the spread of the diffusion layer directly under the gate can be controlled more precisely, and the effective channel length can be formed with even higher precision. The formation of the fine pattern of the insulating film that covers only the gate side and its vicinity, which brought about these effects, is self-aligned and can be done without the addition of a special mask. - It is an extremely simple and controllable method that only requires dry etching with an etching gas incident perpendicularly to the substrate surface.

Since the width W of the insulating film pattern on the side surface of the gate is formed to be approximately equal to the thickness of the insulating film, the width can be obtained with high precision by controlling the film thickness. As in the method shown in Figure 1, there are cases where it is better to make the lateral spread IJ of the source/drain diffusion layer as close to W as possible.In such cases, since the pattern width W is formed with high precision, There is no need to allow extra margin, and (IJ-W) can be minimized.Furthermore, the present invention forms an insulating film pattern on the side of the gate with high precision and utilizes this to form a source/drain pattern. Since electrode contacts to the diffusion layer can be formed in a self-aligned manner, it is possible to achieve high density of MQ, ., S transistor elements with high precision. The structure of the present invention eliminates the need for extensive thermal oxidation of polycrystalline silicon.
Conventional drawbacks such as distortion caused by expansion of the thermal oxide film and reduction in gate breakdown voltage are present.
In the present invention, not only an oxide film but also a nitride film can be used as the insulating film covering the side surface of the gate, which is effective in preventing alkali, ion, and other external contaminants from entering the gate insulating film and stabilizing the characteristics. In the present invention (Table 1), the diffusion layer formed near the insulating film pattern on the side surface of the gate is made to have a lower concentration than the source/drain, so that the slope of the impurity distribution from the source/drain toward the region directly below the gate is made gentler, and the electric field near the drain is Reducing the strength has the effect of preventing a drop in drain breakdown voltage, which is a particular problem in short channels. It's something of high value.

[Brief explanation of the drawing]

Figures 1A-F show the manufacturing process of an example of a MOS transistor used in the present invention. Figures 2A and B show the main steps of another MO5h transistor with a shallow diffusion layer added. Figures 3A-E show the manufacturing process of an example of a MOS transistor used in the present invention. It is also a cross-sectional view of the manufacturing process of a MOS transistor according to an embodiment of the present invention covered with an insulating film.

Claims (2)

[Claims] (1) After a gate is provided in the MOS transistor forming area of a semiconductor substrate via a gate insulating film, the film thickness in the vertical direction of the substrate in the part covering the side surface of the gate is thicker than the same film thickness in other parts. An insulating film is deposited on the entire surface of the MOS transistor forming area, and an etching material is applied almost perpendicularly to the substrate to dry-etch the entire surface of the insulating film in the forming area by a predetermined amount in the vertical direction, thereby covering the side surface of the gate. A portion of the insulating film remains as an insulating film pattern, and impurities are introduced into the substrate surface using the gate and the insulating film pattern as a mask to form a source and a drain, and a source and a drain are formed on the source or drain adjacent to the insulating film pattern. A method for manufacturing a MOS type semiconductor device, which comprises forming a source or drain electrode. (2) The MO according to claim 1, characterized in that, before depositing the insulating film, impurities of the same conductivity type as the source and drain are introduced into the formation portion using the gate as a mask.
A method for manufacturing an S-type semiconductor device.