JPH03129740A - Manufacture of mos-type semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a drop in a breakdown strength of a gate insulating film by a method wherein an insulating film in a part with which a side face of a gate is covered is left as an insulating-film pattern, impurities are introduced into the surface of a substrate by making use of the gate and the insulating-film pattern as a mask and other parts for a source and a drain are formed. CONSTITUTION:Impurities such as As or Sb are introduced into a substrate 1 by making use of a gate 4' and a field oxide film 2 as a mask. Thereby, shallow impurity layers 7, 8 which are to be used as parts for a source and a drain are formed. A silicon oxide film 6 is deposited on them. Then, an etching gas is made incident nearly perpendicularly to the surface of the substrate 1; the oxide film 6 is removed selectively. After that, phosphorus is introduced by making use of the gate 4' and an insulating- film pattern 6' as a mask; impurity layers 17 and 18 which are to be used as other parts for the source and the drain are formed. An oxide film 9 is deposited; contact opening parts 20, 21 are formed in desired positions; a source electrode, a drain electrode and a gate electrode 10, 11, 12 are formed to complete this device. When a spread of a source layer and a drain layer into a part directly under the gate is controlled accurately, an effective channel length of high accuracy can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing MOS type semiconductor devices, and provides an improved method for self-alignment processes such as silicon gates. A gate pattern of, for example, polycrystalline silicon is formed on top of the gate insulating film via a gate insulating film, and impurities are introduced using the gate pattern itself as a diffusion mask to form source/drain diffusion layers.As a result, the upper surface of the gate insulating film is polycrystalline. Although it is covered with silicon, its sides are exposed to high concentrations of impurities. It is known that this causes a reduction in the withstand voltage of the gate insulating film. To avoid this, it is possible to lower the concentration of the diffusion layer.8 Doing so may lead to other problems such as an increase in resistance. If the spread is IJ, the effective channel length between the source and drain, tf, is expressed by the following equation.

L-tt=Lc-2・IJ
(1) It goes without saying that the characteristics of a MOS field effect transistor are determined by the effective channel length L*tt, and in order to make the characteristics uniform, it is necessary to form the effective channel length with high precision. It is preferable to use a structure and manufacturing method that allows the effective channel length to be determined by as few factors as possible.1 In formula (1) I, L-++ is two factors LC,
Force <, which means that it depends on IJ, By reducing IJ, its contribution is reduced and almost L
It is better to use a single factor type that depends only on c (1) However, if the source/drain diffusion layer is made shallow, the electrode wiring will pass through, causing a short circuit between the diffusion layer and the substrate. Although a method has been adopted in which the source/drain diffusion layer is shallow and deep in the contact formation region with the electrode wiring, an extra photomask (glass dry plate) is required for this purpose, and the deep diffusion layer and gate Since the relative position with respect to the mask is determined by mask alignment, a margin must be made in the mask design, making it unsuitable for high-density. A thermal oxide film is grown on the entire surface of the plate with the gate pattern formed. JP-A-52-22481 discloses a method that takes advantage of the fact that the oxide film grows thicker on polycrystalline silicon than on a single crystal substrate. Although this method is shown in Figure 3, by etching the oxide film on the substrate with a hydrogen fluoride solution and stopping the etching after removing it, it is possible to leave only the oxide film on the polycrystalline silicon gate. Covering the sides of the gate with an oxide film can protect the gate insulating film directly under the gate from being directly exposed to high-concentration impurities. Although it is difficult to form precisely because it is determined by two factors: etching conditions, the oxide film expands during thermal oxidation of polycrystalline silicon, so if the oxide film on the sides of the gate is too thick, the gate On the other hand, if the gate is made thinner, the withstand voltage between the gate and the source/drain is too low to be of practical use. It is an object of the present invention to provide a method by which a desired effective channel length can be obtained with high precision, and a structure suitable for alleviating the electric field strength near the drain can be easily manufactured.

Method for manufacturing a MOS type semiconductor device of the present invention to achieve these objects (above) After providing a gate in the M○S transistor formation area on a semiconductor substrate via a gate insulating film, the formation area is formed using the gate as a mask. impurities are introduced into the substrate to form part of the source and drain, and an insulating film is deposited over the entire surface of the forming area, the thickness of which is thicker in the vertical direction of the substrate in the part that covers the side surface of the gate than the same film thickness in other parts. By injecting an etching agent almost perpendicularly into the substrate and dry-etching the entire surface of the insulating film in the forming area by a predetermined amount in the vertical direction, the insulating film covering the side surface of the gate remains as an insulating film pattern. In this method, other parts of the source and drain are formed by introducing impurities into the surface of the substrate using the gate and the insulating film pattern as a mask.

This will be explained in detail below using examples. FIG. 1 shows the manufacturing process of a MOS field effect transistor according to an embodiment of the present invention in the order of steps. A field oxide film 2 for isolation between elements is formed at the position by a well-known selective oxidation method.Then, the substrate 1 is oxidized again and a gate oxide film 3 with a thickness of about 1000 nm is grown on the bottom of the MOS transistor shape. (B) Approximately 500 meters from the top
A polycrystalline silicon film 4 having a thickness of 0 Å is deposited by a well-known vapor phase epitaxy method.A photoresist pattern 5 for forming a gate pattern is formed by a photolithography method.

(C) The polycrystalline silicon film 4 is etched using the photoresist pattern 5 as a mask. At this time, either dry etching using a Freon gas or a nitric acid-hydrofluoric acid based chemical solution may be used. Etching the polycrystalline silicon film 4 Select conditions such that the angle between the plane and the surface of the substrate l is as close to 90" as possible. Its viscosity Polycrystalline silicon film 4
A gate 4' is formed from the side surface 4'b of the gate 4°.
is a steep surface that is almost perpendicular to the surface of the substrate 1. After this, before proceeding to the next step, the gate oxide film 3 may be selectively removed using the gate 4' as a mask.Here, it is left as is.

(D) In the state shown in FIG. 1C, an impurity with a diffusion coefficient as small as possible, such as arsenic A3 or antimony Sb, is introduced into the substrate 1 using the gate 4° and the field oxide film 2 as a mask. Either the toxide method or the ion implantation method may be used, but as is well known, when high precision is required, the ion implantation method is preferable. Keep the concentration slightly lower than that of the other parts of the drain layer.

In this way, a shallow impurity layer 7.8 that becomes part of the source/drain is formed. This state is shown in Figure 1. As shown in the figure, the film is deposited so that the film thickness in the vertical direction is thicker on the substrate in the part covering the side of the gate than in the same part. This free time Gate 4
It is better to choose a condition in which the film thickness on a horizontal plane such as the upper surface 4°a of the gate oxide film 3 and the film thickness on the gate side surface 4°b are as similar as possible. Although the low pressure vapor phase growth method performed at a gas pressure of about 1 Torr is more suitable than the high pressure vapor phase growth method, next, an etching gas 50 as an etching agent is made to be incident almost perpendicularly to the surface of the substrate 1. Oxide film 6 is selectively removed by dry etching.

Figure 2 shows an enlarged view of only the vicinity of gate 4.Dry etching includes methods such as ion beam etching and sputtering, which utilize the collision energy of inert gas such as argon ions, and methods mainly using freon etching. There are methods such as reactive sputtering and plasma etching that utilize chemical reactions of gases in the system.The former method has low etching selectivity and is limited in its application, and plasma etching has no directivity in the direction of gas movement. In contrast, reactive sputtering, in which the sample is placed between two parallel electrodes, allows etching gas to be incident almost perpendicularly to the surface of the substrate (under certain conditions, etching progresses in the same direction). Freon CF4 is convenient for the present invention because it has selectivity. Freon CF4 is used as the gas ~ ＼ 0.01 to 0.03 torr
When high-frequency power is 400 W with Teflon placed on the electrode at a gas pressure of
00 people/minute.

Under such low gas pressure as in this condition, the etching gas is almost perpendicularly incident on the substrate surface.
Oxide film 6 on top surface 4°a and gate oxide film 3
The etching gas is perpendicularly incident on the surfaces 6a and 6C of the gate.
b is close to parallel to the direction of gas incidence, and the amount of gas incident per unit area (very small and the etching speed is 1.%)
Therefore, since the receding speed of the inclined surface 6b in the vertical direction is slow, it almost moves to the right in this figure.Surfaces 6a, 6
b, 6 While the initial shape of c is almost maintained, the etching moves downward in parallel, and as the etching time changes from t1 to t2, etching progresses as shown by the dotted line.At the upper surface 4'a of gate 4' If the time when the oxide film 6 is almost removed is ts, then when the oxide film 6 remains in the shape shown by 6', the time t
At a time of 3 or slightly exceeding the time, the dry etching is stopped to form a fine insulating film pattern 6' of an oxide film that covers only the side surface 4'b of the gate 4' and the gate insulating film 3 in the vicinity thereof. Pattern 6' formed by
The width W of the gate 4' is approximately equal to the thickness of the oxide film 6 on the gate side surface 4'b. After that, the gate 4' and the insulating film are processed by ion implantation or thermal diffusion using the turn 6 as a mask.
From this point, phosphorus is introduced to form impurity layers 17 and 18 which will become the other parts of the source and drain.
The junction depth is adjusted so that the lateral extent lJt of the layers 17 and 18 is smaller than the width W of the oxide film turn 6'.

(G) Depositing the oxide film 9 again by vapor phase growth,
Contact holes 20 are formed at desired positions by photolithography.
21 are provided, and source/drain and gate electrodes 10 and 11 are provided.
．． 12 is completed, the oxide film 6 is formed on the gate side surface 4'b (upper gate upper surface 41a). If it is constant, it is almost fixed, so by monitoring the film thickness on the horizontal plane, it is possible to finely control the width W of the turn 6゛ to a desired value. , when forming the source/drain diffusion layers 7 and 8, the gate 4
The gate oxide film 3 is directly exposed to high concentration impurities directly under the gate 4', which is covered by the oxide film pattern 6". The layer 7.8 can be formed shallowly, and the intrusion 1J! below the gate 4° can be made extremely small, and these can be controlled with high precision by selecting impurities. This is particularly important when the gate length is shortened to achieve higher density or higher speed. , Not only the drain-source breakdown voltage but also the threshold value Vr, which is an important characteristic of a MOS field effect transistor, also depends on the effective channel length L・41
This is because it is necessary to obtain L-IT with high precision because it depends on the phosphorus impurity.
At this time, layer 17.18 and shallow diffusion layer 7.8 formed earlier
are impurities of the same conductivity type, so they are electrically connected.

It is desirable to select the diffusion conditions so that the lateral inward expansion of the layers 17 and 18 is smaller than the width W of the fine pattern 6' of the oxide film1.Since the shallow layers 7 and 8 are also subjected to heat treatment in this step, the diffusion depth is Since the diffusion coefficient of the impurity is small, the IJ spreads below the gate 4'.
As shown in the bottom of Figure 1, I is extremely small (1 In this case, L
・r+ is expressed by the following formula: L・tt−Lc −21Jl
(3) Since IJI can be made extremely small here, L.
Most ITs have source and drain layers 1
The junction depth XJ of 7.18 can be made deep enough to prevent alloy reactions during electrode formation by making lJt as close to W as possible. In the above explanation
Other methods are also possible, but for example
As the oxide 11!6, a doped oxide containing arsenic at least in part may be used. In that case, the shallow layer 7
, 811 may be formed simultaneously when forming the source and drain layers 17 and 18. Also, in the above method, the source,
It is desirable to form the drain layers 17 and 18 with phosphorus, and to form the layers 7 and 8 with an impurity having a smaller diffusion coefficient than phosphorus, such as arsenic or antimony. Taking advantage of the fact that the diffusion coefficient becomes smaller as the number increases, both layers may be formed with the same impurity. In that case (for example, the impurity concentration of shallow layers 7 and 8 is set to 10")
For example, when using phosphorus, by changing the concentration in this way, The diffusion coefficient can be changed by 4 to 6 times.
Therefore, the joining depth can be changed by more than twice. FIG. 3 shows still another embodiment of the present invention.

(A) A first insulating film 14 such as an oxide film is not further deposited on top of the polycrystalline silicon 4 deposited in FIG. 1B.
After that, the photoresist pattern 5 is formed (B'), and the first insulating film is etched using the resist pattern 5 as a mask, and then the polycrystalline silicon 4 is etched either by continuing or after removing the cyst pattern 5. A first insulating film 14 is formed to cover the gate 4' and its upper surface. At this time, the gate oxide film 3 is also etched to expose the surface of the substrate 1 (C). In the same way as step E in the first drawing, a second insulating film 6° covering the 4° side surface of the gate is formed.
It is not necessary that impurities be added to all of the substrate 1 surface. In other words, the first surface of the film deposition. For example, the first 0.
Although it is sufficient to add only 1 μm (D), the source and drain layers 17 and 18 with a high concentration necessary for contact formation are formed. Even if the impurities in the film are diffused into the underlying region and a shallow source/drain layer 7.8 is formed, the depth of the source/drain layer 17.
It is made slightly smaller than the width W of the second insulating film 6' so that it does not reach the region directly below the gate 4°. By doing so, a structure similar to that shown in FIG.
In Figure 3, only the source and drain electrodes 10.11 are shown as being formed in a region slightly apart from the 7th layer 17.18. Even if the source and drain electrodes 10 and 11 extend over the gate 4' as shown in this figure, there will be no short circuit between the gate and the source or drain. (Air contact opening 20.
Even if one side of 21 is composed of an insulating film 6', there is no need to take into account mask alignment errors when forming contact openings 20 and 21 by photolithography as shown in FIG. Although it is shortened further in the source-drain direction, the contact formation to the gate 4° is the same, so the area of the substrate 1 required for device formation is reduced, and this embodiment is suitable for high-density semiconductor devices. However, as the insulating film 6 on the gate side surface, not only an oxide film but also a nitride film or other insulating film can be used as appropriate.As described above, some layers 17 and 18 of the source and drain are In the present invention, an insulating film mask is formed on the side surface of the gate pattern, so the gate insulating film directly under the gate has a high concentration. It is not directly exposed to impurities (therefore, the withstand pressure of the gate insulating film is maintained at its original value). Although the present invention contributes to improving the reliability of quality products of MOS type semiconductor devices, the present invention also improves the reliability of the insulating film pattern 6 on the side surface of the gate.
By forming the junction depth XJ of the source/drain impurity layer as deep as desired for forming contact with the electrode wiring, the lateral inward expansion of the source/drain layer can be made sufficiently small to form a shallow source/drain layer directly under the gate. too
As a result, the effective channel length Lu1l can be reliably made to almost exclusively depend on the gate length L6, so that by forming the gate pattern with high precision, a desired effective short channel length can be obtained with high precision. Since the characteristics of a MOS semiconductor device depend on the effective channel length, it is easier to match the characteristics between elements, making it easier to obtain characteristics as designed and improving the yield rate in the manufacturing process. (
Although this is particularly important when the gate length is shortened due to miniaturization in order to achieve high-density transistors, the present invention also provides a method for forming a shallow layer directly under the insulating film pattern on the side of the gate. By controlling the spread of the source/drain layer more precisely, it is possible to form an effective channel length with even higher precision. However, the formation of the fine pattern of the insulating film covering the vicinity of the gate side surface which brought about these effects is done in a self-aligned manner and without the addition of a special mask. This is an extremely simple and controllable method, as it only requires dry etching with an etching gas that is incident perpendicularly to the surface of the board after the insulating film is deposited on the entire surface of the MOS transistor forming area. Since the width W of the film pattern is formed to be approximately equal to the thickness of the insulating film, the width can be obtained with high precision by controlling the film thickness. In the configuration of the present invention, there is no need to thermally oxidize the polycrystalline silicon, so there are no conventional drawbacks such as distortion caused by expansion of the film due to growth of the thermal oxide film or reduction in gate breakdown voltage. Since not only an oxide film but also a nitride film can be used as the covering insulating film, it is possible to prevent alkali, ion, and other external contaminants from entering the gate insulating film, which is effective in stabilizing the characteristics. It is possible to easily and accurately obtain a structure in which the source/drain layer formed directly under the above-mentioned insulating film pattern on the side surface of the gate has a lower concentration than the other parts of the source/drain. By making the slope of the impurity distribution more gentle in the direction and relaxing the electric field strength near the drain, the present invention has the effect of preventing a drop in drain breakdown voltage, which is a problem especially in short channels. It solves various problems of type semiconductor devices and has extremely high industrial value for realizing high-density semiconductor integrated circuit devices with fine patterns.

[Brief explanation of the drawing]

Figures 1A-G are manufacturing steps of a MOS transistor according to an embodiment of the present invention; Figure 2 is an enlarged cross-section of the main steps in Figure 1; Figures 3A-E are the steps in which the gate is covered with an insulating film. Furthermore, process diagrams of other embodiments are also available.

Claims (5)

[Claims] (1) After providing a gate in a MOS transistor formation area on a semiconductor substrate via a gate insulating film, using the gate as a mask, impurities are introduced into the formation area to form part of the source and drain, and the gate is An insulating film is deposited on the entire surface of the forming part, the thickness of which is thicker in the vertical direction on the substrate in the part covering the side surface than the same film thickness in other parts, and an etching material is applied almost perpendicularly to the substrate to form the forming part. By dry etching the entire surface of the insulating film by a predetermined amount in the vertical direction, the part of the insulating film covering the side surface of the gate remains as an insulating film pattern, and impurities are added to the surface of the substrate using the gate and the insulating film pattern as a mask. A method for manufacturing a MOS type semiconductor device, characterized in that the other parts of the source and drain are formed by introducing the above-mentioned source and drain. (2) After providing a gate in the MOS transistor formation area on the semiconductor substrate via a gate insulating film, using the gate as a mask, arsenic or antimony is introduced as an impurity into the formation area by ion implantation to form the source and drain. An insulating film is deposited on the entire surface of the forming part, and the insulating film is thicker in the vertical direction of the substrate in the part covering the side surface of the gate than in the other parts, and is deposited almost perpendicularly to the substrate. By injecting an etching material and dry etching the entire surface of the insulating film in the formation area by a predetermined amount in the vertical direction, the insulating film covering the side surface of the gate remains as an insulating film pattern, and the gate and the insulating film pattern are Impurities are introduced into a portion of the substrate using the mask as a mask to form other portions of the source and drain that are more highly concentrated than the portions of the source and drain so as not to reach the ends directly below the gate of the portion of the substrate. A method for manufacturing a MOS type semiconductor device. (3) M according to claim 2, characterized in that the other portion is formed so as not to reach the area directly under the gate.
A method for manufacturing an OS type semiconductor device. (4) The method for manufacturing a MOS type semiconductor device according to claim 2, wherein the same impurity as the impurity for forming the part is used as the impurity for forming the other part. (5) The method for manufacturing a MOS type semiconductor device according to claim 1, characterized in that the other partial forming impurity uses an impurity having a larger diffusion coefficient than the partial forming impurity.