JPH03126112A - Constant voltage generating circuit - Google Patents

Constant voltage generating circuit

Info

Publication number
JPH03126112A
JPH03126112A JP1265537A JP26553789A JPH03126112A JP H03126112 A JPH03126112 A JP H03126112A JP 1265537 A JP1265537 A JP 1265537A JP 26553789 A JP26553789 A JP 26553789A JP H03126112 A JPH03126112 A JP H03126112A
Authority
JP
Japan
Prior art keywords
voltage
limiter
circuit
temperature
limit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1265537A
Other languages
Japanese (ja)
Inventor
Naotaka Sumihiro
住廣　直孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1265537A priority Critical patent/JPH03126112A/en
Publication of JPH03126112A publication Critical patent/JPH03126112A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Control Of Voltage And Current In General (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To obtain a stable constant voltage generating circuit whose output voltage is scarcely changed at the time of the temperature change by connecting a voltage clamping circuit, which consists of series connection of two limiters having opposite temperature dependences of limit voltages, to the output terminal of a boosting circuit. CONSTITUTION:The constant voltage generating circuit consists of a voltage clamping circuit 4, where a first limiter 2 and a second limiter 3 are connected in series at a second connection point 9, and a boosting circuit 1 to whose output terminal 10 the voltage clamping circuit 4 is connected to. In the voltage clamping circuit 4, the first limiter 2 whose limit voltage is reduced in accordance with the rise of temperature and the second limiter 6 whose limit voltage is raised in accordance with the rise of temperature are connected in series. Since temperature dependency of limit voltage is cancelled, the output voltage is scarcely changed at the time of the temperature change.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は定電圧発生回路に関し、特に高電圧発生回路に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a constant voltage generation circuit, and particularly to a high voltage generation circuit.

［従来の技術］ 従来、高電圧発生回路は、第４図（ａ）　、　（ｂ）に
示すように、電源電圧Ｖｃｃと、互いに逆相となるクロ
ックφ１．φ２とを人力とする昇圧回路１０１と、その
出力電圧を一定の設定電圧で飽和させるために昇圧回路
出力端１０５に接続されたリミッタ−１０２または１０
２Ａとからなっていた。リミッタ−１０２には同図（ａ
）に示すように、降伏電圧が所定の電圧に設定されたＰ
Ｎ接合からなるダイオード１０３を用いるか、あるいは
同図（ｂ）に示すリミッタ−１０２Ａのように、しきい
値電圧が所定の電圧に設定されたＭＯＳトランジスタ１
０６を用いる。[Prior Art] Conventionally, as shown in FIGS. 4(a) and 4(b), a high voltage generating circuit has been configured to generate a power supply voltage Vcc and clocks φ1. A booster circuit 101 powered by φ2 and a limiter 102 or 10 connected to the booster circuit output terminal 105 to saturate its output voltage at a constant set voltage.
It consisted of 2A. The limiter 102 is shown in the same figure (a).
), the breakdown voltage is set to a predetermined voltage.
Either a diode 103 consisting of an N junction is used, or a MOS transistor 1 whose threshold voltage is set to a predetermined voltage, as in the limiter 102A shown in FIG.
06 is used.

［発明が解決しようとする課題］ 上述した従来の高電圧発生回路には以下に説明するよう
に、動作時の温度により出力電圧が変動するという欠点
がある。リミッタ−１０２にダイオード１０３を用いる
と、その降伏電圧は温度の上昇とともに上昇するため、
高電圧発生回路の飽和電圧、すなわち出力電圧も上昇し
てしまう。また、リミッタ−１０２ＡにＭＯＳトランジ
スタ１０６を用いると、そのしきい値電圧は温度の上昇
とともに低下するため、高電圧発生回路の飽和電圧すな
わち出力電圧も低下してしまう。[Problems to be Solved by the Invention] The conventional high voltage generating circuit described above has a drawback in that the output voltage varies depending on the temperature during operation, as will be explained below. When the diode 103 is used as the limiter 102, its breakdown voltage increases as the temperature increases.
The saturation voltage of the high voltage generation circuit, that is, the output voltage also increases. Further, if the MOS transistor 106 is used as the limiter 102A, its threshold voltage decreases as the temperature rises, so the saturation voltage of the high voltage generation circuit, that is, the output voltage also decreases.

本発明の目的は、温度変化に対して出力電圧のほとんど
変化しない安定な定電圧発生回路を提供することである
。An object of the present invention is to provide a stable constant voltage generation circuit whose output voltage hardly changes with respect to temperature changes.

［課題を解決するための手段］ 本発明の定電圧発生回路は、リミット電圧が温度の上昇
にともない低Ｆする特性を有する第１のリミッタ−と、
リミット電圧が温度の上昇にともない上昇する特性を有
する第２のリミッタ−とが直列接続されて構成された電
圧クランプ回路と、出力端に前記電圧クランプ回路が接
続された昇圧回路とを存する。[Means for Solving the Problems] The constant voltage generation circuit of the present invention includes a first limiter having a characteristic that the limit voltage decreases in F as the temperature rises;
The voltage clamp circuit includes a voltage clamp circuit connected in series with a second limiter having a characteristic that the limit voltage increases as the temperature rises, and a booster circuit having the output terminal connected to the voltage clamp circuit.

［作　川］ リミット電圧の温度依存性が相殺されるため、温度変化
に対して出力電圧がほとんど変化しない。[Sakukawa] The temperature dependence of the limit voltage is canceled out, so the output voltage hardly changes with temperature changes.

［実施例］ 次に、本発明の実施例について図面を参照して説明する
。[Example] Next, an example of the present invention will be described with reference to the drawings.

第１図は本発明の第１の実施例の定電圧発生回路の回路
図、第２図はその出力の温度依存性を示す特性図である
。FIG. 1 is a circuit diagram of a constant voltage generating circuit according to a first embodiment of the present invention, and FIG. 2 is a characteristic diagram showing the temperature dependence of its output.

本実施例の定電圧発生回路は、第１のリミッタ−２と第
２のリミッタ−６が第２の接続点９で直列接続されて構
成された電圧クランプ回路４と、出力端１ｏに電圧クラ
ンプ回路４が接続された昇圧回路１とがらなっている。The constant voltage generation circuit of this embodiment includes a voltage clamp circuit 4 configured by connecting a first limiter 2 and a second limiter 6 in series at a second connection point 9, and a voltage clamp circuit 4 at an output terminal 1o. A booster circuit 1 is connected to a circuit 4.

第１のリミッタ−２は第１の接続点８で直列接続された
第１のＰチャンネルトランジスタ５と第２のＰチャンネ
ルトランジスタ６からなる。第１のＰチャネルトランジ
スタ５はＰ型半導体基板表面近傍に形成されたＮ型半導
体のウェル内に形成され、ウェルとソースは出方端１ｏ
に接続され、ゲート電極とドレインは第１の接続点８に
接続されている。第２のＰチャネルトランジスタ６はＰ
型半導体基板表面近傍に形成されたＮ型ウェル内に形成
され、ウェルとソースは第１の接続点８に接続され、ゲ
ート電極とドレインは第２の接続点９に接続されている
。第２のリミッタ−３はダイオード７からなる。ダイオ
ード７は不純物濃度約４　Ｘ　１０　”ｃｍ−３のＰ型
半導体基板と不純物濃度約Ｉ　Ｘ　１０　”ｃｍ−’の
Ｎ型ソースドレイン拡散層とからなるＰＮ接合で、室温
における降伏電圧は約１４Ｖである。降伏電圧の温度依
存性は、第２図に示すように、温度の上昇にともない降
伏電圧に上昇し、５０℃の変化に対し約０．４ｖ変化す
る。The first limiter 2 consists of a first P-channel transistor 5 and a second P-channel transistor 6 connected in series at a first connection point 8 . The first P-channel transistor 5 is formed in a well of an N-type semiconductor formed near the surface of a P-type semiconductor substrate, and the well and source are connected to the protruding end 1o.
The gate electrode and the drain are connected to the first connection point 8 . The second P channel transistor 6 is P
The well is formed in an N-type well formed near the surface of a type semiconductor substrate, and the well and source are connected to a first connection point 8, and the gate electrode and drain are connected to a second connection point 9. The second limiter 3 consists of a diode 7. The diode 7 is a PN junction consisting of a P-type semiconductor substrate with an impurity concentration of about 4 x 10"cm-3 and an N-type source-drain diffusion layer with an impurity concentration of about I x 10"cm-', and the breakdown voltage at room temperature is about 14V. It is. As shown in FIG. 2, the temperature dependence of the breakdown voltage is such that the breakdown voltage increases as the temperature rises, and changes by about 0.4V for a change of 50°C.

したがフて、第２のリミッタ−６のリミット電圧は温度
、上昇にともない上昇する。第１のＰチャネルトランジ
スタ５および第２のＰチャネルトランジスタ６は不純物
濃度約４　Ｘ　１０１６ｃｍ−”のＮ型ウェル内に形成
されたゲート酸化膜約３００人のＭＯＳトランジスタで
、室温におけるしきい値電圧は約−２，Ｏｖである。し
きい値電圧の温度依存性は、第２図に示すように、温度
の上昇にともないしきい値電圧の絶対値が低下し、５０
℃の変化に対し約０．２ｖ変化するつしたがって、第１
のリミッタ−２のリミット電圧は、第２図に示すように
、低下し、５０℃の変化に対し約０．４　Ｖ低下する。Therefore, the limit voltage of the second limiter 6 increases as the temperature increases. The first P-channel transistor 5 and the second P-channel transistor 6 are MOS transistors formed in an N-type well with an impurity concentration of about 4 x 1016 cm and a gate oxide film of about 300 cm, and have a threshold voltage at room temperature. is about -2, Ov.The temperature dependence of the threshold voltage is as shown in Figure 2, as the absolute value of the threshold voltage decreases as the temperature rises,
It changes by about 0.2v with respect to the change in
As shown in FIG. 2, the limit voltage of limiter 2 decreases by about 0.4 V for a change of 50°C.

電圧クランプ回路４のリミット電圧は直列接続された第
１のリミッタ−２と第２のリミッタ−３のそれぞれのリ
ミット電圧の和となるため温度依存性は相殺され、第２
図に示すように、温度による変動はほとんどなく常に約
１８Ｖを出力する。本実施例においてＰチャネルトラン
ジスタが２個直列接続されているのはしきい値電圧の温
度変化がダイオードの降伏電圧の温度変化より小さいた
め温度変化を相殺するためである。温度変化特性に応じ
電圧クランプ回路４のリミット電圧を一定とするよう適
性個数のＰチャネルトランジスタを接続することも本発
明に包含されることはいうまでもない。The limit voltage of the voltage clamp circuit 4 is the sum of the limit voltages of the first limiter 2 and the second limiter 3 connected in series, so the temperature dependence is canceled out, and the second limiter
As shown in the figure, there is almost no variation due to temperature and the output is always about 18V. The reason why two P-channel transistors are connected in series in this embodiment is to offset the temperature change since the temperature change in the threshold voltage is smaller than the temperature change in the breakdown voltage of the diode. It goes without saying that the present invention also includes connecting an appropriate number of P-channel transistors to keep the limit voltage of the voltage clamp circuit 4 constant in accordance with the temperature change characteristics.

第３図は本発明の第２実施例の定電圧発生回路の回路図
である。FIG. 3 is a circuit diagram of a constant voltage generating circuit according to a second embodiment of the present invention.

第１のリミッタ−２の第１のＰチャネルトランジスタ５
と第２のＰチャネルトランジスタ６とともに同一のＮウ
ェル内に形成され、Ｎウェルは第１のＰチャネルトラン
ジスタ５のソースとともに出力端１０に接続されている
。Ｎウェルの不純物濃度は約３　Ｘ　１０１６ａｍ−３
で、第１のＰチャネルトランジスタ５の室温におけるし
きい値電圧は約１．５　Ｖであり、第２のＰチャネルト
ランジスタ６の室温におけるしきい値電圧は約１．５　
Ｖのバックバイアスが印加されるため約２．５■である
。しきい値電圧の温度変化は第１のＰチャネルトランジ
スタ５と第２のＰチャネルトランジスタ６ともに５０℃
に対し約０．２ｖであるから定電圧回路の出力′賀正は
温度による変動はほとんどなく常に約１８Ｖである。本
実施例では第１のリミッタ−２の第１のＰチャネルトラ
ンジスタ５と第２のＰチャネルトランジスタ６が同一の
Ｎウェル内に形成されるため集積度が高いというメリッ
トがある。First P-channel transistor 5 of first limiter 2
and the second P-channel transistor 6 are formed in the same N-well, and the N-well is connected to the output terminal 10 together with the source of the first P-channel transistor 5 . The impurity concentration of the N-well is approximately 3 x 1016 am-3
The threshold voltage of the first P-channel transistor 5 at room temperature is about 1.5 V, and the threshold voltage of the second P-channel transistor 6 at room temperature is about 1.5 V.
Since a back bias of V is applied, the voltage is about 2.5 . The temperature change in threshold voltage is 50°C for both the first P-channel transistor 5 and the second P-channel transistor 6.
Since the output voltage of the constant voltage circuit is about 0.2V, the output voltage of the constant voltage circuit hardly changes due to temperature and is always about 18V. In this embodiment, since the first P-channel transistor 5 and the second P-channel transistor 6 of the first limiter 2 are formed in the same N well, there is an advantage that the degree of integration is high.

［発明の効果］ 以上説明したように本発明は、昇圧回路の出力端に、リ
ミット電圧の温度依存性が相反する２つのリミッタ−を
直列接続して構成される電圧クランプ回路を接続するこ
とにより、リミット電圧の温度依存性が相殺され、温度
変化、に対して出力電圧のほとんど変化しない安定な定
電圧発生回路を得ることができる。[Effects of the Invention] As explained above, the present invention provides a voltage clamp circuit configured by connecting in series two limiters whose limit voltages have opposite temperature dependencies to the output end of a booster circuit. , the temperature dependence of the limit voltage is canceled out, and a stable constant voltage generation circuit whose output voltage hardly changes with respect to temperature changes can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の第１の実施例の定電圧発生回路の回路
図、第２図はその出力電圧の温度依存性を示す特性図、
第３図は本発明の第２の実施例の定電圧発生回路の回路
図、第４図（ａ）　、　（ｂ）は従来の定電圧発生回路
の回路図である。 １．１０１・・・昇圧回路、 ２・・・第１のリミッタ− ３・・・第２のリミッタ− ４・・・電圧クランプ回路、 ５・・・第１のＰチャネルトランジスタ、６・・・第２
のＰチャネルトランジスタ、７．１０３・・・ダイオー
ド、８・・・第１の接続点、９・・・第２の接続点、１
０，１０４・・・出力端、１０２．１０２Ａ・・・リミ
ッタ− １０５・・・接続点、１０６・・・トランジスタ。FIG. 1 is a circuit diagram of a constant voltage generating circuit according to a first embodiment of the present invention, and FIG. 2 is a characteristic diagram showing the temperature dependence of its output voltage.
FIG. 3 is a circuit diagram of a constant voltage generating circuit according to a second embodiment of the present invention, and FIGS. 4(a) and 4(b) are circuit diagrams of a conventional constant voltage generating circuit. 1.101... Boost circuit, 2... First limiter, 3... Second limiter, 4... Voltage clamp circuit, 5... First P-channel transistor, 6... Second
P-channel transistor, 7.103...Diode, 8...First connection point, 9...Second connection point, 1
0,104...Output end, 102.102A...Limiter 105...Connection point, 106...Transistor.

Claims (1)

【特許請求の範囲】 １、リミット電圧が温度の上昇にともない低下する特性
を有する第１のリミッターと、リミット電圧が温度の上
昇にともない上昇する特性を有する第２のリミッターと
が直列接続されて構成された電圧クランプ回路と、 出力端に前記電圧クランプ回路が接続された昇圧回路と
を有する定電圧発生回路。[Claims] 1. A first limiter having a characteristic that the limit voltage decreases as the temperature rises and a second limiter having the characteristic that the limit voltage increases as the temperature rises are connected in series. 1. A constant voltage generation circuit comprising: a voltage clamp circuit configured as described above; and a booster circuit having an output terminal connected to the voltage clamp circuit.
JP1265537A 1989-10-11 1989-10-11 Constant voltage generating circuit Pending JPH03126112A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1265537A JPH03126112A (en) 1989-10-11 1989-10-11 Constant voltage generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1265537A JPH03126112A (en) 1989-10-11 1989-10-11 Constant voltage generating circuit

Publications (1)

Publication Number Publication Date
JPH03126112A true JPH03126112A (en) 1991-05-29

Family

ID=17418503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1265537A Pending JPH03126112A (en) 1989-10-11 1989-10-11 Constant voltage generating circuit

Country Status (1)

Country Link
JP (1) JPH03126112A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3477837A1 (en) * 2017-10-25 2019-05-01 ams AG Charge pump structure with regulated output voltage

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3477837A1 (en) * 2017-10-25 2019-05-01 ams AG Charge pump structure with regulated output voltage
WO2019081304A1 (en) * 2017-10-25 2019-05-02 Ams Ag Charge pump structure with regulated output voltage
CN111247732A (en) * 2017-10-25 2020-06-05 希奥检测有限公司 Charge pump architecture with regulated output voltage
US11398778B2 (en) 2017-10-25 2022-07-26 Sciosense B.V. Charge pump structure with regulated output voltage
CN111247732B (en) * 2017-10-25 2023-08-11 希奥检测有限公司 Charge pump structure with regulated output voltage

Similar Documents

Publication Publication Date Title
EP0116820B1 (en) Complementary mos circuit
JPH04312107A (en) Constant voltage circuit
US4066917A (en) Circuit combining bipolar transistor and JFET's to produce a constant voltage characteristic
JPH08335122A (en) Semiconductor device for reference voltage
US6441680B1 (en) CMOS voltage reference
JP2724872B2 (en) Input circuit for semiconductor integrated circuit
JP2674669B2 (en) Semiconductor integrated circuit
JPH04102107A (en) Semiconductor integrated circuit
JPH0740050B2 (en) Voltage detection circuit
JP3324562B2 (en) Semiconductor integrated circuit
JPH03126112A (en) Constant voltage generating circuit
US7279880B2 (en) Temperature independent low voltage reference circuit
JPH0581083B2 (en)
JPH064160A (en) Mosfet constant current source generation circuit
JPH0291975A (en) Semiconductor device
JPH0244151B2 (en)
EP0921619A3 (en) A power source circuit of a semiconductor integrated circuit
JPS63217970A (en) Semiconductor integrated circuit
JPS61133423A (en) Reference voltage source
JPH01282858A (en) Semiconductor device
JPH06105865B2 (en) Semiconductor integrated circuit
US20060267675A1 (en) PMOS current mirror with cascaded PMOS transistors and zero voltage gate threshold transistor
JPH01253267A (en) Input protective circuit for semiconductor device
JPH08139200A (en) Transistor gate driving voltage generator and manufacture of the transistor
JPH0218968A (en) Vertical mos field effect transistor