JPH06105865B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit, and more particularly to a depletion type
The present invention relates to a semiconductor integrated circuit having a MOS transistor as a resistance element.

[Conventional technology]

In a semiconductor integrated circuit, particularly an analog integrated circuit, a resistance element may be included in the circuit. This resistance element is realized in various forms according to the necessity of its absolute accuracy, relative accuracy, current consumption, occupied area and the like. Generally, in a resistance element that is not trimmed after manufacturing, high absolute accuracy,
When relative accuracy is required, current consumption tends to increase and the occupied area tends to increase, and it is difficult to achieve both low consumption current and small occupied area. This is because, for example, if the width of the diffusion layer or the gate width of the MOS transistor is reduced, the processing accuracy will deteriorate.

A depletion type MOS transistor is an example of a resistance element that matches well with the current manufacturing process of a semiconductor integrated circuit mainly composed of a MOS transistor.

FIG. 5 shows an example of a bias circuit in which a current flowing through a resistor is used as a reference current and a current of a predetermined multiple of the current value is taken out through a current mirror circuit. The p-channel enhancement type MOS transistors 53, 54 and 55 are current mirror circuits. It is the n-channel depletion type MOS transistor 52 that constitutes the circuit and determines the magnitude of the reference current. The depletion type MOS transistor 52 is used, for example, in the ROI of the ion implantation code mask method in a semiconductor integrated circuit.
When M is built in, it can be formed at the same time by the ion implantation step of making the memory transistor into a depletion type, and no additional step is particularly required, so that it is particularly convenient for a standard cell type LSI.

The gate electrode of the depletion type MOS transistor 52 is normally connected to the ground potential in order to reduce the fluctuation of the drain current with respect to the fluctuation of the power supply voltage.

FIG. 6 shows an example of a resistance division circuit for obtaining a second reference potential at the terminal 67 by dividing the potential from the first reference potential applied to the terminal 66. The depletion type MOS transistors 63, 62 are shown in FIG.
The first reference potential is divided according to the resistance ratio between the source and drain electrodes.

The depletion type MOS transistor described above has a relatively large inevitable characteristic variation due to its manufacturing process.
Circuit design with a margin is required, and at the same time strict current and
It is difficult to apply to circuits that require voltage.

FIG. 7 is a characteristic diagram showing an example of the back gate voltage dependence of the threshold voltage of the n-channel depletion type MOS transistor. The average value (◯ − ◯) and the maximum value (× ...) Of the threshold voltage.
×) and the minimum value (Δ ... Δ) are plotted. The variation of the threshold voltage is extremely large when the back gate voltage is small.

[Problems to be solved by the invention]

The conventional semiconductor integrated circuit described above is a depletion type MOS.
Since the transistor is used as a resistance element, the increase or decrease of the current value or the resistance value due to the variation caused by the manufacturing process is a direct circuit operation, that is, the increase or decrease of the consumption current of the semiconductor integrated circuit or the increase or decrease of the reference voltage. Since it appears, it has a drawback that it cannot be applied to products with a small design margin.

An object of the present invention is to provide, as a resistance element of a semiconductor integrated circuit, a composite resistance element capable of suppressing variations in characteristics due to such a manufacturing process.

[Means for solving problems]

A semiconductor integrated circuit according to the present invention includes a depletion type MOS transistor, a resistance element inserted between a source electrode of the depletion type MOS transistor and a substrate potential supply terminal of the depletion type MOS transistor, and the depletion type MOS transistor. It has a composite resistance element comprising means for connecting the gate electrode of a MOS transistor to one of its source electrode, drain electrode or fixed potential supply terminal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit of a first embodiment of the present invention.

In this embodiment, an n-channel depletion type MOS transistor 12 and an n-channel depletion type MOS transistor 12 are used.
Of the resistor element 11 and the gate electrode of the n-channel depletion type MOS transistor 12 inserted between the source electrode of the n-channel depletion type MOS transistor 12 and the substrate potential supply terminal (ground terminal) of the n-channel depletion type MOS transistor 12 are connected to the source electrode thereof. It has a composite resistance element consisting of means. Here, this composite resistance element is used as a high resistance element as a constant current source that determines the current on the primary side of the current mirror circuit.

More specifically, 13, 14, and 15 are p-channel enhancement type MOS transistors, whose gate electrodes are commonly connected to each other, and an n-channel depletion type MOS transistor 1 is provided.
A current mirror circuit is configured by being connected to the drain electrode of 2. p-channel enhancement type
The channel lengths of the MOS transistors 13, 14, 15 are generally the same, and the channel widths of 14, 15 are designed to be a predetermined multiple of the channel width of 13, and the drain current of a predetermined multiple of the drain current flowing in the , 15 respectively. The drain current flowing through the p-channel enhancement type MOS transistor 13 is determined by the n-channel depletion type MOS transistor 12 and the resistance element 11.

The drain electrode of the n-channel depletion type MOS transistor 12 is connected to the gate electrode and drain electrode of the p-channel enhancement type MOS transistor 13,
Further, its gate electrode is commonly connected to the source electrode and connected to one end of the resistance element 11. The other end of the resistance element 11 is connected to the ground terminal.

Therefore, the n-channel depletion type MOS transistor 12
The source electrode is applied with the potential drop generated in the resistance element 11 as the back gate bias voltage, and therefore the variation in the threshold voltage due to the manufacturing process in the depletion type MOS transistor can be reduced.

The resistance element 11 is formed so as to coincide with the manufacturing process of the MOS type semiconductor integrated circuit. However, the resistance element 11 is mainly formed at the same time as the diffusion layer resistance for forming the source and drain regions, or at the same time for forming the gate electrode. A crystalline silicon resistance, an ion implantation resistance by ion implantation, or the like can be used.

Although the gate electrode of the n-channel depletion type MOS transistor 12 is connected to its own source electrode in this embodiment, the gate electrode may be biased to another bias point, for example, the ground potential.

FIG. 2 is a circuit diagram of the second embodiment of the present invention.

In this embodiment, the resistance dividing circuit is calibrated by using a composite resistance element composed of n-channel depletion type MOS transistors 22 and 21. The n-channel depletion type MOS transistor 21 is used as a resistance element inserted between the source electrode of the n-channel depletion type MOS transistor 22 and the substrate potential supply terminal (here, the ground terminal).

That is, the circuit shown in FIG. 2 uses a resistance element composed of a composite resistance element including an n-channel depletion type MOS transistor 22 and a n-channel depletion type MOS transistor 23 from a power supply terminal 26 for giving a first reference potential. Is a resistance division circuit that obtains the second reference potential at the output terminal 27 by the potential division described above. The n-channel depletion type MOS transistor 21 is provided between the source electrode of the n-channel depletion type MOS transistor 22 and the ground terminal. N-channel depletion type MO with common gate and drain electrodes
It is inserted by connecting the source electrode of the S transistor 22 and the source electrode to the ground terminal, respectively. The n-channel depletion type MOS transistor 22 is back-gate biased according to the drain current flowing through the n-channel depletion type MOS transistor 21. Therefore, variations in the threshold voltage of the n-channel depletion type MOS transistor 22 can be reduced. Since the n-channel depletion type MOS transistor 23 is back-gate biased by the voltage of the output terminal 27, the variation of the threshold voltage is small without using the composite resistance element. The composite resistance element according to the present embodiment is characterized in that it can be constituted by only transistors.

In the second embodiment, the n-channel depletion type
It goes without saying that the gate electrodes of the MOS transistors 23, 22 may be connected to their own source electrodes, or they may be connected to other suitable bias points, for example their own drain electrodes.

FIG. 3 is a circuit diagram of the third embodiment of the present invention.

In this embodiment, a pn junction diode 31 is used as a resistance element. Others are the same as those in the first embodiment. In the first and second embodiments, the n-channel depletion type MOS transistor 12,
The n-channel depletion type MOS transistor 32 of the third embodiment has a characteristic that it is placed under a relatively constant back gate bias, while the 23 is back gate biased depending on the magnitude of the drain current flowing through itself. There is.

FIG. 4 is a sectional view of a semiconductor chip when the pn junction diode 31 in FIG. 3 is formed in the same manufacturing process as a CMOS semiconductor integrated circuit.

An n-type well region 102 is formed in a p-type semiconductor substrate 101 made of silicon, and the n-type well region 10 is formed together with the formation of source and drain regions of a p-channel MOS transistor.
2. A p diffusion layer 103 is formed in 2 and a p diffusion layer 104 is formed in the p-type semiconductor substrate 101. Further, an n diffusion layer 105 is formed in the n-type well region 102 together with the formation of the source and drain regions of the n-channel MOS transistor. That is, the pn junction diode 31 is formed between the p diffusion layer 103 and the n-type well region 102.

It should be noted that the first resistance element for applying the back gate bias voltage
11. The magnitude of the potential drop in the n-channel depletion type MOS transistor 21 depends on the threshold voltage value of the n-channel depletion type MOS transistor used. Can be reduced to less than half of that, which is practically effective for improving circuit characteristics.

〔The invention's effect〕

As described above, according to the present invention, a resistance element can be inserted between a source electrode of a depletion type MOS transistor and a substrate potential supply terminal and operated in a state in which a back gate bias voltage is applied. Since it has, the variation due to the manufacturing process originally possessed by the depletion type MOS transistor can be reduced,
This has the effect of expanding the applicability of resistance elements that use MOS transistors.

[Brief description of drawings]

1 to 3 are circuit diagrams of first to third embodiments of the present invention, respectively. FIG. 4 is a sectional view of a semiconductor chip showing the structure of a pn junction diode of FIG. 3, FIG. 5 and FIG. FIG. 6 is a circuit diagram of a conventional example, and FIG. 7 is a characteristic diagram showing the back gate voltage V _BG dependency of the threshold voltage V _T of the depletion type MOS transistor. 11 …… Resistance element, 12,22,32,52 …… n-channel depletion type MOS transistor, 13,33,53,14,34,54,15,35,55
... P-channel enhancement type MOS transistor, 1
6,26,36,56,66 …… Power supply terminal, 21,22,23 …… n-channel depletion type MOS transistor, 27,67 …… Output terminal,
31 …… pn junction diode, 32,53,62,63 …… n channel depletion type MOS transistor, 101 …… p type semiconductor substrate, 102 …… n type well region, 103,104 …… p diffusion layer, 10
5 ... n diffusion layer.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03F 3/343 A 8124-5J

Claims (3)

[Claims] 1. A first depletion type MOS transistor,
The resistor element inserted between the source electrode of the first depletion type MOS transistor and the substrate potential supply terminal of the first depletion type MOS transistor, and the first element.
7. A semiconductor integrated circuit having a composite resistance element comprising means for connecting the gate electrode of the depletion type MOS transistor to any one of its source electrode, drain electrode or first fixed potential supply terminal. 2. A resistance element uses a second depletion type MOS transistor and a gate electrode of the second depletion type MOS transistor as one of its source electrode, drain electrode or second fixed potential supply terminal. The semiconductor integrated circuit according to claim (1), which comprises connecting means. 3. The semiconductor integrated circuit according to claim 1, wherein the resistance element is a PN junction diode.