JPH03124229U - - Google Patents
Info
- Publication number
- JPH03124229U JPH03124229U JP3440190U JP3440190U JPH03124229U JP H03124229 U JPH03124229 U JP H03124229U JP 3440190 U JP3440190 U JP 3440190U JP 3440190 U JP3440190 U JP 3440190U JP H03124229 U JPH03124229 U JP H03124229U
- Authority
- JP
- Japan
- Prior art keywords
- reset
- microprocessor
- cpu
- signal
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002457 bidirectional effect Effects 0.000 claims 2
- 238000002955 isolation Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図は本考案の原理ブロツク図、第２図は本
考案の装置の一実施例を示す構成ブロツク図、第
３図は従来のマイクロプロセツサ装置の一例を示
す構成概念図である。
１……マイクロプロセツサ、２……メモリ回路
、３……リセツト制御回路、４……ＣＰＵリセツ
ト分離回路。
FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a structural block diagram showing an embodiment of the device of the present invention, and FIG. 3 is a conceptual diagram of the structure of an example of a conventional microprocessor device. 1...Microprocessor, 2...Memory circuit, 3...Reset control circuit, 4...CPU reset separation circuit.
Claims (1)
ロプロセツサ１と、 このマイクロプロセツサによつてアクセスされ
るメモリ回路２と、 外部からのリセツト信号およびマイクロプロセ
ツサからのＣＰＵリセツト信号に応じてバスの使
用権を獲得すると共に、制御信号を出力するリセ
ツト制御回路３と、 前記マイクロプロセツサから出力される双方向
ＣＰＵリセツト信号を前記リセツト制御回路から
の制御信号に応じて分離しリセツト制御回路に与
えるＣＰＵリセツト分離回路４と を備えたマイクロプロセツサ装置。[Claims for Utility Model Registration] A microprocessor 1 that outputs a bidirectional CPU reset signal, a memory circuit 2 that is accessed by this microprocessor, and a reset signal from the outside and a CPU from the microprocessor. A reset control circuit 3 that acquires the right to use the bus in response to a reset signal and outputs a control signal, and a bidirectional CPU reset signal output from the microprocessor in response to a control signal from the reset control circuit. A microprocessor device comprising a CPU reset isolation circuit 4 which separates and supplies a reset control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3440190U JPH03124229U (en) | 1990-03-30 | 1990-03-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3440190U JPH03124229U (en) | 1990-03-30 | 1990-03-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03124229U true JPH03124229U (en) | 1991-12-17 |
Family
ID=31538838
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3440190U Pending JPH03124229U (en) | 1990-03-30 | 1990-03-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03124229U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006099410A (en) * | 2004-09-29 | 2006-04-13 | Mitsubishi Electric Corp | Method for controlling i2c |
-
1990
- 1990-03-30 JP JP3440190U patent/JPH03124229U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006099410A (en) * | 2004-09-29 | 2006-04-13 | Mitsubishi Electric Corp | Method for controlling i2c |