JPH03120975A - Signal generator - Google Patents

Abstract

PURPOSE:To decrease an output signal level difference more by applying subtraction processing to an output of a prescribed voltage and a signal outputted from a signal generating means. CONSTITUTION:A holding means is provided, which holds tentatively a prescribed voltage applied to a signal generating means and a means applying subtraction processing to an output of a prescribed voltage of the holding means and a signal outputted from the signal generating means and outputting the result is provided, and a prescribed voltage is subtracted from a signal outputted from the signal generating means. Thus, dispersion or the like of the prescribed voltage is completely eliminated. Moreover, since the dispersion or the like of a signal caused when a circuit component is provided to a post stage of the signal generating means is added to both the output of a prescribed voltage of the holding means and a signal outputted from the signal generating means, the dispersion or the like of the signal is eliminated because of cancellation by the subtraction processing. Thus, a level difference from a signal outputted from each signal generating means is completely eliminated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a signal generating device, and particularly to a signal generating device to which a predetermined voltage is applied and which removes the predetermined voltage from a signal generating means that generates a signal containing the predetermined voltage. The present invention relates to a signal generating device that outputs a signal.

[Prior Art] In recent years, the number of pixels in solid-state imaging devices has increased, and the signal readout speed has also increased. As a signal processing method to deal with this problem, a multi-line division readout method is known in which a signal line is divided into a plurality of parts and read out. However, this multi-line split readout method has a problem in that level differences in output signals occur between signal lines due to differences in parasitic capacitance and resistance between signal lines, differences in clock waveforms for driving the readout system, and the like.

Therefore, as a method for solving such a signal level difference, there is a signal readout method as shown in FIG.

In FIG. 4, A to A4 are buffer amplifiers.

is an amplifier, and Q1 to Q2□ are MOS transistors (hereinafter referred to as
(called a transistor). Further, 01 to C1 are capacitors, and B is a constant voltage source.

Note that the transistor Q s + QllI Q+41
Q21 is a first reset means, transistor Q4. Q+
o+Q+t and Qao serve as second reset means, and capacitors C2 to C4 serve as capacitance means.

S1 to S4 are sensor signals from the sensors, and N and to N4 are sensor reset level signals (output signals of the sensor when the sensor is in the reset state), which are the sensor signal S1, the reset level signal N2, and the sensor signal S2. and reset level signal N2, sensor signal S3 and reset level signal N
3. The sensor S4 and the reset level signal N4 are manually inputted through the same signal line.

Next, specific circuit operation will be explained. FIG. 5 shows sensor signals S, -S, reset level signals N1 to N4, clocks input to each section, and output signals (2). , is a waveform diagram of .

First, clock φ1. When φ8 becomes high level, transistor Q2. Q4. Q is turned on and the reset level signal N1 is read out. At the same time, b of capacitor C1
The side is set to a predetermined voltage (■) by a constant voltage source B. Next, clock φ3 is inverted to low level while clock φ1 remains at high level, and when clock φ1 becomes high level, transistors Q,,Q, are turned on, and transistor Q
,,Q, is turned off. Note that the transistor Q.

remains on. In this case, the sensor signal S.

However, since the potential of the reset level signal N has been previously applied to the a side of the capacitor C10'), the buffer amplifier A on the b side of the capacitor C3.

A signal with a potential of (S, -N+) +V is read out to the input of. This signal is input to amplifier A via transistors Q, , Q, and is amplified by a predetermined value i&V. Output as ut.

Here, the sensor signal S1 and the reset level signal N1 are
Since they are input through the same signal line, the effects of the parasitic capacitance and resistance of the signal line, the clock waveform of the readout system drive, etc. are the same, so (S, -N,) It can be said that this is a signal in which the influence of the system drive clock waveform, etc. has been removed, that is, the level difference has been removed.

In the circuit of FIG. 4, after (sensor signal St, reset level signal Nl) is read out in this way, next (
Sensor signal S8. The signals are sequentially divided and read out for each signal line, such as reset level signal N,), (sensor signal S2. reset level signal N2), and (sensor signal S4. reset level signal N,). After these signals are amplified by amplifier A, they are serially output in the above order. In this case, (sensor signal S2. reset level signal N2) to (sensor signal S4. reset level signal N,) are also output as signals with level differences removed, in the same way as described above.

[Problem to be solved by the invention] However, in such a circuit, the capacitor C, -
When setting the potential of C to the predetermined voltage of constant voltage source B,
The predetermined voltage V varies from signal line to signal line, or the offset voltages of the buffer amplifiers A and A4 vary from signal line to signal line. Therefore, it is not possible to eliminate such variations, and there is a problem in that it is not possible to accurately eliminate the level difference between the output signals.

The present invention has been made in view of such problems, and an object of the present invention is to provide a signal generating device suitably used in an imaging device that can further eliminate level differences in output signals.

[Means for Solving the Problems] The signal generating device of the present invention comprises: a signal generating means to which a predetermined voltage is applied and generates a signal including the predetermined voltage; a holding means for temporarily holding the predetermined voltage; and a holding means for temporarily holding the predetermined voltage. It is characterized by comprising means for subtracting the output of the predetermined voltage outputted from the means and the signal outputted from the signal generation means.

[Operation] The present invention provides a holding means that temporarily holds a predetermined voltage applied to the signal generating means, and subtracts the output of the predetermined voltage of the holding means and the signal output from the signal generating means and outputs the result. Since the predetermined voltage is subtracted from the signal output from the signal generation means, it is possible to completely eliminate variations in the predetermined voltage, and furthermore, it is possible to completely remove circuit elements after the signal generation means. Signal variations (for example, variations in the offset voltage of a buffer amplifier) that occur when such signals are provided are also added to both the predetermined voltage output of the holding means and the signal output from the signal generating means. Therefore, the subtraction process cancels out the signal variations, etc. In this way, it is possible to completely eliminate the causes of variations in the output signal, and when a plurality of signal generating means are provided, it is possible to completely eliminate the level difference between the signals output from each signal generating means.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

Note that, although the signal generating device of the present invention is suitably used in a signal readout circuit of an imaging device described below, it is not limited to such use.

FIG. 1 is a circuit diagram showing an embodiment of a signal readout circuit of an imaging device using the present invention. Incidentally, FIG. 1 shows a circuit of a four-division readout system, and the same parts as in the conventional device are given the same reference numerals.

In FIG. 1, CA and CB are capacitors, which are holding means for temporarily holding a predetermined voltage. A1-A4
is a buffer amplifier, and here buffer amplifier A,
The offset voltage of Vofl + the offset voltage of buffer amplifier A2 is ■. , 2. The offset voltage of buffer amplifier A3 is ■. ts and the offset voltage of buffer amplifier A4 is V Of 4. Further, the predetermined voltages applied from the constant voltage source B to each of the capacitors 01 to C4 are as follows. That is, the predetermined voltage applied to the capacitor C1 to which the sensor signal Sl and the reset level signal are input is
1.Hereafter, sensor signal Sz, reset level signal N
The predetermined voltage to be applied to the capacitor C2 to which
The predetermined voltage to be applied to the capacitor C3 to which the 2% sensor signal St and the reset level signal N3 are inputted is (3) and the sensor signal S4. The predetermined voltage applied to the capacitor C4 to which the reset level signal N4 is input is assumed to be 4. Furthermore, Q
1 to Q 2g are transistors, and clocks φ1 to φ
4 and clock φ1. The operation is controlled by φ6.

The sensor signal S1 is a signal from a sensor for image detection, and the reset level signal Nl is a reset level signal of the sensor, and the sensor signal Sl and reset level signal N1 are input through the same signal line. Also, S2, N2
, Ss, Ns, S4. N4 is also a sensor signal and a reset level signal, respectively, and each is input manually through the same signal line.

Figure 2 shows sensor signals S1 to s4 and reset level signal N.
1 to N4, the clock signals φ1 to φ4, φ, .

First, in period T1, the sensor signal Sl and the reset level signal N1 are input, the clock φ1 is at a high level, the clock φ2 is at a low level, and the clock φ,
is at low level, and clock φ8 is at high level. In this case, transistor Q 2+ Q< + Qe + Q
23 is on, transistor Q l+ Q 3. Q2
4. Q25 is off. In this state, the reset level signal N1 is a transistor. At the same time, a predetermined voltage v1 from constant voltage source B is applied to the other side of capacitor C1 via transistor Q4. Therefore, a predetermined voltage V1 is applied to the buffer amplifier A, and an offset voltage (2) between the predetermined voltage V1 and the buffer amplifier A. 1. The voltage of the sum of ■1+■. fl
is temporarily held in capacitor cA.

Next, in period T2, the clock φ is at a high level,
Since the clock φ8 is inverted to low level, the transistor Q + + Qz4+ QCs is turned on and the transistors Q21Q4+Q23 are turned off. As a result, the sensor signal S1 is input to the capacitor C1 via the transistor Q1, and the input voltage of the other side of the capacitor C1, that is, the buffer amplifier A1, is (Sl-Nl) + V
+. -This voltage is applied to the child terminal of differential amplifier A6 via buffer amplifier A0 and transistors Qs and Q24. However, the voltage given here is the offset voltage V of buffer amplifier 81. Since there is fl, (s
+ −Nl) +V + +V ot +. At the same time, the voltage V held in the capacitor CA
+ + V Ot+ is applied to one terminal of differential amplifier A via transistor Qt. Therefore, the output V of the differential amplifier A6. ut is (S, -N,), the predetermined voltage VI, and the offset voltage ■. 2. can be offset.

On the other hand, in period T2, the clock φ3 is inverted to a high level and the clock φ4 is inverted to a low level. In this case, clock ψ6 is at high level, clock φ8 is at low level, and transistors Q+s, Q17IQ
+8+ Q26 is on, transistor Q1□, QI
41 Q2? l Qis is off. Therefore, the reset level N3 is input to the capacitor C3 via the transistor Q'+3, and at the same time, the other side of the capacitor C3 is set to a predetermined voltage 3 by the constant voltage source B via the transistor Q+7. This predetermined voltage v3 and the offset voltage ■ of the buffer amplifier A3. , the sum of 3 Va +V.

, 3 are temporarily held in the capacitor C3 in the same way as in the operation described above.

Next, in period T3, the clock φ. is low level, clock φB is inverted to high level, and transistor Q +3
The sensor signal S3 is input to the capacitor C3 via the capacitor C3. Therefore, the + side terminal voltage of buffer amplifier A is
Similar to the operation described above, it becomes (S3'-NS) + V 3, and by adding an offset voltage to it (Ss-Na)
+V S +V 6t3 (7) The voltage is input to the child terminal of differential amplifier A6. At the same time, the voltage V s +V ot3 held in the capacitor CB is applied to one terminal of the differential amplifier A6. Therefore, differential amplifier A6
■ Output of. , becomes (S, -N,), and the predetermined voltage ■2
, offset voltage■. , 3 can be canceled out.

During this period T3, at the same time, an operation of holding a predetermined voltage applied to the capacitor C2 is performed, and the predetermined voltage v2 is applied to the capacitor CA and the offset voltage V of the buffer amplifier A2. +2
The sum of V2 +V. t2 is temporarily held in capacitor CA. Then, in the next period T, the lever holding voltage Vz
+V. +2 and (S2-N2) +V z + Vo
t2 is input to the differential amplifier A8, and similarly the output ■ of the differential amplifier A6. , becomes (S2-N2), the predetermined voltage V2, and the offset voltage ■. , can be offset.

Further, during the period T4, the predetermined voltage applied to the capacitor C4 and the offset voltage are held in the capacitor C3.

That is, the predetermined voltage v4 of the constant voltage source B and the offset voltage ■ of the buffer amplifier A4 are applied to the capacitor Cll. t4 sum voltage V, +V. +4 is retained. Then, in period T6, this holding voltage and (S4-N4) + V 4 + V.

, 4 are input to the differential amplifier Al+, and similarly, the output V a ut of the differential amplifier A6 becomes (S, -N4), and it is possible to cancel the predetermined voltage ■4, offset voltage v, f4. can. On the other hand, in this period T, a process is performed again in which a voltage equal to the sum of the predetermined voltage applied to the capacitor CI and the offset voltage is held in the capacitor CA. In this way, the signals inputted to each signal line are processed, and the output signals are serially outputted to each signal line.

In this embodiment, a predetermined voltage and an offset voltage are temporarily held in a capacitor for each signal line, and each input terminal of the differential amplifier is connected to a voltage that is the sum of this holding voltage, the manually input signal, the predetermined voltage, and the offset voltage. Enter. Therefore, a signal from which the clamp voltage and offset voltage have been removed is obtained from the output of the differential amplifier, and level differences can be completely removed. Further, in this embodiment, the circuit not only functions to remove level differences but also effectively functions as a sample-and-hold circuit for output signals.

FIG. 3 is a circuit diagram showing another embodiment of the signal readout path of the imaging device using the present invention. In the embodiment shown in FIG. 1, buffer amplifiers A1 to A4 were provided corresponding to each signal line, but in this embodiment, buffer amplifiers A, , A are replaced by one buffer amplifier A7, and buffer amplifiers A, , A, This is an improved version in which one buffer amplifier As is used for the same purpose. Therefore, the circuit configuration is simpler because there are no two buffer amplifiers.

In the circuit operation, as in the previous embodiment, first, a predetermined voltage (1) of the constant voltage source B and an offset voltage (2) of the buffer amplifier A7 are applied to the capacitor CA. 2. The sum of the voltages is 10. f7 is temporarily held. Next, this holding voltage is input to one terminal of the differential amplifier 80, and the child terminals (Sl-Nl) +V, +
V. 1. voltage is input. Therefore, differential amplifier A6
A predetermined voltage and offset voltage were removed from the output of (sl
-Nl> is obtained. Hereinafter, (S3-N3), (s
Output signals are serially output from the differential amplifier A6 for each signal line, such as z-N2) and (S4-N4).

In this embodiment as well, the level difference can be completely removed as in the previous embodiment, and it can also be used as a sample-and-hold circuit.

FIG. 6 is a schematic configuration diagram of an imaging device to which the present invention is applied.

In the figure, an image sensor 201 in which optical sensors are arranged in an area is subjected to television scanning by a vertical scanning section 202 and a horizontal scanning section 203.

The signal output from the horizontal scanning section 203 is sent to the processing circuit 20.
4 and output as a standard television signal.

Drive pulse φ for vertical and horizontal scanning units 202 and 203
HIII φOld mushroom φH2tsu φV3+ φVl, φV
The second class is supplied by driver 205. The driver 205 is also limited by the controller 206.

[Effects of the Invention] As explained above, according to the present invention, variations in the predetermined voltage applied to the signal generation means, variations in the signal that occur when a circuit element is provided after the signal generation means (for example,
It is possible to completely eliminate the causes of variations in the output signal due to variations in the offset voltage of the buffer amplifier, etc., and when multiple signal generation means are provided, it completely eliminates the level difference between the signals output from each signal generation means. be able to.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a signal readout circuit of an imaging device using the present invention, and FIG. 2 is a time chart showing the timing of each input signal, clock pulse, and output signal of the circuit of the embodiment. FIG. 3 is a circuit diagram showing another embodiment, FIG. 4 is a circuit diagram showing a signal readout circuit of a conventional image pickup device,
FIG. 5 is a time chart showing the timing of each input signal, clock pulse, and output signal of the circuit of FIG. 4, and FIG. 6 is a schematic configuration diagram of an imaging apparatus to which the present invention is applied. A6... Differential amplifier B... Constant voltage source

Claims (1)

[Claims] (1) Signal generating means to which a predetermined voltage is applied and generates a signal including the predetermined voltage, holding means for temporarily holding the predetermined voltage, and the predetermined voltage output from the holding means. and means for subtracting the output of the signal from the signal output from the signal generating means. (2) The signal generating device according to claim 1, wherein the signals output from the plurality of signal generating means are sequentially subtracted by one subtracting processing means and output as a serial signal. (3) The signal generating means includes a capacitor means into which a first signal output from a first signal source and a second signal output from a second signal source are sequentially input, and an input side of the capacitor means. and a second reset means connected to the output side of the capacitive means and applying the predetermined potential, the first signal output and the second signal output Claim 1 is a subtraction processing signal generating means for outputting a subtraction processing signal of
The signal generator described. (4) The first signal output from the first signal source is a sensor signal from a photoelectric conversion sensor, and the second signal output from the second signal source is a reset level signal from the photoelectric conversion sensor. The signal generating device according to claim 3.