JP2999237B2 - Multi-chip type photoelectric conversion device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip photoelectric conversion device, and more particularly to a multi-chip photoelectric conversion device in which a level difference between chips is reduced and an S / N ratio is improved. Related to the device.

[Prior Art] Hereinafter, a conventional multi-chip type photoelectric conversion device and a configuration of a chip used in the device will be described with reference to FIGS. 5 and 4. FIG.

FIG. 4 is a circuit configuration diagram of a photoelectric conversion element and a signal readout circuit provided in one chip.

FIG. 5 is a schematic configuration diagram for explaining a configuration of a multi-chip photoelectric conversion device.

As shown in FIG. 4, a pixel 10 serving as a photoelectric conversion element, a storage capacitor 20 for temporarily storing a photoelectric conversion signal read from the pixel 10, and a signal from the storage capacitor 20 to an output signal line are provided in the chip. A scanning circuit 30 for outputting, a reset transistor 40 for resetting an output signal line to a reference potential,
Amplifier 50 that amplifies the signal of the output signal line, transistor 60 for an output switch that controls the external output of amplifier 50, pixel
A transistor 21 for resetting the emitter and horizontal output line of the transistor 10, a transfer transistor 22 for transferring a signal read from the pixel 10 to a storage capacitor 20, a transistor 23 for resetting the storage capacitor 20, and a signal stored in the storage capacitor 20 To the output signal line. Further, a logic circuit 70 for driving each pixel and circuit is also incorporated.

In this configuration example, the pixel 10 has a configuration equivalent to a bipolar transistor, accumulates carriers generated by light irradiation on a base, and outputs a signal corresponding to the carriers from an emitter. And a transistor M for resetting the base.

φ _HS , φ _H1 , φ _H2 are pulses for controlling the scanning circuit 30,
φ _VC , φ _RF , φ _T , φ _CR , φ _HC , φ _OUT are pulses for controlling the transistors 21, M, 22, 23, 40, 60, respectively.

A plurality of chips each having the photoelectric conversion element and the signal readout circuit shown in FIG. 4 are connected to form a multi-chip photoelectric conversion device as shown in FIG.

The multi-chip type photoelectric conversion device of the present example is configured by three chips. A pulse φclock is input to each chip, and output terminals are commonly connected.

The operation of the multichip photoelectric conversion device is started by a pulse φstart. After the photocarriers are accumulated in the bipolar sensor T of the pixel 10 and the accumulation operation is completed,
Pixel signals from each chip are collectively read out to the storage capacitor 20, and signals (Vout in the figure) are sequentially output from the chip 1. When all the signals of the chip 1 are output, a pulse φ _O is sent from the chip 1 to the chip 2 (as shown in the figure, a pulse φ _O is sent from the output terminal Po to the output terminal Pin),
As a result, a signal is subsequently output from the chip 2.
Similarly, when all the signals of the chip 2 are output, a pulse φ _O is sent from the chip 2 to the chip 3, and the signal is output from the chip 3.

[Problems to be Solved by the Invention] However, in the above-described conventional multi-chip type photoelectric conversion device, a level difference occurs in an output signal from each chip due to an offset variation of the amplifier 50 between the chips. Hereinafter, this offset variation will be described with reference to FIG.

FIG. 6 is a schematic diagram of an output signal of the multi-chip type photoelectric conversion device shown in FIG. 5 in a dark state.

As shown in the drawing, a level difference is generated in the output signals from the chip 1, the chip 2, and the chip 3 due to the offset variation (Δv1, Δv2, Δv3) of the amplifier 50 between the chips. This level difference is several mv to several tens mv with respect to the signal 1v, and finally, the image is printed or displayed like a vertical stripe, and the image is significantly deteriorated.

Conventionally, chip sorting has been performed to reduce this level difference, but this has resulted in a significant reduction in chip yield and an increase in cost.

[Means for Solving the Problems] A multi-chip photoelectric conversion device according to the present invention includes a plurality of clamp units that clamp a photoelectric conversion signal from a photoelectric conversion element and a reference signal generation unit that is configured to be equivalent to the clamp unit. And a subtraction processing means for subtracting the output signal of the clamp means and the output signal of the reference signal generation means, wherein the output side of the clamp means and the output side of the reference signal generation means of each chip are common. Connected to the subtraction processing means.

[Operation] According to the present invention, the offset variation of the amplifier between the chips is removed by the clamp operation by the clamp means, and the offset of the clamp means is different from the offset of the dummy clamp circuit (reference voltage generation means) provided in the same chip. From the subtraction process. As a result, it is possible to eliminate a level difference between chips.

Examples Hereinafter, examples of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of an output unit provided in one chip of a multi-chip photoelectric conversion device of the present invention.

The configuration of the photoelectric exchange element and the signal readout circuit is as follows:
Except for the configuration of the output unit described below, it is the same as that shown in FIG.

As shown in the figure, the output unit includes a clamp circuit 100 for clamping a signal from the amplifier 50, and a dermy clamp circuit 200 configured similarly to the clamp circuit 100. The clamp circuit 100 includes a coupling capacitor 101, a switch transistor 102, and a buffer amplifier 103, and the dermy clamp circuit 200 includes a switch transistor 102 and a buffer amplifier 103. The signal input to the clamp circuit 100 is a pulse φcla input to the switch transistor 102.
clamped by mp.

Since the clamp circuit 100 and the dermy clamp circuit 200 are provided adjacent to each other in the same chip, they have substantially the same offset voltage, and the output signal (V
s out) and loaders Me output signal of the clamp circuit 200 (V _B ou
By performing the subtraction process with t), the offset voltage component of the output signal of the clamp circuit 100 can be removed.

Next, the operation of the output unit described with reference to FIG. 1 will be described with reference to the timing chart shown in FIG.

First, in the chip 1, T _C is the clamp period for clamping operation, a pulse phi _HC as a high level, the output signal line and the reset transistor 40 in the ON state is reset to the reference voltage V _O (GND). Amplifier 50 at this time
Is input to the clamp circuit 100, the switch transistor 102 is turned on by the pulse φclamp, and the output signal from the amplifier 50 is clamped. That is, the clamped signal is a portion where the output signal is reset to the reference potential (GND) by a pulse phi _HC.

Although the offset voltage of the amplifier 50 is superimposed on the clamped signal, this is removed by the clamp operation.
After the clamp operation, the photoelectric conversion signal is output from the pixel, and the potential of the electrode on the amplifier side of the coupling capacitor 101 is changed from the offset potential V _O to the photoelectric conversion signal + offset voltage (V _S + V _O ).
Since the potential of the electrode on the output side of the coupling capacitor 101 only becomes the clamp voltage + the photoelectric conversion signal voltage from the clamp potential, the offset voltage V _O of the amplifier 50 is not output from the clamp circuit 100.

The output signal from the clamp circuit 100 is a pulse φselect
The output to the outside is controlled by the output switch transistor 60 controlled by the switch.

This control is different between chip 1 and the other chips. The clamped signal is externally output by the chip 1,
There is no external output for other chips. This is because the clamped signal of the chip 1 is necessary as a reference signal for image processing, and other clamped signals are unnecessary.

Signals of each chip, it is necessary to continuously, in the present embodiment, as shown in FIG. 2, the signal output period of the chip 1 T _O
In addition, since the clamp operation of the chip 2 is performed and the clamped signals other than the chip 1 are not output as described above, the pulse φselect applied to each chip is sequentially set to the high level so that the continuous signal is output. Obtainable. This continuous signal is an output signal after the clamp operation, and is a signal from which the offset voltage of the amplifier 50 has been removed as described above.

FIG. 3 is a schematic explanatory view showing one embodiment of the multi-chip photoelectric conversion device.

Signal output terminal L _S of each chip are connected in common, and also the reference signal output terminal L _B are connected in common. Signal V _S out and signal V _B o
ut is the signal output Vou from which the subtraction process is performed by the differential amplifier 300 and the offset voltage of the clamp circuit 100 is removed.
t 'is output.

In the embodiments of the present invention, a bipolar type photoelectric conversion element has been described as an example, but the gist of the present invention is to obtain a continuous signal from which an offset voltage has been removed after clamping a signal to be clamped. Photoelectric conversion element (J-FET
Type, MOS type, CCD, etc.).

[Effects of the Invention] As described above, according to the present invention, after clamping the signal from the photoelectric conversion element, the output signals of a plurality of chips are selectively combined, so that the level difference between the chips can be removed. It becomes possible. Therefore, chip selection is not required, and a high-quality image can be obtained at low cost.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of an output section of a photoelectric conversion element provided in one chip of a multi-chip photoelectric conversion device of the present invention. FIG. 2 is a timing chart for explaining the operation of the output unit. FIG. 3 is a schematic explanatory view showing one embodiment of the multi-chip photoelectric conversion device. FIG. 4 is a circuit configuration diagram of a conventional photoelectric conversion element and a signal readout circuit provided in one chip. FIG. 5 is a schematic configuration diagram for explaining a configuration of a multi-chip photoelectric conversion device. FIG. 6 is a schematic diagram of an output signal of the multi-chip type photoelectric conversion device shown in FIG. 5 in a dark state. 10 ... pixel, 20 ... storage capacity, 30 ... scanning circuit, 50 ... amplifier, 100 ... clamp circuit, 200 ... dermy clamp circuit, 300 ... differential amplifier.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 1/40-1/409 H04N 1/028 H04N 5/335 H01L 27/14

Claims (1)

(57) [Claims] A clamp means for clamping a photoelectric conversion signal from a photoelectric conversion element, a plurality of chips having a reference signal generating means configured equivalently to the clamp means; an output signal of the clamp means and the reference signal generation; Subtraction means for subtracting the output signal of the chip from the multi-chip type photoelectric converter connected to the subtraction processing means by connecting the output side of the clamping means and the output side of the reference signal generation means of each chip in common. Conversion device.