JPH0678218A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To provide an XY address type solid-state image pickup device capable of canceling FPN of offset property in real time without using a frame memory and increasing a chip area. CONSTITUTION:CMD picture elements 1-11 to 1-44 are arranged in two-dimensional fashion, and the gate terminal of each row is arranged by connecting commonly to vertical selection lines 5-1 to 5-4, and the source terminal of each column is arranged by connecting two column lines 8-1a to 8-4b alternately. The two column lines are connected to two video lines 4-1, 4-2 via a pair of transistors 2-1a to 2-4b for column selection driven commonly, and the two video lines 4-1, 4-2 are connected to signal lines 11-1, 11-2 via change-over switch groups 9-1 to 9-4. The signal line 11-1 is inputted to a differential amplifier 14 via a current/voltage conversion amplifier 12-1 and a delay circuit 13, and the signal line 11-2 is inputted to the differential amplifier 14 via a current/ voltage conversion amplifier 12-2, then, a differential signal of them is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to an XY address type solid-state image pickup device using an amplification type image pickup device capable of removing fixed pattern noise (hereinafter abbreviated as FPN).

[0002]

2. Description of the Related Art Conventionally, solid-state image pickup devices such as CCD image sensors have been widely used as image input devices. In a CCD image sensor, a charge signal photoelectrically converted by a photodiode is sequentially transferred by a CCD shift register, and finally, one or a plurality of charge detection amplifiers provided on the chip allows a low impedance video signal. Is generally used. The charge transfer efficiency of CCD shift register is 99.9
In the current CCD image sensor with 9% or more, except for the aperture ratio variation and the dark current variation of the photodiode, there is no FPN of the video signal due to the patterning variation of the CCD part that occurs during the process, so the low F
An image of PN can be obtained.

However, in a normal CCD image sensor, the signal charge read by the charge detection amplifier is reset, so that the signal read once is destroyed. Therefore, it is not possible to confirm the storage state by monitoring the image while the optical information is being stored, or to read it out a plurality of times. Also CC
Due to the configuration of the D image sensor, it is difficult to add a special function such as random access to pixels or taking out only a part of image information. Further CC
The problem with D is that in the CCD image sensor, the transfer gates of all CCDs must be pulse-driven, so that when the number of pixels is increased or high-speed operation is attempted, the power consumed by the gate capacitance section becomes large. is there.

An XY address type amplification type image sensor has been proposed as an image sensor for solving these problems. This includes, for example, CMD (Charge Modul
ation Device, charge modulation device) image sensor and SI
T (Static Induction Transistor) image sensor, AMI (Amplified MosIma)
There is something called a ge sensor). Regarding the CMD element used in the CMD image sensor, for example, JP-A-60-206063 and IEDM (International Electron Device Meeting) held in 1986.
), Pp. 353-356, "A New MOS Image Sen"
sor Operating in a Non-destructive Readout Mode ”
Are described in detail in the papers entitled Each of these image sensors has a photoelectric conversion function and a signal amplification function for each pixel, and since the signal charges are stored unless reset, nondestructive readout of the signal charges is possible.

Next, XY using a conventional amplification type image pickup device
As an example of the address-type image sensor, a configuration of an image sensor using CMD as a pixel is shown in FIG.
Will be explained. CMD101-11, 10 that constitutes each pixel
1-12, ... 101-mn are arranged in a matrix, and a video voltage V _DD (> 0) is commonly applied to each drain thereof.
The gate terminals of the CMD groups in each row arranged in the X direction are connected to the vertical selection lines 102-1, 102-2, ... 102-m, respectively, and the sources of the CMD groups in each column arranged in the Y direction are connected. The terminals are connected to the column lines 103-1, 103-2, ... 103-n, respectively. The column lines 103-1, 103-2, ... 103-n are column selection transistors 104-1, 104-2 ,.
, And grounding transistors 105-1, 105-2, ... 105
-n is connected to the video signal line 106 and the line 107 grounded to the ground, respectively. Video signal line 106
Is a current-voltage conversion type preamplifier whose input is virtually grounded.
The video signal of negative polarity is connected to the output terminal 109 of the preamplifier 108 and is read out in time series.

Vertical selection lines 102-1, 102-2, ... 102-
m is connected to the vertical scanning circuit 110, and signals Φ _G1 , Φ _G2 , ... Φ _Gm are applied to them. The gate terminals of the column selection transistors 104-1, 104-2, ... 104-n and the grounding transistors 105-1, 105-2, ... 105-n are connected to the horizontal scanning circuit 111. Then, the signals Φ _S1 , Φ _S2 , ... Φ _Sn and their inverted signals are applied to each. Each CMD is formed on the same substrate, and the voltage V _SUB (<0) is applied to the substrate.

FIG. 6 is a signal waveform diagram for explaining the operation of the CMD solid-state image pickup device having the configuration shown in FIG. The signals Φ _G1 , Φ _G2 , ... Φ _Gm applied to the vertical selection lines 102-1, 102-2, ... 102-m are read gate voltage V _RD , reset voltage V _RS , overflow voltage V _OF , Storage voltage V
Consists _AC, during the horizontal blanking period t _BL in the non-selected row overflow voltage V _OF, horizontal video effective period t _H of the accumulated voltage V _AC, and the during the horizontal video effective period t _H is in the selected row readout gate The voltage V _RD and the reset voltage V _RS during the subsequent horizontal blanking period t _BL . Further, the signals Φ _S1 , Φ _S2 , ... Φ _Sn applied to the gate terminals of the column selection transistors 104-1, 104-2, ... 104-n are column lines.
103-1, 103-2, ... 103-n signal for selecting
The low level is the column selection transistors 104-1, 104-2.
, ... 104-n is turned off, grounding transistors 105-1, 105-2, ... 105-n are turned on, and high level turns on the column selection transistor and the grounding transistor off. The voltage value is set to

[0008]

The amplification type solid-state image pickup device having the above-mentioned structure can perform various operations which cannot be obtained by the CCD image sensor.
Since each pixel has a signal amplifying function, variations in characteristics of each pixel due to variations occurring during the process are
As a result, there is a problem that the image quality is deteriorated by being mixed in the video signal. The FPN due to the characteristic variation of each pixel is roughly divided into a light amount-dependent component corresponding to uneven sensitivity and a component corresponding to offset. Of these, the FPN that depends on the amount of light is said to be acceptable as long as it is 1% or less as a general video signal.
PN directly reduces the dynamic range of the image sensor. Therefore, as an image input device using the amplification type solid-state imaging device having the above-mentioned configuration, a method of canceling the offset FPN by some method is adopted.

There are roughly two methods for canceling the offset FPN. The first method is to cancel the offset FPN by storing the dark output of each pixel in the frame memory in advance and taking the difference between the video signal and the dark output at the time of image pickup (off. Chip cancellation method). The other method causes the operations of reading and storing, resetting, and reading to be performed within the horizontal video valid period t _H and the horizontal blanking period t _BL .
Offsetting FP by taking the difference between two signals
This is to cancel N (on-chip cancel method).

The former method has a problem in that a device such as a frame memory is required, so that the structure of the image input device becomes complicated and the cost becomes high. Furthermore, with this method, the output in darkness cannot be changed in real time, so when used for a long period of time or in an environment where the temperature changes drastically, there is a problem that the accuracy of cancellation deteriorates due to changes in the element characteristics. is there.

In the latter method, since a circuit for canceling the FPN is usually provided on the same substrate as the image sensor, there is a problem that the chip area increases and integration becomes difficult.

The present invention has been made to solve the above problems in the XY address type solid-state image pickup device using the conventional amplification type image pickup device, and does not use a frame memory and does not increase the chip area. Offset FP
It is an object of the present invention to provide an XY address type solid-state image pickup device using an amplification type image pickup element in which N can be canceled in real time.

[0013]

In order to solve the above problems, the present invention uses a non-destructive readable photoelectric conversion element as a pixel, and has a pixel array in which the pixel is two-dimensionally arranged. In the XY address type solid-state imaging device, means for outputting a plurality of video signals having different accumulation times from each pixel of the pixel array and means for outputting a difference signal of the plurality of video signals having different accumulation times are provided. Constitute.

In the solid-state image pickup device configured as described above, the FPN can be canceled without the need for the frame memory for storing the FPN.
Real-time FPN cancellation is possible. Also F
Since it is not necessary to provide the PN cancel circuit in the chip in which the pixel array is provided, there is no hindrance to integration and it is possible to suppress an increase in the chip area.

[0015]

EXAMPLES Next, examples will be described. FIG. 1 is a circuit configuration diagram of a first embodiment of a solid-state image pickup device according to the present invention. To simplify the explanation, the pixel array is set to 4 × 4,
Illustration of the grounding transistor shown in the conventional example of FIG. 5 is omitted. In the figure, 1-11 to 1-44 are two-dimensionally arranged in a non-destructive read-out phototransistor group typified by, for example, CMD, which constitutes each pixel, and the gate terminals of the CMD pixels in each row are Vertical selection line 5-1 ~
Commonly connected to 5-4. That is, CMD pixel group 1-1
The gate terminals of 1 to 1-14 are on the vertical selection line 5-1 and the gate terminals of the CMD pixel groups 1-21 to 1-24 are on the vertical selection line 5-2.
And so on. Vertical selection signals Φ _{G1 to} Φ _G4 are applied from the vertical scanning circuit 7 to the vertical selection lines 5-1 to 5-4, respectively.

Two column lines 8 are provided for each column of pixels.
-1a, 8-1b, ..., 8-4a, 8-4b are provided, and the source terminals of the CMD pixels in each column are alternately connected to different column lines every other column. That is, the source terminal of the CMD pixel 1-11 is connected to the column line 8-1a, the source terminal of the CMD pixel 1-21 is connected to the column line 8-1b, and so on. The column lines 8-1a, 8-1b, ~, 8-4a, 8-4b are respectively column selecting transistors 2-1a, 2-1b, ~, 2-4a ,.
The two video lines 4-1 and 4-2 are alternately connected via 2-4b. Two column selecting transistors 2-1a and 2-1b, 2-2a and 2 connected to two column lines in the same column
-2b, 2-3a and 2-3b, 2-4a and 2-4b have common gate selection signal lines 3-1, 3-2, 3-3, 3 respectively.
-Connected to -4. Column selection signal lines 3-1, 3-2, 3-3, 3-4
The column selection signals Φ _{S1 to} Φ _S4 are supplied to the horizontal scanning circuit 6 respectively.
Is applied more.

The two video lines 4-1 and 4-2 are provided with a changeover switch group 9-1 to 9-1, which are controlled by a changeover signal line 10.
It is connected to the signal lines 11-1 and 11-2 via 9-4. Signal line
The two video signals output from 11-1 and 11-2 are converted into voltages by current-voltage conversion amplifiers 12-1 and 12-2, respectively. The output signal on the signal line 11-1 side is set to 1 by the delay circuit 13.
After being delayed by the horizontal scanning period, it is input to the differential amplifier 14, while the output signal on the signal line 11-2 side is input to the differential amplifier 14 as it is, and the difference signal between the two is output from the differential amplifier 14. To be done.

FIG. 2 is a signal waveform diagram for explaining the operation of one field of the solid-state image pickup device having the configuration shown in FIG. Switching signal Φ applied to switching signal line 10
_I is changeover switch 9-3 and 9-4 are turned on when the pulse 20 is applied, otherwise changeover switch 9-1 and 9-2 are turned on. The vertical selection signals Φ _{G1 to} Φ _G4 applied to the vertical selection lines 5-1 to 5-4 are composed of the pulses of the read signal 22, the reset signal 23, and the overflow signal 21, and when those pulses are not applied. Becomes the signal accumulation state. Column selection signal lines 3-1, 3-2, 3-3, 3-4
The column selection signals Φ _{S1 to} Φ _S4 applied to the
The selection switches 2-1a to 2-4b are turned on only when is applied. On the time axis, t ₁ to t ₅ indicate the beginning of each horizontal scanning period.

Next, the operation will be described with reference to FIG.
First, at time t ₁ , the read signal 22 is output to the vertical selection signal Φ _G1 and the first selection signal is connected to the vertical selection line 5-1.
The CMD pixel in the row is selected. Further, since the switching signal Φ _I output to the switching signal line 10 is at “H” level, the switching switches 9-3 and 9-4 are on. In this state, when the column selection pulse 24 of the column selection signal Φ _S1 is output to the column selection signal line 3-1, the column selection transistor 2-1a.
And 2-1b turns on. Therefore, CMD pixel 1-11
Is output to the signal line 11-1 via the column selecting transistor 2-1a, the video line 4-1, and the switch 9-4.
However, since the second and subsequent rows are not selected, the signal line 11
Nothing is output to -2. The signal on the signal line 11-1 is converted into a voltage by the current-voltage conversion amplifier 12-1 and then delayed.
The signal is delayed by one horizontal period Δt _H , that is, a time of t ₂ −t ₁ by 13, and then input to the + terminal of the differential amplifier 14.

Next, the column selection pulse 24 is applied to the column selection signal line 3
When it is applied to -2, the signal of the CMD pixel 1-12 is output to the signal line 11-1 in the same manner. Similarly, CMD pixel 1
-13, 1-14 are output to the signal line 11-1 in this order, converted into a voltage by the current-voltage conversion amplifier 12-1, and then the delay circuit 13
Entered in. When this horizontal scanning is completed, the reset signal 23 is output to the vertical selection signal Φ _G1, and the CMD pixel column of the first row connected to the vertical selection line 5-1, that is, CMD
The signal charges of the pixels 1-11, 1-12, 1-13 and 1-14 are reset. At this time, the other vertical selection lines 5-2, 5-3,
An overflow signal 21 is applied to 5-4, and unnecessary excess charges overflow in the CMD pixels other than the first row.

Next, at time t ₂ , the second horizontal scanning starts. At this time, the read signal 22 is added to the vertical selection signals Φ _G1 and Φ _G2.
Is output and the CMD pixels in the first and second rows connected to the vertical selection lines 5-1 and 5-2 are selected. Further, since the changeover signal Φ _I becomes "L" level, the changeover switches 9-1 and 9-2 are turned on and 9-3 and 9-4 are turned off. In this state, when the column selection pulse 24 of the column selection signal Φ _S1 is output to the column selection signal line 3-1, the column selection transistor 2-1a.
And 2-1b turns on. Therefore, CMD pixel 1-11
After resetting, the signal is the column selection transistor 2
-1a, video line 4-1, signal line through switch 9-2
It is output to 11-2. The signal of the CMD pixel 1-21 is output to the signal line 11-1 via the column selecting transistor 2-1b, the video line 4-2 and the switch 9-1. Similarly, CMD pixels 1-21, 1-22, 1-2 are connected to the signal line 11-1.
The signal immediately after the reset of 3 and 1-24 is C on the signal line 11-2.
The signals of the MD pixels 1-11, 1-12, 1-13 and 1-14 are sequentially output. Similar to the first horizontal scanning, the signal to the signal line 11-1 is converted into a voltage by the current-voltage conversion amplifier 12-1 and then delayed by one horizontal period Δt _H by the delay circuit 13 and then the differential amplifier. Input to 14+ terminal. On the other hand, the signal output to the signal line 11-2 is directly input to the-terminal of the differential amplifier 14 after being converted into a voltage by the current-voltage conversion amplifier 12-2.

At this time, the + terminal of the differential amplifier 14 is delayed by the delay circuit 13 and is CM in the first horizontal scanning.
The signal of D pixel 1-11 is input. Therefore, the differential amplifier 14 causes the CMD pixel 1-11 in the first horizontal scan.
And the signal of the CMD pixel 1-11 in the second horizontal scanning are output. Similarly, the differential amplifier 14 sequentially outputs the difference between the signal in the first horizontal scanning and the signal in the second horizontal scanning of the CMD pixel 1-12, the CMD pixel 1-13.
The difference between the signal in the first horizontal scanning and the signal in the second horizontal scanning and the difference between the signal in the first horizontal scanning and the signal in the second horizontal scanning of CMD pixel 1-14 are output.

In the third and subsequent horizontal scanning operations as well, the same operation as in the second horizontal scanning operation is performed to obtain the difference between the signals read once and the signals read again after being reset in all pixels. it can.

Next, the reason why the offset component of the FPN can be canceled by such an operation will be described.
The magnitude V of the signal input to the + terminal of the differential amplifier 14
₊ Is the vertical and horizontal address of the pixel (m, n),
It is expressed by the following equation (1). V ₊ = α × (t _F −Δt _H + n × Δt _S ) + V _{0 (m, n)} (1)

Here, α is a parameter indicating sensitivity, t _F is one frame time, Δt _H is one horizontal period, that is, t ₂ −t.
₁ , n is the column number of the pixel, Δt _S is the pulse width of the horizontal scanning, that is, the pulse width of the column selection pulse 24, and V _{0 (m, n)} is the output of the pixel of address (m, n) converted to voltage And the offset component of FPN is also included in this. Further, (t _F −Δt _H + n × Δt _S ) multiplied by α represents the pixel accumulation time. On the other hand, the differential amplifier 14 −
The magnitude V _{− of the} signal input to the terminal is represented by the following equation (2) using the parameters common to the equation (1). V ₋ = α × (n × Δt _S ) + V _{0 (m, n)} ... (2)

Next, assuming that the gain of the amplifier is 1, the output V _OUT of the differential amplifier 14 is expressed by the following equation (3). V _OUT = V ₊ −V ₋ = α × (t _F −Δt _H ) (3) Therefore, the output of the differential amplifier 14 includes a term including the offset component of the FPN, V _{0 (m, Since n)} is removed, it is possible to obtain a signal having no FPN offset component.

Another advantage of the present embodiment is that, in the conventional method, as shown in equation (1), the accumulation time has a term of n × Δt _S , which depends on the column number of the pixel, and the columns are different. There was a drawback that the storage time also differed, but that problem is solved.

In the present embodiment, the one using the phototransistor with the CMD in mind as the pixel is shown, but the present invention is not limited to the CMD, and a MOS transistor is used.
Obviously, it can be applied to a solid-state image pickup device using an image sensor or another amplification type image pickup device such as SIT or AMI.

Next, a second embodiment will be described. Figure 3
FIG. 6 is a circuit configuration diagram for explaining a second embodiment,
FIG. 4 is a signal waveform diagram for explaining the operation of one frame. First, the circuit configuration will be described. Phototransistor group that can read non-destructively such as CMD 31-11 ~
31-44 are arranged two-dimensionally, and the gate terminals of the phototransistors in each row are commonly connected through the vertical selection lines 32-1 to 32-4. Vertical selection signals Φ _{G1 to} Φ _G4 are applied from the vertical scanning circuit 33 to the vertical selection lines 32-1 to 32-4, respectively. The source terminals of each row of the phototransistor group 31-11 to 31-44 are connected to the common signal lines 34-1 to 34-4.
Connected to the video line 36 via the vertical selection switches 35-1 to 35-4. The control terminals of the vertical selection switches 35-1 to 35-4 are connected to the horizontal scanning circuit 38 via horizontal selection lines 37-1 to 37-4, respectively. The current signal input to the video line 36 is converted into a voltage by the current-voltage conversion amplifier 39 and then divided into two parts, one of which is delayed by the delay circuit 40 and then connected to the + terminal of the differential amplifier 41. It The other is directly connected to the-terminal of the differential amplifier 41. The differential amplifier 41 outputs the voltage difference between the two to the output terminal 42.

Next, the operation of this embodiment will be described with reference to FIG. In FIG. 4, 50 is a read signal of the vertical selection signals Φ _{G1 to} Φ _G4 , 51 is also a reset signal, and 52 is a selection pulse of the horizontal selection signal. In this embodiment, horizontal scanning is performed twice during one horizontal period. First, the read signal 50 is applied to the vertical selection line 32-1 to select the first row of phototransistors. When horizontal scanning is performed in this state, the phototransistors 31-11, 31-12, 31 are connected to the video line 36.
The signal current corresponding to the accumulated charge is output in the order of -13 and 31-14. The signal voltage is converted into a voltage by the current-voltage conversion amplifier 39 and then divided into two, one of which is a differential amplifier 41.
Is input to the negative terminal and the other is delayed by Δt _{H / 2} by the delay circuit 40.
After being time-delayed, it is input to the + terminal of the differential amplifier 41. When the horizontal scanning is completed, the reset signal 51 is applied to the vertical selection line 32-1 and the phototransistors 31-11, 31-12, 31-13 and 31-14 of the first row are reset.

After that, the read signal 50 is applied to the vertical selection line 32-1 again, and the next horizontal scanning is performed, so that the signal of the phototransistor in the first row after the reset is changed to the phototransistor 31-11. , 31-12, 31-13,
It is output to the video line 36 in the order of 31-14. The signal current is converted into a voltage by the current-voltage conversion amplifier 39 and then divided into two, one of which is input to the negative terminal of the differential amplifier 41,
The other is input to the delay circuit 40. At this time, the differential amplifier
To the + terminal of 41, the signal in the previous horizontal scanning delayed by Δt _{H / 2} time is input. Therefore the differential amplifier
41 outputs the difference between the signal including the optical information of each pixel and the signal after reset. After that, this operation is repeated for all rows.

Next, the reason why the offset component of the FPN can be canceled by this operation will be described as in the first embodiment. The magnitude V _{+ of the} signal input to the + terminal of the differential amplifier 41 is the vertical and horizontal addresses of the pixel (m,
n) is represented by the following equation (4). _{V + = α × (t F} -Δt H / 2 + n × Δt S) + V 0 (m, n) ······ (4)

As in the case of the first embodiment, α is a parameter indicating sensitivity, t _F is one frame time, n is the pixel column number, Δt _S is the horizontal scanning sampling period, that is, the pulse width of the column selection pulse 52. , V _{0 (m, n)} is converted to voltage,
It is the offset component of the output of the pixel at the address (m, n), and the offset component of the FPN is also included in this. Also,
(t _F −Δt _{H / 2} + n × Δt _S ) multiplied by α represents the pixel accumulation time. On the other hand, the differential amplifier 41 - the magnitude of the signal input to the terminal V _- using the common parameters and the formula (4), is expressed by the following equation (5). V ₋ = α × (n × Δt _S ) + V _{0 (m, n)} ... (5)

Next, assuming that the gain of the amplifier is 1, the output V _OUT of the differential amplifier 41 is expressed by the following equation (6). V _OUT = V ₊ −V ₋ = α × (t _F −Δt _{H / 2} ) (6) Therefore, the output of the differential amplifier 41 includes the term V _{0 (} V _{0 ( Since (m, n)} is removed, it is possible to obtain a signal having no FPN offset component.

As described above, according to this embodiment, it is not necessary to provide a plurality of signal lines, and the FP has an extremely simple structure.
A solid-state imaging device capable of canceling N offset components is realized.

[0036]

As described above on the basis of the embodiments,
According to the present invention, it is possible to easily realize a solid-state imaging device having an FPN cancel function, which does not require a frame memory and does not need to provide a circuit for canceling in a chip, and therefore does not increase a chip area.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a signal waveform diagram for explaining the first embodiment shown in FIG.

FIG. 3 is a circuit configuration diagram showing a second embodiment.

FIG. 4 is a signal waveform diagram for explaining the operation of the second embodiment.

FIG. 5 is a circuit configuration diagram showing a configuration example of a conventional solid-state imaging device.

FIG. 6 is a signal waveform diagram for explaining the operation of the conventional example shown in FIG.

[Explanation of symbols]

 1-11 to 1-44 Phototransistor (CMD pixel) 2-1a to 2-4b Column selection transistor 3-1 to 3-4 Column selection signal line 4-1 and 4-2 Video line 5-1 to 5- 4 Vertical selection line 6 Horizontal scanning circuit 7 Vertical scanning circuit 8-1a to 8-4b Column line 9-1 to 9-4 Changeover switch 10 Changeover signal line 11-1, 11-2 Signal line 12-1, 12-2 Current-voltage conversion amplifier 13 Delay circuit 14 Differential amplifier

Claims (6)

[Claims] 1. An XY address type solid-state imaging device comprising a pixel array in which non-destructive readable photoelectric conversion elements are used as pixels and the pixels are arranged two-dimensionally, and a storage time from each pixel of the pixel array. And a means for outputting a difference signal between the plurality of video signals having different storage times, and a solid-state image pickup device. 2. The solid according to claim 1, further comprising means for delaying at least one signal of the plurality of video signals having different storage times by a time corresponding to a difference in storage time. Imaging device. 3. The solid-state image pickup device according to claim 1, wherein a MOS type image pickup element or an amplification type image pickup element is used as the photoelectric conversion element. 4. A plurality of vertical signal lines are provided for each column of the pixel array, and a plurality of rows are selected and read out at the same time, according to any one of claims 1 to 3. The solid-state imaging device described. 5. The solid-state imaging device according to claim 4, wherein a plurality of video signal lines are provided and a plurality of video signals having different storage times are simultaneously output. 6. The solid-state image pickup device according to claim 5, further comprising a switch for switching connection between the plurality of video signals and the output terminal during a horizontal blanking period.