JPH0311747A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0311747A JPH0311747A JP1147010A JP14701089A JPH0311747A JP H0311747 A JPH0311747 A JP H0311747A JP 1147010 A JP1147010 A JP 1147010A JP 14701089 A JP14701089 A JP 14701089A JP H0311747 A JPH0311747 A JP H0311747A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor device
- bonded
- auxiliary
- formation surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 124
- 239000004020 conductor Substances 0.000 claims abstract description 21
- 230000015572 biosynthetic process Effects 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 5
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 230000006870 function Effects 0.000 description 12
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
本発明は半導体装置に係り、特にフィルムキャリアに所
定のパターン状に取付けられた導体リードとこれらの導
体リードに接合された半導体素子とから構成される半導
体装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a semiconductor device comprising conductor leads attached to a film carrier in a predetermined pattern and a semiconductor element bonded to these conductor leads. The present invention relates to a semiconductor device.
［従来の技術］
今日電気機器にはＣＰＵ等の種々の半導体素子が極めて
広く使用されている。この半導体素子は印刷配線基板や
液晶表示基板等に一般に次のようにして接続される。即
ち、予め半導体素子に多数の導体リードを所定のパター
ン状に正確に接合した半導体装置を用意し、この半導体
装置の導体リードを印刷配線基板等の回路パターンに位
置合せした後に半田付けする。この半導体装置は一般に
フィルムキャリアにパターン状に貼着された多数の導体
リードに半導体素子を接合したフィルムキャリア半導体
装置として製造される。[Prior Art] Today, various semiconductor devices such as CPUs are extremely widely used in electrical equipment. This semiconductor element is generally connected to a printed wiring board, liquid crystal display board, etc. in the following manner. That is, a semiconductor device is prepared in advance in which a large number of conductor leads are accurately bonded to a semiconductor element in a predetermined pattern, and the conductor leads of this semiconductor device are aligned with a circuit pattern on a printed wiring board or the like and then soldered. This semiconductor device is generally manufactured as a film carrier semiconductor device in which a semiconductor element is bonded to a large number of conductor leads attached in a pattern to a film carrier.
第１０図及びｔｊｓ１１図は従来のフィルムキャリア半
導体装置を示したもので、フィルムキャリア１はスプロ
ケット孔２が上下に穿孔されており、中央部には半導体
素子用孔３とこの半導体素子用孔３の周囲に複数個の外
側リードボンディング孔４とが夫々穿孔されている。こ
れらの半導体素子用孔３と外側リードボンディング孔４
は所定間隔でフィルムキャリア１に沿って多数穿孔され
ている。多数の導体リード５は、インナーリード部５ａ
が半導体素子用孔３内に突出すると共にアウタリード部
５ｂが外側リードボンディング孔４を跨ぐように、所定
のパターン状にフィルムキャリア１上に貼着されている
。半導体素子６は第１１図に示されたように金やスズ等
のバンプ７によってインナーリード部５ａに接合され、
この半導体素子６はボッティング樹脂８によってボッテ
ィングコートされ外部の湿気や外力から保護されている
。FIG. 10 and FIG. 11 show a conventional film carrier semiconductor device, in which a film carrier 1 has sprocket holes 2 formed vertically, and a semiconductor element hole 3 and a semiconductor element hole 3 in the center. A plurality of outer lead bonding holes 4 are formed around each of the outer lead bonding holes 4 . These semiconductor element holes 3 and outer lead bonding holes 4
are perforated along the film carrier 1 at predetermined intervals. A large number of conductor leads 5 are connected to an inner lead portion 5a.
is attached to the film carrier 1 in a predetermined pattern so that the outer lead portion 5b protrudes into the semiconductor element hole 3 and the outer lead portion 5b straddles the outer lead bonding hole 4. As shown in FIG. 11, the semiconductor element 6 is bonded to the inner lead portion 5a by bumps 7 made of gold, tin, etc.
This semiconductor element 6 is coated with a botting resin 8 to protect it from external moisture and external force.
このようなフィルムキャリア半導体装置は、示を省略し
たスプロケットによって移送されたフィルムキャリア１
に半導体素子用孔３と外側リードボンディング孔４とを
所定間隔で順次、穿孔すると共に多数の導体リード５を
貼着し、次いでこれらの導体リード５に半導体素子６を
接合し、その後にボッティング樹脂８によってボッティ
ングコートすることによって製造される。Such a film carrier semiconductor device includes a film carrier 1 transported by a sprocket (not shown).
Semiconductor element holes 3 and outer lead bonding holes 4 are sequentially drilled at predetermined intervals, and a large number of conductor leads 5 are pasted thereon, and then semiconductor elements 6 are bonded to these conductor leads 5, and then a botting process is performed. It is manufactured by botting coating with resin 8.
この後、外側リードボンディング孔４のアウタリード部
５ｂと、隣接する外側リードボンディング孔４の間のフ
ィルム１とを切断し、即ち打抜きフォーミングして半導
体装置をフィルムキャリア１から取出す。この取出され
た半導体装置はアウタリード部５ｂが印刷配線基板や液
晶表示基板等の回路パターンに半田付けされる。Thereafter, the outer lead portion 5b of the outer lead bonding hole 4 and the film 1 between the adjacent outer lead bonding holes 4 are cut, that is, punched and formed, and the semiconductor device is taken out from the film carrier 1. The outer lead portion 5b of the extracted semiconductor device is soldered to a circuit pattern of a printed wiring board, a liquid crystal display board, or the like.
［発明が解決しようとする課題］
ところが、上述のような従来の半導体装置は基本的な機
能を有する半導体素子に新たな機能を追加する必要が生
じた場合には、この機能を有する別個の半導体装置を用
意してこれらの複数個の半導体装置を印刷配線基板や液
晶表示基板等に個々に接続するか、それとも従来の半導
体素子を両方の機能を具備した新たな半導体素子に変え
る必要があった。この前者の方法では印刷配線基板や液
晶表示基板等の基板を作り直さねばならないと共に基板
自体が大きくなってしまうという問題があり、また後者
の方法では、新しい半導体素子を開発しなければならず
比較的長期の開発期間を要すると共にコストアップを招
くという問題があった。[Problems to be Solved by the Invention] However, in the conventional semiconductor device as described above, when it becomes necessary to add a new function to a semiconductor element having a basic function, it is necessary to add a separate semiconductor device having this function. It was necessary to prepare equipment and individually connect these multiple semiconductor devices to printed wiring boards, liquid crystal display boards, etc., or to replace conventional semiconductor elements with new semiconductor elements that had both functions. . The former method has the problem of having to remanufacture the printed wiring board, liquid crystal display board, etc., and the board itself becomes large, while the latter method requires the development of a new semiconductor element, which is relatively large. There were problems in that it required a long development period and increased costs.
そこで、本発明の目的は基板や半導体素子を作り直すこ
となく、新たな機能の半導体素子を追加することのでき
る半導体装置を提供することにある。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device to which a semiconductor element with a new function can be added without remanufacturing the substrate or the semiconductor element.
［課題を解決するための手段］
この目的を達成するために本発明は、可とう性の絶縁フ
ィルム上に所定のパターン状に取付けられた複数本の導
体リードと、これらの導体リードにバンプによって接合
された半導体素子とを具備する半導体装置において、上
記半導体素子に保持された補助半導体素子を具備し、こ
の補助半導体素子は回路形成面が上記半導体素子の回路
形成面にバンプによって直接に接合されていることを特
徴とするものである。[Means for Solving the Problems] In order to achieve this object, the present invention includes a plurality of conductor leads attached in a predetermined pattern on a flexible insulating film, and bumps on these conductor leads. A semiconductor device comprising a bonded semiconductor element includes an auxiliary semiconductor element held by the semiconductor element, the auxiliary semiconductor element having a circuit forming surface directly bonded to the circuit forming surface of the semiconductor element by a bump. It is characterized by the fact that
この構成にあっては、上記半導体素子の回路形成面には
、外周縁に沿って複数のリード用ボンディングパッドが
形成されていると共にこれらのリード用ボンディングパ
ッドの内側に複数の補助半導体素子用ボンディングパッ
ドが形成され、上記リード用ボンディングパッドは上記
導体リードに接合され、上記補助半導体素子用ボンディ
ングパッドは上記補助半導体素子の回路形成面に接合さ
れていることが望ましい。In this configuration, a plurality of lead bonding pads are formed along the outer periphery of the circuit forming surface of the semiconductor element, and a plurality of auxiliary semiconductor element bonding pads are formed inside these lead bonding pads. It is preferable that pads are formed, the lead bonding pad being bonded to the conductor lead, and the auxiliary semiconductor element bonding pad being bonded to the circuit forming surface of the auxiliary semiconductor element.
［作 用］
新たな機能を有する補助半導体素子は半導体素子に保持
されると共にその半導体素子に直接に接続される。従っ
て基板や半導体素子を新たに作り直すことなく、既存の
半導体装置に新たな半導体機能を簡単に追加することが
できる。[Function] The auxiliary semiconductor element having a new function is held by the semiconductor element and is directly connected to the semiconductor element. Therefore, new semiconductor functions can be easily added to an existing semiconductor device without having to recreate a new substrate or semiconductor element.
［実施例］
次に、本発明による半導体装置の一実施例を第１０図お
よび第１１図と同部分には同一符号を付して示した第１
図乃至第９図を参照して説明する。[Example] Next, an example of the semiconductor device according to the present invention is shown in Fig. 1, in which the same parts as in Figs.
This will be explained with reference to FIGS. 9 to 9.
第１図及び第２図において、フィルムキャリア１には半
導体素子用孔３とこの半導体素子用孔３の周囲に複数個
の外側リードボンディング孔４とが夫々穿孔されている
。これらの半導体素子用孔３と外側リードボンディング
孔４は所定間隔でフィルムキャリア１に沿って多数穿孔
されている。1 and 2, a film carrier 1 is provided with a semiconductor element hole 3 and a plurality of outer lead bonding holes 4 around the semiconductor element hole 3, respectively. A large number of these semiconductor element holes 3 and outer lead bonding holes 4 are bored along the film carrier 1 at predetermined intervals.
多数の導体リード５は、インナーリード部５ａが半導体
素子用孔３内に突出すると共にアウタリード部５ｂが外
側リードボンディング孔４を跨ぐように、所定のパター
ン状にフィルムキャリア１上に貼着されている。主半導
体素子６は金やスズ等のバンプ７によってインナーリー
ド部５ａの先端に接合されている。以上の構成は前述し
た従来の半導体装置の構成と同一である。A large number of conductor leads 5 are pasted on the film carrier 1 in a predetermined pattern such that the inner lead portion 5a protrudes into the semiconductor element hole 3 and the outer lead portion 5b straddles the outer lead bonding hole 4. There is. The main semiconductor element 6 is bonded to the tip of the inner lead portion 5a by a bump 7 made of gold, tin, or the like. The above configuration is the same as that of the conventional semiconductor device described above.
主半導体素子６の中央部には補助半導体素子９がフェー
スダウンボンディングされている。即ち、主半導体素子
６の回路形成面６ａには補助゛Ｙ導体素子９の回路形成
面９ａがバンプ１０によって接合されている。主半導体
素子６の回路形成面６ａには、第３図に示されたように
外周縁に沿って複数個のリード用ボンディングパッド１
１が形成されると共にこのリード用ボンディングパッド
１１の内側には複数個の補助半導体素子用ボンディング
パッド１２が形成されている。リード用ボンディングパ
ッド１１は導体リード５に接合され、補助半導体素子用
ボンディングパッド１２は補助半導体素子９に接合され
る。An auxiliary semiconductor element 9 is face-down bonded to the center of the main semiconductor element 6. That is, the circuit forming surface 9a of the auxiliary Y conductor element 9 is bonded to the circuit forming surface 6a of the main semiconductor element 6 by bumps 10. On the circuit forming surface 6a of the main semiconductor element 6, a plurality of lead bonding pads 1 are provided along the outer periphery as shown in FIG.
1 is formed, and a plurality of auxiliary semiconductor element bonding pads 12 are formed inside this lead bonding pad 11. The lead bonding pad 11 is bonded to the conductor lead 5, and the auxiliary semiconductor element bonding pad 12 is bonded to the auxiliary semiconductor element 9.
第１図に示されたように、フェースダウンボンディング
された主半導体素子６と補助半導体索−Ｆ９とはポツテ
ィング樹脂８によってボッティングコートされている。As shown in FIG. 1, the face-down bonded main semiconductor element 6 and auxiliary semiconductor wire F9 are potted coated with potting resin 8.
なお、補助半導体素子９は半導体装置に機能追加が可能
なものであれば任意の半導体素子を使用することができ
る。例えば、主半導体素子６がＣＰＵである場合にはこ
の補助半導体素子つとしてメモリＩＣを使用すれば、演
算機能と記憶機能とを兼備えた多機能な半導体装置が構
成される。Note that any semiconductor element can be used as the auxiliary semiconductor element 9 as long as it can add functionality to the semiconductor device. For example, when the main semiconductor element 6 is a CPU, if a memory IC is used as one of the auxiliary semiconductor elements, a multifunctional semiconductor device having both an arithmetic function and a memory function is constructed.
次に、この半導体装置の製造方法を説明する。Next, a method for manufacturing this semiconductor device will be explained.
第４図において、主半導体素子６のリード用ボンディン
グパッド１１とインナーリード部５ａとが顕微鏡を使用
した目視観察によって、または視覚認識装置を使用して
高精度に位置合せされる。In FIG. 4, the lead bonding pads 11 of the main semiconductor element 6 and the inner lead portions 5a are aligned with high precision by visual observation using a microscope or by using a visual recognition device.
リード用ボンディングパッド１１とインナーリード部５
ａとの一方にバンプ７が付着されており、この位置合せ
されたインナーリード部５ａを熱圧若によりリード用ボ
ンディングパッド１１に接合する。この後に、この主半
導体素子６の回路形成面６ａのボンディングパッドに補
助半導体索子９の回路形成面９ａのボンディングパッド
を高精度に位置合せして第５図に示したように両者をバ
ンプ１０によ゛って接合する。Lead bonding pad 11 and inner lead part 5
A bump 7 is attached to one side of the inner lead portion 5a, and the aligned inner lead portion 5a is bonded to the lead bonding pad 11 by heat and pressure. After this, the bonding pads on the circuit-forming surface 9a of the auxiliary semiconductor cable 9 are aligned with the bonding pads on the circuit-forming surface 6a of the main semiconductor element 6 with high precision, and both are connected to the bump 10 as shown in FIG. Then join.
第６図と第７図は主半導体素子６と補助半導体素子９と
を先にフェイスダウンボンディングした後に、主半導体
素子６を導体リード５に接合する例を示している。なお
、この例の場合には、主半導体素子６を導体リード５に
接合するのに使用するボンディング工具１３はインナー
リード部５ａを加圧する際に補助半導体素子９を加圧し
ないように中央部に凹部１４が形成されている。6 and 7 show an example in which the main semiconductor element 6 and the auxiliary semiconductor element 9 are first face-down bonded, and then the main semiconductor element 6 is bonded to the conductor lead 5. In this example, the bonding tool 13 used to bond the main semiconductor element 6 to the conductor lead 5 is placed in the center so as not to pressurize the auxiliary semiconductor element 9 when pressurizing the inner lead portion 5a. A recess 14 is formed.
第８図と第９図は上記実施例の変形内を示したもので、
２ｇＪの補助半導体素子９Ａ、９Ｂが主半導体素子６に
フェースダウンボンディングされている。なお、これら
の２ｒｒＭの補助半導体索子９Ａ。Figures 8 and 9 show variations of the above embodiment.
Auxiliary semiconductor elements 9A and 9B of 2 gJ are face-down bonded to the main semiconductor element 6. In addition, these 2rrM auxiliary semiconductor cords 9A.
９Ｂは機能及び大きさが同一の素子であっても、異なる
機能または異なる大きさの素子であってもよい。更に、
三個以上の補助半導体素子をフェースダウンボンディン
グしてもよい。9B may be elements with the same function and size, or may be elements with different functions or sizes. Furthermore,
Three or more auxiliary semiconductor elements may be face-down bonded.
［発明の効果コ
以上の説明から明らかなように、本発明によれば、補助
半導体素子は回路形成面が半導体素子の回路形成面にバ
ンプによって直接接合されるため、半導体装置を搭載す
る基板や半導体素子を作り直すことなく、既存の半導体
装置に新たな半導体機能を簡単に追加することができる
と共に、開発期間の大幅な短縮を図ることができる。[Effects of the Invention] As is clear from the above description, according to the present invention, the circuit forming surface of the auxiliary semiconductor element is directly bonded to the circuit forming surface of the semiconductor element by bumps, so that it is possible to attach the circuit forming surface of the auxiliary semiconductor element to the circuit forming surface of the semiconductor element. New semiconductor functions can be easily added to existing semiconductor devices without re-manufacturing semiconductor elements, and the development period can be significantly shortened.
第１図は本発明による半導体装置の一実施例を示した断
面図、第２図は上記実施例を示した斜視図、第３図は上
記実施例の主半導体素子の回路形成面のボンディングパ
ッドの位置関係を示した斜視図、第４図と第５図は上記
実施例の半導体装置を製造する一方法を示した断面図、
第６図と第７図は上記実施例の半導体装置を製造する別
の方法を示した断面図、第８図と第９図は上記実施例の
変形例を夫々示した断面図と斜視図、第１０図と第１１
図は従来の半導体装置を夫々示した平面図と断面図であ
る。
１・・・フィルムキャリア、５・・・導体リード、６・
・・半導体素子１．６ａ・・・回路形成面、７・・・バ
ンプ、９・・・補助半導体素子、９ａ・・・回路形成面
、１０・・・バンプ。FIG. 1 is a sectional view showing one embodiment of a semiconductor device according to the present invention, FIG. 2 is a perspective view showing the above embodiment, and FIG. 3 is a bonding pad on the circuit forming surface of the main semiconductor element of the above embodiment. 4 and 5 are cross-sectional views showing one method of manufacturing the semiconductor device of the above embodiment,
6 and 7 are sectional views showing another method of manufacturing the semiconductor device of the above embodiment, and FIGS. 8 and 9 are sectional views and perspective views showing modifications of the above embodiment, respectively. Figures 10 and 11
The figures are a plan view and a cross-sectional view, respectively, showing a conventional semiconductor device. 1... Film carrier, 5... Conductor lead, 6...
...Semiconductor element 1.6a...Circuit formation surface, 7...Bump, 9...Auxiliary semiconductor element, 9a...Circuit formation surface, 10...Bump.
Claims (1)
付けられた複数本の導体リードと、これらの導体リード
にバンプによって接合された半導体素子とを具備する半
導体装置において、上記半導体素子に保持された補助半
導体素子を具備し、この補助半導体素子は回路形成面が
上記半導体素子の回路形成面にバンプによって直接に接
合されていることを特徴とする半導体装置。 ２、上記半導体素子の回路形成面には、外周縁に沿って
複数のリード用ボンディングパッドが形成されていると
共にこれらのリード用ボンディングパッドの内側に複数
の補助半導体素子用ボンディングパッドが形成され、上
記リード用ボンディングパッドは上記導体リードに接合
され、上記補助半導体素子用ボンディングパッドは上記
補助半導体素子の回路形成面に接合されていることを特
徴とする請求項１記載の半導体装置。[Claims] 1. In a semiconductor device comprising a plurality of conductor leads attached in a predetermined pattern on a flexible insulating film and a semiconductor element bonded to these conductor leads by bumps. . A semiconductor device comprising an auxiliary semiconductor element held by the semiconductor element, the circuit forming surface of the auxiliary semiconductor element being directly bonded to the circuit forming surface of the semiconductor element by a bump. 2. On the circuit forming surface of the semiconductor element, a plurality of lead bonding pads are formed along the outer periphery, and a plurality of auxiliary semiconductor element bonding pads are formed inside these lead bonding pads, 2. The semiconductor device according to claim 1, wherein the lead bonding pad is bonded to the conductor lead, and the auxiliary semiconductor element bonding pad is bonded to the circuit forming surface of the auxiliary semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1147010A JPH0311747A (en) | 1989-06-09 | 1989-06-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1147010A JPH0311747A (en) | 1989-06-09 | 1989-06-09 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0311747A true JPH0311747A (en) | 1991-01-21 |
Family
ID=15420512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1147010A Pending JPH0311747A (en) | 1989-06-09 | 1989-06-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0311747A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004057668A3 (en) * | 2002-12-20 | 2004-08-12 | Koninkl Philips Electronics Nv | Electronic device and method of manufacturing same |
| US9273464B2 (en) | 2009-09-01 | 2016-03-01 | Roger C. Roen | Structurally integrated accessible floor system |
-
1989
- 1989-06-09 JP JP1147010A patent/JPH0311747A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004057668A3 (en) * | 2002-12-20 | 2004-08-12 | Koninkl Philips Electronics Nv | Electronic device and method of manufacturing same |
| US9273464B2 (en) | 2009-09-01 | 2016-03-01 | Roger C. Roen | Structurally integrated accessible floor system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5886876A (en) | Surface-mounted semiconductor package and its manufacturing method | |
| JPH04256343A (en) | Flip-chip package for integrated circuit use | |
| JP2005322921A (en) | Flip-chip semiconductor package for testing bumps and method of fabricating same | |
| JP2005079581A (en) | Tape substrate, semiconductor chip package using tape substrate, and lcd device using semiconductor chip package | |
| KR20090026891A (en) | Wiring substrate, tape package having the same, display device having the same, method of manufacturing the same, method of manufacturing a tape package having the same and method of manufacturing a display device having the same | |
| JP2753696B2 (en) | Automatic bonding structure of semiconductor package tape | |
| US7449364B2 (en) | Device and method for including passive components in a chip scale package | |
| JPH0311747A (en) | Semiconductor device | |
| JPH06283561A (en) | Package of semiconductor device | |
| JPH10233401A (en) | Semiconductor device | |
| KR100473414B1 (en) | Smt mounted tab package structure | |
| US5519579A (en) | Method and apparatus for replacing directly attached chip | |
| JPS6244851B2 (en) | ||
| JP3692810B2 (en) | Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus | |
| KR100385088B1 (en) | Multi-chip semiconductor module and manufacturing process thereof | |
| JPS6154656A (en) | Semiconductor device | |
| US20060000718A1 (en) | Substrate plating methods and apparatus | |
| JP2626081B2 (en) | Film carrier semiconductor device | |
| JPS61225827A (en) | Mounting structure of semiconductor element | |
| JPH03293739A (en) | Semiconductor device | |
| JPH0751794Y2 (en) | Semiconductor mounting structure | |
| JP2555916B2 (en) | Film carrier semiconductor device | |
| KR940004278Y1 (en) | Cot package | |
| JPH0362538A (en) | Electrode terminal | |
| JP2006071508A (en) | Semiconductor device manufacturing method |