JP2006071508A - Semiconductor device manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the production cost of a BGA structure semiconductor. <P>SOLUTION: The semiconductor device manufacturing method comprises a process for preparing a semiconductor chip 2 provided with a plurality of electrode terminals 5 on its principal plane, a process for preparing a substrate 4a provided with a plurality of test pads 22 formed on areas other than the area on which the semiconductor chip 2 is installed, a process for forming a lead 6 for electrically connecting an electrode terminal 5 with the test pads 22 on the substrate 4a, and a process for testing the semiconductor chip 2 by bringing a voltage impressing contact pin 33 into contact with the plurality of test pads 22. Even for BGA structure semiconductor devices having different external shapes, pin pitches, and arrangements, a test is performed with the position of the contact pin 33 being in contact with the test pads 22 unchanged by standardizing the arrangement of the test pads 22. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to the manufacture of a semiconductor device having a BGA (Ball Grid Array) structure.

  As electronic devices become more sophisticated and smaller and lighter, semiconductor devices used in electronic devices are required to be smaller, lighter, and thinner. As one of the semiconductor devices that can meet this demand, A surface-mount type BGA semiconductor device is known. In this BGA structure semiconductor device, a plurality of external electrode terminals made of a metal member such as ball-shaped solder (solder ball) are arranged on the front surface or the back surface of the substrate and electrically connected to a semiconductor chip mounted on the substrate. Has a structure.

In such a BGA structure semiconductor device, a contact pin (inspection pin) group arranged in the same arrangement as the external electrode terminals in voltage application (hereinafter collectively referred to as a test) such as a burn-in test and measurement of electrical characteristics. In general, a jig (socket) is used, and contact pins are brought into direct contact with external electrode terminals (see, for example, Patent Document 1).
Japanese Patent No. 3431873

  However, when the test is performed by directly contacting the external electrode terminal and the contact pin, there is a risk of causing damage (damage) to the external electrode terminal. In particular, since the burn-in test is performed at a high temperature, the damage is increased and the terminal is deformed. For this reason, a defect occurs in the external electrode terminal, and the manufacturing yield of the semiconductor device decreases.

  Further, the socket must be prepared for each of a plurality of BGA structure semiconductor devices having different external shapes with different external shapes (sizes) of the BGA structure semiconductor devices, pin pitches and arrangements of the external electrode terminals. Furthermore, in response to the trend of increasing signal input / output due to higher performance and higher integration of semiconductor devices in the future, sockets were prepared together with BGA structure semiconductor devices of different external shapes. Cost increases.

  An object of the present invention is to reduce the manufacturing cost of a semiconductor device.

  Another object of the present invention is to improve the manufacturing yield of semiconductor devices.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A method of manufacturing a semiconductor device according to the present invention includes a step of preparing a semiconductor chip having a plurality of electrode terminals on a main surface, and a substrate having a plurality of test pads formed in a region outside the region on which the semiconductor chip is mounted. Preparing a wiring for electrically connecting the electrode terminal and the test pad to the substrate, and applying a voltage to the semiconductor chip through the plurality of test pads. It is characterized by having.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  By sharing the test environment of the BGA structure semiconductor device, the manufacturing cost of the semiconductor device can be reduced.

  Further, the manufacturing yield of the semiconductor device can be improved by performing the test without damaging the external electrode terminal of the BGA structure semiconductor device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
In this embodiment, an example in which the present invention is applied to a semiconductor device having a BGA (Ball Grid Array) structure using a tape for TAB (Tape Automated Bonding) will be described.

  The structure of the semiconductor device 1 described in this embodiment will be described with reference to FIGS. 1 is a schematic plan view showing the semiconductor device 1, FIG. 2 is a schematic plan view in which the sealing portion 13 of the semiconductor device 1 in FIG. 1 is omitted, and FIG. 3 is a cross-sectional view of the semiconductor device 1 in FIG. FIG. 4 is a schematic sectional view, and FIG. 4 is a bottom view of the semiconductor device 1 of FIG.

  The semiconductor device 1 shown in this embodiment is a fan-out BGA structure semiconductor device. The semiconductor device 1 includes a substrate 4 made of TAB tape, a semiconductor chip 2 mounted on the substrate 4, an electrode terminal 5 formed on the main surface of the semiconductor chip 2, and one end (hereinafter referred to as a tip) as an electrode. An inner lead (hereinafter referred to as a lead) 6 which is also a wiring electrically connected to the terminal 5, an external electrode terminal 3 formed on the substrate 4 electrically connected to the lead 6 extending from the tip, and a semiconductor And a sealing portion 13 that covers and protects the main surface of the chip 2.

  The semiconductor chip 2 is made of, for example, p-type single crystal silicon, and is diced and separated from a semiconductor wafer (semiconductor substrate). In the semiconductor chip 2, a semiconductor element constituting an IC circuit or an LSI circuit is formed on the main surface of the semiconductor substrate, and an electrode terminal 5 having a center pad structure connected to the semiconductor element is formed. ing. In FIG. 2, the semiconductor chip 2 is mounted on the back side of the substrate 4, but is indicated by a dotted line for ease of explanation.

  The electrode terminal 5 is made of, for example, gold. For example, a power supply terminal and a GND terminal for supplying power for driving the semiconductor element, a power supply terminal for a clock that determines the operation timing of the semiconductor element, and an input / output of the semiconductor element It is composed of input / output terminals formed on the semiconductor chip 2 for inputting / outputting signals to / from an external circuit.

  The substrate 4 is cut out from a TAB tape wound in a reel shape, and the TAB tape is an insulating tape (tape substrate) having a thickness of about 50 μm, and is formed of, for example, a polyimide resin film. Has been. A plurality of leads 6 are formed on one surface (upper surface) of the substrate 4, and the leads 6 formed near the edge (outer periphery) of the substrate 4 are for protecting the leads 6. An insulating protective film 8 is formed. In FIG. 1 and FIG. 2, the protective film 8 is omitted.

  The leads 6 formed on the substrate 4 are made of printed wiring formed by using a printed wiring technique, are formed by patterning a copper foil, and a gold plating film is formed on the surface thereof. The protective film 8 is made of, for example, a solder resist film having a film thickness of about 20 μm, and protects the leads 6 and prevents the substrate 4 from warping.

  Further, openings 9 are formed in the substrate 4 at a predetermined pitch along each side near the edge of the substrate 4 in order to form the external electrode terminals 3. In the opening 9, the lead 6 extends so as to cross. The lead 6 existing in the opening 9 serves as a pad for forming the external electrode terminal 3. The external electrode terminal 3 is formed on the pad made of the lead 6 and is made of a metal member such as ball-shaped solder (solder ball). A plating film is formed on the upper and lower (front and back) surfaces of the pad made of the lead 6. That is, in order to make it easy to form the external electrode terminal 3 on the lower surface of the pad, and to make it easier to connect the external electrode terminal of the upper semiconductor device to the upper surface of the lead 6 when the semiconductor device 1 is stacked and used. Plating films are formed on the upper and lower surfaces of the pad.

  In addition, an elongated opening (device hole) 10 is provided at the center of the substrate 4, and the lead 6 protrudes into the opening 10. The tips of the leads 6 are connected to the electrode terminals 5 of the semiconductor chip 2 having a center pad structure. In addition, openings 11 are provided along the opening 10 on both sides of the opening 10. A rectangular frame-shaped opening (slit) 12 is provided inside the opening 9 and outside the semiconductor chip 2 fixed to the substrate 4.

  The opening 12 extends linearly along each side of the substrate 4 and has a width of about 500 μm, for example. By this opening 12, the substrate 4 is divided into an inner part (inner part, product area part) of the opening part 12 and an outer part (outer part, outside of the product area). Therefore, the inside where the semiconductor chip 2 is to be mounted is supported to the outside through the opening 12 and the connecting portion 14 between the openings 12.

  Further, the opening 12 applies stress to the substrate 4 when stress or thermal stress is applied to the substrate 4 itself or a member constituting the semiconductor device including the substrate 4 after each stage of manufacturing the semiconductor device 1 or after manufacturing. It is provided in order to prevent the portion including the substrate 4 from being warped by dividing the inner region and the outer region. The opening 12 also serves to stop the outflow of resin to the outside (outside of the opening 12) when resin sealing is performed.

  The opening 11 selectively provided on the substrate 4 inside the opening 12 warps due to a difference in thermal expansion coefficient between the substrate 4 made of resin (polyimide resin) and the lead 6 formed of a conductor (copper foil). It is for cutting and reducing.

  A lead (wiring) 6 extending through each opening 9 is bent as necessary, and one end (inner end) of the lead 6 extends from one of the long sides of the opening 10 into the opening 10. The other has a structure that reaches the outer edge of the substrate 4. The other end of the lead 6 of the semiconductor device 1 extends to the outer edge of the substrate 4 when the test pad (test pad) described later and the lead 6 are connected in the precursor of the semiconductor device 1. This is because the test pad was removed from the precursor by dicing or the like when the apparatus 1 was formed.

  A sealing portion 13 is formed of an insulating resin on the main surface side of the semiconductor chip 2 where the electrode terminals 5 are provided. The sealing portion 13 has a structure that covers the substrate 4 and the leads 6 on the main surface side of the semiconductor chip 2. The sealing portion 13 covers the entire area inside the opening 12 and has a structure that also seals the opening 10 and the opening 11.

  Next, the board | substrate 4a used for the precursor (piece | piece) of the semiconductor device 1 is demonstrated using FIGS. FIG. 5 is a schematic plan view showing the substrate 4a, FIG. 6 is a schematic plan view showing the arrangement of test pads (inspection pads) 22 formed on the substrate 4a, and FIGS. It is a schematic plan view showing a wiring pattern 23 connected (connected) to an opening 9. The wiring pattern 23 includes the lead 6 described above.

  A substrate 4a shown in FIG. 5 is cut out from a TAB tape wound in a reel shape, and constitutes the substrate 4 of the semiconductor device 1 described above. The TAB tape is an insulating tape (tape substrate) having a thickness of about 50 μm, and is formed of, for example, a polyimide resin film. Accordingly, the substrate 4a is in a state of being cut from a TAB tape continuously wound in a reel shape, and for example, its shape is a strip shape as shown in FIG.

  On this substrate 4a, a product region 21 (region surrounded by a dotted line in the figure) where the above-described semiconductor device 1 is formed, a test pad 22, a sprocket hole 24, an opening 20 and a wiring pattern 23 are formed. Area (excluding the product area 21, hereinafter referred to as a test area).

  For example, 30 pads (60 pads in total) are arranged at predetermined intervals on both ends of the test pad 22 along the longitudinal direction of the strip-shaped substrate 4a. This test pad 22 is a group of contact pins (inspection pins) arranged in the same arrangement as the test pad 22 when a voltage is applied (generally referred to as a test) such as a burn-in test of the semiconductor device 1 or measurement of electrical characteristics. It is provided in order to make it contact with the contact pin of the jig | tool (socket) which has this. Therefore, the test pad 22 is made of a conductor, and is made of, for example, a printed wiring formed using a printed wiring technique in the same manner as the lead 6 (wiring pattern 23) described above, and is formed by patterning a copper foil. A gold plating film is formed on the substrate.

  Conventionally, the test is performed by directly contacting the external electrode terminal and the contact pin, and there is a risk of causing damage (damage) to the external electrode terminal. Particularly in the burn-in test, since the temperature is high, the damage becomes large, causing problems such as deformation of the terminals, and further defects in the external electrode terminals, which reduces the reliability of the semiconductor device. However, in the present embodiment, when the test is performed, the terminal brought into contact with the contact pin is not the external electrode terminal but the test pad 22, so that the test can be performed without causing any damage to the external electrode terminal. Thereby, the reliability of the semiconductor device can be improved.

  The wiring pattern 23 includes the lead 6 of the semiconductor device 1 described above. Since the lead 6 has been described above, the wiring pattern 23 from the opening 9 where the external electrode terminal is formed to the test pad 22 will be described here.

  One (tip) of the wiring pattern 23 is disposed at a position where it is connected to the electrode terminal of the semiconductor chip, and the other is electrically connected to the test pad 22 through the opening 9 in a direction extending from the tip of the wiring pattern 23. Has been. For this reason, the wiring pattern 23 is formed in the product region 21 and the test region.

  That is, the wiring pattern 23 electrically connects the test pad 22 fixedly arranged on the substrate 4a and the opening 9 whose arrangement is determined by the outer shape (size) of the semiconductor device, the pin pitch of the external electrode terminals, and the arrangement. Connect. Therefore, even if the arrangement of the openings 9 formed in the substrate 4a is different depending on the semiconductor device having different outer shapes, pin pitches, and arrangements of the semiconductor device, the wiring pattern 23 is deformed to form the substrate 4a. Can be electrically connected to the test pad 22 fixed to the electrode terminal of the semiconductor chip. In FIG. 5, the wiring pattern 23 that is not connected to the test pad 22 also exists because the purpose of arranging the wiring pattern 23 is to connect to an electrode terminal on the semiconductor chip, and a test that does not correspond to the electrode terminal. This is because it is not necessary to form the wiring pattern 23 to be connected to the pad 22.

  Further, the substrate 4a has sprocket holes 24 formed at regular intervals on both sides along the short direction, and the sprocket gear meshes with the sprocket holes 24 to form the reel 4a. Is pitch fed.

  The substrate 4a is provided with openings 20 that are refracted at right angles at portions that correspond to the corners of the product region 21 and the test region. The semiconductor device 1 described above can be manufactured by cutting the connecting portion between the openings 20 in the final stage of manufacturing the semiconductor device.

  FIG. 6 is a schematic plan view showing the test pad 22 formed on the substrate 4a shown in FIG. In the figure, symbols such as VDD and CLK written on the test pad 22 are general abbreviations indicating functions of terminals of the semiconductor device. For example, a power supply for driving a semiconductor element A terminal VDD, a power supply terminal CLK for a clock that determines the operation timing of the semiconductor element, and the like.

  As described above, for example, 30 pads (60 pads in total) are arranged at predetermined intervals on both sides of the test pad 22 along the longitudinal direction of the strip-shaped substrate 4a. By arranging the test pad 22 at a predetermined position on the substrate 4a, it is possible to make the arrangement of the contact pins of the socket used during the test common. That is, even if the arrangement of the openings 9 determined from the outer shape (size) of the semiconductor device, the pitch and arrangement of the external electrode terminals differs depending on the type of the semiconductor device (product), the wiring connected to the test pad 22 By changing the pattern 23, a test can be performed using a common socket without changing the arrangement of the contact pins of the socket. Further, by using a common socket, that is, by making the test environment of the BGA structure semiconductor device common, the product cost of the semiconductor device can be reduced.

  7 to 9 are schematic plan views showing an example of the wiring pattern 23 formed on the substrate 4a. Note that symbols such as VDD and CLK described in the test pad 22 and the opening 9 are general abbreviations indicating functions of terminals of the semiconductor device.

  FIG. 7 shows a wiring pattern 23 when the size of the product (semiconductor device) is about 12 mm × 12 mm, the pitch of external electrode terminals (pin pitch) is about 0.65 mm, and the number of external electrode terminals (number of pins) is 64 pins. Is shown. 8 and 9 show the wiring pattern 23 when the product size is about 10 mm × 10 mm, the pin pitch is about 0.50 mm, and the number of pins is 72 pins. The difference between FIG. 8 and FIG. 9 is that the wiring pattern 23 is deformed due to the difference in test items.

  Conventionally, a socket has to be prepared for each of a plurality of different BGA structure semiconductor devices having different external shapes, pin pitches, and arrangements of BGA structure semiconductor devices. However, as shown in this embodiment, even if the outer shape, pin pitch, and arrangement of the semiconductor device having the BGA structure are different, if the arrangement of the test pad 22 is made common, the position of the contact pin that contacts the test pad 22 can be changed. You can test with a common socket without changing it.

  Further, even in semiconductor devices having different test items, a test can be performed with a common socket simply by changing the wiring pattern 23 so that a voltage can be applied to the electrode terminals of the semiconductor chip necessary for the test item. .

  Next, the manufacturing process of the semiconductor device 1 shown in the present embodiment will be described with reference to FIGS. 10 to 18 are schematic cross-sectional views during the manufacturing process of the semiconductor device.

  First, an IC circuit, a semiconductor element constituting an LSI circuit, and the like are formed on the main surface of the semiconductor substrate, and a semiconductor chip 2 having a center pad structure electrode terminal 5 connected to the semiconductor element or the like is formed. prepare.

  FIG. 10 shows a schematic cross-sectional view when projecting electrode terminals (projection electrodes, bump electrodes) 5 are formed on the main surface of the semiconductor chip 2. As shown in the left diagram of FIG. 10, the tip of a wire 26 made of, for example, gold held by a capillary 25 is ultrasonically connected on the base electrode 5 a formed on the main surface of the semiconductor chip 2. That is, the tip of the wire 26 is spheroidized by discharge or the like, and the spheroidized portion is rubbed and connected to the base electrode 5a by pressure welding and ultrasonic vibration, and then the wire 26 is pulled and cut in the vicinity of the connection. Thereafter, as shown in the right diagram of FIG. 10, the connecting portion on the base electrode 5 a is suppressed and crushed by the piece 27 to form the protruding electrode, that is, the electrode terminal 5. The electrode terminal 5 includes a base electrode 5a.

  Next, as shown in FIG. 11, a substrate 4a composed of a TAB tape formed of a polyimide resin film having a thickness of about 50 μm is prepared. The substrate 4a is wound in a reel shape, but is unwound in each step.

  Subsequently, a copper foil having a thickness of about 35 μm is adhered to one surface or the other surface of the substrate 4a having the openings 9 to 12 with an adhesive having a thickness of about 12 μm, and then the copper foil is etched into a desired pattern. Then, the wiring pattern 23 including the leads 6 is formed. As shown in FIG. 5, the wiring pattern 23 is connected from the tip of the lead 6 to the external electrode terminal 3 (the lead 6 of the opening 9) and from the external electrode terminal 3 to the test pad 22. As described above, by forming the wiring pattern 23 corresponding to a product in which the size of each semiconductor device (product), the pitch and the arrangement of the external electrode terminals are different, a test socket is used in common during the test. be able to. In addition, before performing the bonding process mentioned later, the lead | read | reed 6 which protrudes in the opening part 10 is flat.

  Subsequently, an insulating protective film 8 is formed on the substrate 4a in a direction opposite to the direction in which the semiconductor chip is mounted from the opening 12 so as to sandwich the leads 6 with the substrate 4a.

  Subsequently, as shown in FIG. 12, after the substrate 4a wound in a reel shape is unwound and the semiconductor chip 2 is mounted on the substrate 4a, the tip of the lead 6 is connected to the electrode terminal 5 of the semiconductor chip 2 (inner lead). Bonding: ILB, bonding). That is, the substrate 4a including the lead 6 wound in a reel shape is unwound, the semiconductor chip 2 is positioned below the substrate 4a, and the connection tool is lowered from above the substrate 4a to connect the tip of the lead 6 to the electrode terminal. 5 and press to connect. Next, the substrate 4a on which the bonding has been performed is wound up on a winding reel.

  Subsequently, as shown in FIG. 13, the substrate 4a wound in a reel shape is unwound, and an insulating resin is dropped (potted) so as to cover the main surface of the semiconductor chip 2, and the applied resin is baked. Then, the sealing portion 13 is formed by curing. The resin dropped onto the substrate 4a spreads on the upper surface of the substrate 4a and falls from the opening 10 and the opening 11 and spreads on the main surface of the semiconductor chip 2. The resin spreading on the substrate 4a stops at the inner edge of the opening 12 due to the effect of surface tension. Since the connection part between the opening part 12 and the opening part 12 is short, it stops at the part corresponding to the inner periphery of the opening part 12 by the surface tension of resin. The resin that does not stop here also stops at a portion corresponding to the outer peripheral edge of the opening 12. The resin on the main surface of the semiconductor chip 2 also stops at a portion that extends from the outer peripheral edge of the semiconductor chip 2 to the inner peripheral edge of the opening 12 of the substrate 4a. The extent of such resin spread depends on the amount of application by the dispenser and the viscosity of the resin, and is therefore selected appropriately. Next, the substrate 4a on which the sealing portion 13 is formed is wound on a winding reel.

  Next, as shown in FIG. 14, the external electrode terminals 3 are formed on the substrate 4a unwound from the reel. In forming the external electrode terminal 3, the surface of the substrate 4a to be balled is faced upward, the ball is balled to form the external electrode terminal (bump electrode) 3, and then cleaning for removing flux or the like is performed. Next, the substrate 4a on which the external electrode terminals 3 are formed is wound up on a winding reel.

  Next, as shown in FIG. 15, the substrate 4 a wound in a reel shape is cut at a predetermined interval to form a semiconductor device precursor (piece) 1 a, and then the precursor 1 a is attached to the test socket 31. Then, a predetermined test is performed by bringing the contact pin 33 installed in the test device 32 into contact with the test pad 22. In FIG. 15, the contact pin 33 is installed in the test apparatus 32, but the test may be performed using the test apparatus 32 by arranging the contact pin 33 in the socket 31.

  Conventionally, the test is performed by directly contacting the external electrode terminal and the contact pin, and there is a risk of causing damage (damage) to the external electrode terminal. Particularly in the burn-in test, since the temperature is high, the damage becomes large, causing problems such as deformation of the terminal, and thus a defect of the external electrode terminal occurs. However, in the present embodiment, when the test is performed, since the terminal brought into contact with the contact pin 33 is not the external electrode terminal but the test pad 22, the test can be performed without damaging the external electrode terminal at all. it can.

  Conventionally, a socket has to be prepared for each of a plurality of different types of BGA semiconductor devices having different external shapes (sizes), pin pitches and arrangements of external electrode terminals. However, in the present embodiment, even if the arrangement of the openings 9 determined from the external shape (size) of the semiconductor device, the pitch of the external electrode terminals, and the arrangement differs depending on the type of the semiconductor device (product), the test pad By changing the wiring pattern 23 connected to the socket 22, the test can be performed using a common socket without changing the arrangement of the contact pins 33 of the socket. Further, by using a common socket, that is, by making the test environment of the BGA structure semiconductor device common, the manufacturing cost of the semiconductor device can be reduced.

  Subsequently, as shown in FIG. 16, a region (test region) including the test pad 22 is removed from the substrate 4a (the substrate 4a becomes the substrate 4 of the semiconductor device 1), and the semiconductor device 1 is formed (completed). . Since the test for the semiconductor device 1 is not performed by bringing the external electrode terminal and the contact pin into contact with each other as in the prior art, and is performed by bringing the test pad 22 and the contact pin 33 into contact with each other, the external electrode terminal is completely damaged. A test can be carried out without giving it, whereby the manufacturing yield of the semiconductor device 1 can be improved.

  Subsequently, the semiconductor device 1 is mounted on a mounting substrate 34 as shown in FIG. On the upper surface of the mounting substrate 34, lands 35 are provided corresponding to the external electrode terminals 3 of the semiconductor device 1. Further, the upper surface of the mounting substrate 34 where the land 35 is not provided is covered with an insulating film 36. Therefore, in order to mount the semiconductor device 1 on the mounting substrate 34, the semiconductor device 1 is placed on the surface of the land 35 in advance after the external electrode terminals 3 on the lower surface are placed on the lands 35 of the mounting substrate 34. The solder etc. that has been melted are remelted (reflowed) to electrically connect the external electrode terminal 3 to the land 35.

  Further, as shown in FIG. 18, the semiconductor device 1 may be structured to be stacked and connected in four stages. That is, after preparing the four semiconductor devices 1b to 1e, the semiconductor device 1c is mounted on the semiconductor device 1b. Next, the semiconductor device 1d is placed on the semiconductor device 1c. Next, the semiconductor device 1e is placed on the semiconductor 1d. During the stacking, the external electrode terminals 3 of the upper semiconductor device are positioned and stacked so as to overlap the leads 6 extending to the openings 9 of the lower semiconductor device. Thereafter, the lead 6 and the external electrode terminal 3 thereon can be electrically connected by reflow to manufacture a semiconductor device.

(Embodiment 2)
In this embodiment, an example in which the present invention is applied to a semiconductor device having a BGA (Ball Grid Array) structure using a glass epoxy copper clad laminate will be described. In the first embodiment, the TAB tape is used for the substrate. However, the present embodiment is different in that a glass epoxy copper clad laminate is used for the substrate. In the following, this difference will be mainly described.

  The structure of the semiconductor device 51 described in this embodiment will be described with reference to FIGS. 19 is a schematic plan view showing the semiconductor device 51, FIG. 20 is a schematic plan view in which the sealing portion 52 of the semiconductor device 51 in FIG. 19 is omitted, and FIG. 21 is a cross-sectional view of the semiconductor device 51 in FIG. FIG. 22 is a schematic sectional view, and FIG. 22 is a bottom view of the semiconductor device 51 of FIG.

  The semiconductor device 51 shown in the present embodiment includes a substrate 53 made of a glass epoxy copper clad laminate, a semiconductor chip 54 mounted on one surface (front surface) of the substrate 53, and the other surface (back surface) of the substrate 53. External electrode terminals 58 arranged and formed in a grid, electrode terminals 56 formed on the main surface of the semiconductor chip 54, electrode terminals 57 formed on the surface of the substrate 53, electrode terminals 56 and electrode terminals A bonding wire 55 that electrically connects the semiconductor chip 57 and a sealing portion 52 that covers the semiconductor chip 54 mounted on the surface of the substrate 53. Details will be described together with the precursors 51a, 51b, and 51c of the semiconductor device 51 shown below.

  First, the precursor 51a of the semiconductor device 51 will be described with reference to FIGS. 23 is a schematic plan view showing the precursor 51a of the semiconductor device 51, FIG. 24 is a schematic plan view in which the sealing portion 52 of the precursor 51a of the semiconductor device 51 shown in FIG. 23 is omitted, and FIG. 25 is shown in FIG. 26 is a schematic cross-sectional view of the precursor 51a of the semiconductor device 51, and FIG. 26 is a bottom view of the precursor 51a of the semiconductor device 51 shown in FIG.

  The precursor 51a includes a substrate 53a, a sealing portion 52 formed on one surface (front surface) of the substrate 53a, a test pad 59 disposed on the outer peripheral side of the surface of the substrate 53a, and the other surface of the substrate 53. The external electrode terminals 58 are arranged and formed in an array on the (rear surface). The semiconductor device 51 is formed by removing unnecessary regions (test regions) other than the product region 60 (regions surrounded by dotted lines in the drawing) from the precursor 51a, for example, by dicing.

  Further, the precursor 51a is a bonding wire 55 that electrically connects the semiconductor chip 54 mounted on the surface of the substrate 53a, the electrode terminal 56 formed on the semiconductor chip 54, and the electrode terminal 57 on the substrate 53a. Are sealed by the sealing portion 52.

  Although not shown, the electrode terminal 57 and the test pad 59 are electrically connected by wiring (wiring pattern). This wiring is formed on the front surface, the back surface of the substrate 53a, or in the substrate if the substrate 53a is a multilayer substrate. Note that when the back surface of the substrate 53a or the wiring formed in the substrate is connected to the electrode terminal 57, the connection is made through a through hole (not shown). Therefore, as long as the electrode terminal 56 and the test pad 59 are electrically connected, the wiring pattern may have any shape.

  Conventionally, the test is performed by directly contacting the external electrode terminal and the contact pin, and there is a risk of causing damage (damage) to the external electrode terminal. Particularly in the burn-in test, since the temperature is high, the damage becomes large, causing problems such as deformation of the terminals, and further defects in the external electrode terminals, which reduces the reliability of the semiconductor device. However, in this embodiment, when the test is performed, the terminal to be brought into contact with the contact pin is not the external electrode terminal 58 but the test pad 59. Therefore, the test can be performed without damaging the external electrode terminal 58 at all. Thus, the reliability of the semiconductor device can be improved.

  Next, a precursor 51b of the BGA structure semiconductor device 51 in which a plurality of test pads 59 are arranged on the outer peripheral portion of the surface (back surface) opposite to the front surface of the substrate 53a will be described with reference to FIGS. 27 is a schematic plan view showing the precursor 51b of the semiconductor device 51, FIG. 28 is a schematic sectional view of the precursor 51b of the semiconductor device 51 shown in FIG. 27, and FIG. 29 is a precursor of the semiconductor device 51 shown in FIG. It is a bottom view of 51b.

  This precursor 51b is different from the above-described precursor 51a in the arrangement of the test pad 59. Therefore, even in this case, since the terminal brought into contact with the contact pin is not the external electrode terminal 58 but the test pad 59 when performing the test, the test can be performed without damaging the external electrode terminal 58 at all. Thereby, the reliability of the semiconductor device can be improved.

  Next, a precursor 51c of the BGA structure semiconductor device 51 in which the entire surface of the substrate 53a is covered with a sealing portion and a plurality of test pads 59 are arranged on the outer peripheral portion of the back surface will be described with reference to FIGS. 30 is a schematic plan view showing the precursor 51c of the semiconductor device 51, FIG. 31 is a schematic sectional view of the precursor 51c of the semiconductor device 51 shown in FIG. 30, and FIG. 32 is a precursor of the semiconductor device 51 shown in FIG. It is a bottom view of 51c.

  This precursor 51c is different from the above-described precursor 51b in that the entire surface of the substrate 53a is covered with the sealing portion 52. Therefore, even in this case, since the terminal brought into contact with the contact pin is not the external electrode terminal 58 but the test pad 59 when performing the test, the test can be performed without damaging the external electrode terminal 58 at all. Thereby, the reliability of the semiconductor device can be improved.

  Next, a manufacturing process of the semiconductor device 51 described in this embodiment will be described with reference to FIGS. FIG. 33 is a schematic plan view of a substrate used as a precursor of the semiconductor device 51. 34 to 38 are schematic cross-sectional views of the semiconductor device 51 during the manufacturing process.

  As shown in FIG. 33, a substrate 53b is prepared so that a large number of semiconductor devices 51 can be taken. With this substrate 53b, 12 substrates 53a of the precursors (pieces) 51a of the semiconductor device 51, that is, 12 semiconductor devices 51 can be obtained. As shown in FIG. 33, a plurality of substrates 53a arranged in a matrix, dicing lines 61 separating the substrates 53a, and electrode terminals 57 formed on the substrate 53a (substrate 53b) are formed on the substrate 53b. Has been. Using this substrate 53b, for example, batch molding is performed in which resin molding is performed in a state where the plurality of substrates 53a are collectively covered.

  Subsequently, as shown in FIG. 34, the semiconductor chip 54 is mounted on the substrate 53b on which the wiring including the test pad 59 and the electrode terminal 57 is formed, and the electrode terminal 56 formed on the semiconductor chip 54 and the substrate The electrode terminal 57 formed on 53b is connected (bonded) with a bonding wire 55. The semiconductor chip 54 is mounted on the substrate 53b by applying an adhesive to the surface of the substrate 53b where the semiconductor chip 54 is mounted, and mounting and fixing the semiconductor chip 54 thereon.

  Subsequently, as shown in FIG. 35, molding is performed using a mold for transfer molding, the semiconductor chip 54 and the bonding wire 55 are sealed with a sealing resin, the mold resin is cured, and the sealing is performed. A part 52 is formed. As the mold resin, for example, an epoxy thermosetting resin is used.

  Subsequently, as shown in FIG. 36, external electrode terminals 58 are formed on the connection electrodes formed on the back surface of the substrate 53b. The external terminal electrode 58 is made of, for example, ball-shaped solder, the semiconductor chip 54 mounting surface of the substrate 53b is directed downward, and a ball mounting jig that holds the plurality of external electrode terminals 58 by vacuum suction is disposed above the external terminal electrode 58. It is formed by being mounted on connection electrodes (pads) in the product region from above the substrate 53b.

  Subsequently, as shown in FIG. 37, a test is performed on the precursor 51a of the semiconductor device 51 obtained by dividing the substrate 53b by dicing. When performing the test, first, the precursor 51 a is placed in the socket 62. The precursor 51a is attached to the test socket 62, and a predetermined test is performed by bringing the contact pin 63 installed in the test apparatus 64 into contact with the test pad 59. In FIG. 37, the contact pin 63 is installed in the test device 64, but the test may be performed using the test device 64 by arranging the contact pin 63 in the socket 62.

  Conventionally, the test is performed by directly contacting the external electrode terminal and the contact pin, and there is a risk of causing damage (damage) to the external electrode terminal. Particularly in the burn-in test, since the temperature is high, the damage becomes large, causing problems such as deformation of the terminal, and thus a defect of the external electrode terminal occurs. However, in the present embodiment, when the test is performed, the terminal brought into contact with the contact pin is not the external electrode terminal but the test pad, so that the test can be performed without damaging the external electrode terminal at all.

  Conventionally, a socket has to be prepared for each of a plurality of different types of BGA semiconductor devices having different external shapes (sizes), pin pitches and arrangements of external electrode terminals. However, in the present embodiment, even if the external shape (size) of the semiconductor device, the pitch and arrangement of the external electrode terminals vary depending on the type of the semiconductor device (product), the wiring pattern connected to the test pad is changed. Thus, a test can be performed using a common socket without changing the arrangement of the contact pins of the socket. Further, by using a common socket, that is, by making the test environment of the BGA structure semiconductor device common, the manufacturing cost of the semiconductor device can be reduced.

  Subsequently, as shown in FIG. 38, the product region portion is taken out from the precursor 51a by dicing, and the semiconductor device 51 is completed. As described above, the test for the semiconductor device 51 is not performed by bringing the external electrode terminal 58 and the contact pin 63 into contact with each other, but is performed by bringing the test pad 59 and the contact pin 63 into contact with each other. A test can be performed without damaging the semiconductor device, thereby improving the manufacturing yield of the semiconductor device.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above embodiment, the case where the present invention is applied to a semiconductor device having a BGA structure using a ball-shaped conductor as an external conductive terminal has been described. However, an LGA (Land Grid) using a land-shaped conductor as an external conductive terminal is described. The present invention can also be applied to a semiconductor device having an (Array) structure.

  The present invention is widely used in the manufacturing industry for manufacturing semiconductor devices.

1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention. It is the schematic plan view which abbreviate | omitted the sealing part of the semiconductor device of FIG. It is a schematic sectional drawing of the semiconductor device cut | disconnected by the XX line of FIG. FIG. 2 is a schematic bottom view of the semiconductor device of FIG. 1. FIG. 3 is a schematic plan view of a substrate used as a semiconductor device precursor in the first embodiment. FIG. 6 is a schematic plan view showing an arrangement of test pads formed on the substrate of FIG. 5. It is the schematic plan view which showed an example of the wiring pattern on the board | substrate of FIG. It is the schematic plan view which showed an example of the wiring pattern on the board | substrate of FIG. It is the schematic plan view which showed an example of the wiring pattern on the board | substrate of FIG. It is a schematic sectional drawing in the manufacturing process of the semiconductor device in Embodiment 1 of this invention. FIG. 11 is a schematic cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 10; FIG. 12 is a schematic cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is a schematic cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; FIG. 14 is a schematic cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 13; FIG. 15 is a schematic cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 14; FIG. 16 is a schematic cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15; FIG. 17 is a schematic cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 16; FIG. 17 is a schematic cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 16; It is a schematic plan view of the semiconductor device in Embodiment 2 of this invention. FIG. 20 is a schematic plan view in which a sealing portion of the semiconductor device of FIG. 19 is omitted. It is a schematic sectional drawing of the semiconductor device cut | disconnected by the XX line of FIG. FIG. 20 is a schematic bottom view of the semiconductor device of FIG. 19. It is a schematic plan view which shows an example of the precursor of the semiconductor device in Embodiment 2 of this invention. FIG. 24 is a schematic plan view in which a sealing portion of a precursor of the semiconductor device shown in FIG. 23 is omitted. It is a schematic sectional drawing of the precursor of the semiconductor device shown in FIG. FIG. 24 is a schematic bottom view of the precursor of the semiconductor device shown in FIG. 23. 5 is a schematic plan view showing an example of a precursor of a semiconductor device in a second embodiment. FIG. It is a schematic sectional drawing of the precursor of the semiconductor device of FIG. It is a schematic bottom view of the precursor of the semiconductor device of FIG. 5 is a schematic plan view showing an example of a precursor of a semiconductor device in a second embodiment. FIG. FIG. 31 is a schematic cross-sectional view of a precursor of the semiconductor device of FIG. 30. FIG. 31 is a schematic bottom view of a precursor of the semiconductor device of FIG. 30. It is a schematic plan view of the board | substrate used for the precursor of the semiconductor device in this Embodiment 2. FIG. It is a schematic sectional drawing in the manufacturing process of the semiconductor device in this Embodiment 2. FIG. 35 is a schematic cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 34; FIG. 36 is a schematic cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 35; FIG. 37 is a schematic cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 36; FIG. 38 is a schematic cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 37;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 1a Precursor 1b, 1c, 1d, 1e Semiconductor device 2 Semiconductor chip 3 External electrode terminal 4, 4a Substrate 5 Electrode terminal 5a Pad (base electrode)
6 Inner lead (lead)
DESCRIPTION OF SYMBOLS 8 Protective film 9, 10, 11, 12 Opening part 13 Sealing part 14 Connection part 20 Opening part 21 Product area 22 Test pad 23 Wiring pattern 24 Sprocket hole 25 Capillary 26 Wire 27 Holding piece 31 Socket 32 Test apparatus 33 Contact pin 34 Mounting substrate 35 Land 36 Insulating film 51 Semiconductor device 51a, 51b, 51c Precursor 52 Sealing portion 53, 53a, 53b Substrate 54 Semiconductor chip 55 Bonding wire 56 Electrode terminal 57 Electrode terminal 58 External electrode terminal 59 Test pad 60 Product region 61 Dicing line 62 Socket 63 Contact pin 64 Test equipment

Claims (5)

(A) preparing a semiconductor chip having a plurality of electrode terminals on the main surface;
(B) preparing a substrate comprising a plurality of test pads formed in a region outside the region on which the semiconductor chip is mounted, and wirings for electrically connecting the electrode terminals and the test pads;
(C) applying a voltage to the semiconductor chip through the plurality of test pads. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
(D) A method for manufacturing a semiconductor device, further comprising a step of removing the plurality of test pads from the substrate after the step (c). (A1) preparing a first semiconductor chip having a plurality of first electrode terminals on the main surface;
(B1) a plurality of first test pads formed in a region outside the region on which the first semiconductor chip is mounted, a first wiring that electrically connects the first electrode terminal and the first test pad; Preparing a first substrate comprising:
(C1) applying a voltage to the first semiconductor chip via the first test pad;
(A2) preparing a second semiconductor chip having a plurality of second electrode terminals on the main surface;
(B2) a plurality of second test pads formed in a region outside the region on which the second semiconductor chip is mounted and having the same arrangement as the plurality of first test pads; the second electrode terminal; and the second test. Preparing a second substrate comprising: a second wiring that electrically connects the pad;
(C2) applying a voltage to the second semiconductor chip through the second test pad. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 3,
(D1) After the step (c1), removing the plurality of first test pads from the first substrate;
(D2) The method of manufacturing a semiconductor device, further comprising a step of removing the plurality of second test pads from the second substrate after the step (c2). In the manufacturing method of the semiconductor device according to any one of claims 1 to 4,
The method for manufacturing a semiconductor device, wherein the substrate is a polyimide tape or a glass epoxy copper clad laminate.

Images