JPH03115812A - Load-cell type scale - Google Patents

Abstract

PURPOSE:To prevent deterioration in a common-mode rejection ratio by a method wherein a synthesized resistance value of specific resistors of a reference voltage setting circuit and a first gain setting circuit is made equal to the resistance value of a specific resistor of a second gain setting circuit. CONSTITUTION:A synthesized resistance value of a resistance value of a reference voltage setting circuit 12 and a resistance value of a resistor R1 to be directly connected to the circuit 12 among first gain setting resistors 16 is assumed to be rx. A resistance value of a resistor R4 to be connected to an output of a two-stage operational amplifier 15 among second gain setting resistors 17 is assumed to be r4. The resistance value rx and the resistance value r4 are set equal. A common-mode rejection ratio of a circuit is determined by a ratio of a common mode gain A and a differential gain B, while since the resistors 17 are not connected to the circuit 12, the ratio is determined by the gain A. Therefore by making the resistance values rx and r4 equal, the gain A is zero so that the common-mode rejection ratio approaches zero, preventing deterioration.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a load cell scale that amplifies an electrical signal from a load cell via a signal amplifier to which a reference voltage is applied from a reference voltage setting circuit.

[Prior Art] Conventionally, as this type of load cell type scale, one shown in FIG. 2 is known. The load cell 1 is connected to an 18V DC power source, and a reference voltage setting circuit 2 formed by connecting a resistor R5 and a resistor R6 in series is connected. The load cell 1 outputs an electric signal between a and b in response to a load, and supplies the electric signal to a signal amplification circuit 3. The signal amplification circuit 3 includes a first-stage operational amplifier 4 and a second-stage operational amplifier 5, and a non-inverting output terminal (+
), the voltage at point a of load cell 1 is input to the non-inverting output terminal (+) of the two-stage operational amplifier 5.
Point voltage is being input. The first stage operational amplifier 4 is provided with a gain setting resistor group 6 formed by connecting a resistor R1 and a resistor R2 in series, and the connection point between the resistors R1 and R2 is the inverting input terminal of the first stage operational amplifier 4. (-), and the other end of the resistor R2 is connected to the output terminal of the first stage operational amplifier 4. The other end of the resistor R1 is connected to the output terminal of a buffer 8 composed of an operational amplifier. The input terminal of this buffer 8 is connected to the resistor R in the base voltage setting circuit 2.
5 and the connection point between resistor R6.

Further, the two-stage operational amplifier 5 is provided with a gain setting resistor group 7 formed by connecting a resistor R3 and a resistor R4 in series, and the connection point between the resistor R3 and the resistor R4 is connected to the two-stage operational amplifier 5. The resistor R4 is connected to the inverting input terminal (-), and the other end of the resistor R4 is connected to the output terminal of the two-stage operational amplifier 5. Resistance R
The other end of 3 is connected to the output terminal of the first stage operational amplifier 4.

The signal amplifying circuit 3 outputs an amplified electrical signal from the output terminal of its two-stage operational amplifier 5, and supplies it to an A/D (analog/digital) converter 9. This A/D converter 9 converts the input electrical signal into a digital signal and outputs the digital signal.

In such an amplifier circuit, the voltage from the DC power supply is divided by the resistors R5 and R6 of the reference voltage setting circuit 2 to generate a reference voltage, and this reference voltage is used as the zero point of the scale to be sent to the signal amplifier via the buffer 8. 3.

Here, in the buffer 8, the dividing resistors R5 and R6 of the reference voltage setting circuit 2 are connected to the gain setting resistors R1 to R6 of the signal amplifier 3.
It is combined with R4 to prevent the common mode rejection ratio (CMRR) of the circuit from deteriorating.

[Problems to be Solved by the Invention] However, in this conventional load cell type scale, the buffer 8 consisting of an operational amplifier is used to prevent the common-mode component rejection ratio of the circuit from deteriorating. There was a problem in that as the number of points increased, the cost also increased.

Furthermore, there was also the problem that the zero point of the scale was likely to fluctuate due to the drift of the buffer 8.

Therefore, the present invention can prevent the common mode rejection ratio of the circuit from deteriorating without using a buffer, reduce the number of parts used, reduce costs, and reduce the zero point of the scale. The purpose is to provide a load cell type scale that can be stably obtained.

[Means for Solving the Problems] The present invention includes a load cell that outputs an electric signal corresponding to a load, a reference voltage setting circuit that outputs a reference voltage, and one electric signal from the load cell is directly inputted, and the reference voltage setting circuit outputs a reference voltage. The reference voltage from the voltage setting circuit is inputted via the first gain setting resistor group to the first stage operational amplifier, and the other electric signal from the load cell is directly inputted, and the output voltage of the first stage operational amplifier is inputted via the first gain setting resistor group. A signal amplification circuit that has a two-stage operational amplifier that is input via a group of setting resistors and amplifies the electrical signal from the load cell, and an A/D that converts the electrical signal output from this signal amplification circuit into a digital signal. In a load cell type scale comprising a conversion section, the combined resistance value of the resistance value of the reference voltage setting circuit and the resistance value of the resistor directly connected to the reference voltage setting circuit in the first gain setting resistor group is 2 in the gain setting resistor group
It is made equal to the resistance value of the resistor connected to the output side of the stage operational amplifier.

[Function] In the present invention having such a configuration, the combined resistance value of the resistance value of the reference voltage setting circuit and the resistance value of the resistor directly connected to the reference voltage setting circuit in the first gain setting resistor group is calculated as follows. When Rx is Rx and the resistance value of the remaining resistors in the first gain setting resistor group is Ra, the gain G1 of the first stage operational amplifier is expressed by the following equation (1).

G1-Ra/Rx =il) Also,
When the resistance value of the resistor connected to the output side of the two-stage operational amplifier in the second gain setting resistor group is Rb, and the resistance value of the remaining resistor in the second gain setting resistor group is Rc, 2 The gain G2 of the stage operational amplifier is expressed by the following equation (2).

G2=Rb/Re (2) Therefore, the common mode gain A of the circuit is expressed by the following equation (3), and the differential gain B is expressed by the following equation (4).

A-1-01・G2...(3)B-
1+02...(4) Here, the resistance value R of the remaining resistors in the first gain setting resistor group
When a and the resistance value Rc of the remaining resistors in the second gain setting resistor group are defined to be equal, the common mode gain A shown by the above equation (3) is expressed by the following equation (5).

A-1-Rb/Rx-(5) On the other hand,
The common mode rejection ratio (CMRR) of the circuit is determined by the ratio of the common mode gain A to the differential gain B. However, the differential gain B is (4
) As is clear from the equation, it is determined by the resistance values Rb and Rc in the second gain setting resistor group, and these resistance values Rb and Rc are determined by the resistance values Rb and Rc when the second gain setting resistor group is connected to the reference voltage setting circuit. Therefore, it is not affected by this circuit.

Therefore, it is the common-mode gain A that influences the common-mode component rejection ratio, which depends on the resistance value Rx according to the above equation (5). That is, the common-mode component rejection ratio changes depending on the combined resistance value Rx of the resistance value of the reference voltage setting circuit and the resistance value of the resistors directly connected to the reference voltage setting circuit in the first gain setting resistor group. In other words, by setting RxmRb, the common-mode component removal ratio approaches "0",
Deterioration of the common-mode component removal ratio is prevented.

[Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

As shown in Figure 1, load cell 1 is connected to 18V DC power supply.
1 and a reference voltage setting circuit 12 formed by connecting a resistor R5 and a resistor R6 in series. The load cell 11 outputs an electric signal between a and b in response to a load, and supplies the electric signal to a signal amplification circuit 13. The signal amplification circuit 13 has a first-stage operational amplifier 14 and a two-stage operational amplifier 15 , and inputs the point a voltage of the load cell 11 to the non-inverting output terminal (+) of the first-stage operational amplifier 14 . The voltage at point b of the load cell 11 is input to the non-inverting output terminal (+). The first stage operational amplifier 14 is provided with a first gain setting resistor group 16 formed by connecting a resistor R1 and a resistor R2 in series, and the connection point between the resistors R1 and R2 is connected to the first stage operational amplifier 14.
The other end of the resistor R2 is connected to the output terminal of the first stage operational amplifier 14. Resistance R
The other end of 1 is the resistor R5 in the reference voltage setting circuit 12.
and the connection point between the resistor R6 and the resistor R6.

Further, the two-stage operational amplifier 15 is provided with a second gain setting resistor group 17 formed by connecting a resistor R3 and a resistor R4 in series, and the connection point between the resistor R3 and the resistor R4 is connected to the two-stage operational amplifier 15. The resistor R4 is connected to the inverting input terminal (=) of the amplifier 15, and the other end of the resistor R4 is connected to the output terminal of the two-stage operational amplifier 15. The other end of the resistor R3 is connected to the output terminal of the first stage operational amplifier 14.

The signal amplification circuit 13 outputs an amplified electrical signal from the output terminal of its two-stage operational amplifier 15, and supplies it to an A/D (analog/digital) converter 18. This A/
The D converter 18 converts the input electrical signal into a digital signal and outputs the digital signal.

Then, the resistance value of the reference voltage setting circuit 12 and the first
The combined resistance value of the resistance value of the resistor R1 directly connected to the reference voltage setting circuit 12 in the gain setting resistor group 16 is calculated as the output of the two-stage operational amplifier 15 in the second gain setting resistor group 17. The resistance value is set equal to the resistance value of the resistor R4 connected to the side.

In this embodiment having such a configuration, the resistance value of the resistor R5 of the reference voltage setting circuit 12 is r5, the resistance value of the resistor R6 is r6, and the resistance value of the resistor R1 in the first gain setting resistor group 16 is When set to 1, reference voltage setting circuit 1
The combined resistance value "X" of the resistance value of R2 and the resistance value of the resistor R1 in the first gain setting resistor group 16 is expressed by the following equation (6).

rx-rl+r5・r6/(r5+r6) −(6)
Therefore, when the resistance value of the resistor R2 in the first gain setting resistor group 16 is set to r2, the gain G1 of the first stage operational amplifier 14 is expressed by the following equation (7).

Gl-r2/rx = 47) Also,
When the resistance value of the resistor R4 in the second gain setting resistor group 17 is r4, and the resistance value of the resistor R3 in the second gain setting resistor group 17 is r3, the two-stage operational amplifier 1
The gain G2 of 5 is expressed by the following equation (8).

G2-r4/r3 = 18) Therefore, the common mode gain A of the circuit is expressed by the following equation (9), and the differential gain B is expressed by the following equation (10).

A-1-Gl・G2...(9)B
−1+02 −(10) where,
When the resistance value r2 of the resistor R2 in the first gain setting resistor group 16 and the resistance value r3 of the resistor R3 in the second gain setting resistor group 17 are defined as being equal, the above (9
) is expressed by the following equation (11).

A-1-r4/rx=ill
) On the other hand, the common mode component rejection ratio (CMRR) of the circuit is determined by the ratio of the common mode gain A to the differential gain B (A/B). However, as is clear from equation (1o) above, the differential gain B is
The resistance value r3. of the resistor R3 and the resistor R4 in the gain setting resistor group 17. r4, and this resistance value r3. Since the second gain setting resistor group 17 is not connected to the reference voltage setting circuit 12, r4 is not affected by this circuit 12. Therefore, it is the common-mode gain A that influences the common-mode component rejection ratio, which depends on the resistance value "X" according to the above equation (II).

That is, the resistance value of the reference voltage setting circuit 12 [r5・r6
/(r5+r6)] and the resistance value "1" of the resistor R1 directly connected to the reference voltage setting circuit 12 in the first gain setting resistor group 16. The common-mode component rejection ratio changes depending on the combined resistance value rx.

Here, in this embodiment, the combined resistance value rx is transferred to the two-stage operational amplifier 15 in the second gain setting resistor group 17.
Since the resistance value r4 is made equal to the resistance value r4 of the resistor R4 connected to the output side of the resistor R4, the common mode gain A becomes approximately "0", as is clear from the above equation (11).

Therefore, the common-mode component removal ratio approaches "0",
Deterioration of the common-mode component removal ratio is prevented. Therefore, the ability to remove the common mode component can be maintained at a high level against changes in the output of the load cell 11 due to fluctuations in the power supply voltage.

In this way, according to this embodiment, the deterioration of the common-mode component rejection ratio of the circuit can be prevented without using the buffer 8 made of a conventional operational amplifier, and with a simple configuration that only requires setting the resistance value to a predetermined value. Therefore, the number of parts used can be reduced and costs can be reduced. Furthermore, since fluctuations in the reference voltage due to drift of the buffer 8 are eliminated, the zero point of the scale can be stably obtained.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to easily prevent the common mode rejection ratio of the circuit from deteriorating without using a buffer, and the number of parts used can be reduced. At the same time, it is possible to provide a load cell scale that can reduce costs and stably obtain the zero point of the scale.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional example. 11... Load cell, 12... Reference voltage setting circuit,
13... Signal amplification circuit, 14... First stage operational amplifier,
15... Two-stage operational amplifier, 16.17... First. Second gain setting resistor group, 18...A/D conversion section.

Claims (1)

[Scope of Claims] A load cell that outputs an electric signal corresponding to a load, a reference voltage setting circuit that outputs a reference voltage, and one electric signal from the load cell is directly inputted, and the electric signal from the reference voltage setting circuit is inputted directly. A first-stage operational amplifier to which a reference voltage is input via a first gain-setting resistor group and the other electric signal from the load cell is directly input, and an output voltage of the first-stage operational amplifier is input to a second gain-setting resistor. a signal amplification circuit that includes a two-stage operational amplifier that is inputted via the load cell, and that amplifies the electrical signal from the load cell; and an A/D conversion section that converts the electrical signal output from the signal amplification circuit into a digital signal. In the load cell type scale, the combined resistance value of the resistance value of the reference voltage setting circuit and the resistance value of the resistor directly connected to the reference voltage setting circuit in the first gain setting resistor group is determined by the resistance value of the resistance value of the reference voltage setting circuit. A load cell type weigher, characterized in that the resistance value is equal to the resistance value of the resistor connected to the output side of the two-stage operational amplifier in the second gain setting resistor group.