JPH0418481B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a differential amplifier circuit, and more particularly to a differential amplifier circuit having a differential single-ended conversion circuit.

[Conventional technology]

Conventionally, to amplify bridge outputs such as strain gauges and thermistors, instrumentation amplifiers (for example, BURR BROWN
Company INA101) is used. That is, the (+) input terminal of the operational amplifier 11 is connected to the input terminal 1. A resistor 13 and a resistor 22 are connected to the output terminal of the operational amplifier 11. The other end of this resistor 13 is connected to the (-) input terminal of the operational amplifier 11 and a resistor 14 . This resistance 1
The other end of 4 is connected to the (-) input terminal of the operational amplifier 12 and a resistor 15. The other end of this resistor 15 is connected to the output terminal of the operational amplifier 12 and a resistor 23 . Also, the (+) of operational amplifier 12
The input terminal is connected to input terminal 2.

These operational amplifiers 11, 12 and resistors 13, 14,
15 constitutes an amplifier circuit 10. This amplifier circuit has a function of amplifying the values input from the input terminals 1 and 2 to a predetermined value and outputting the amplified value.

Further, the resistor 24 and the (-) input terminal of the operational amplifier 21 are connected to the other end of the resistor 22 . The output terminal of the operational amplifier 21 is connected to the other end of the resistor 24 . The output terminal 3 is connected to the output terminal of this operational amplifier 21, and the other end of the resistor 23 and the resistor 25 are connected to the (+) input terminal. The other end of this resistor 25 is grounded.

The differential single-end conversion circuit 2
0 is configured.

With this configuration, in the amplifier circuit 10, the differential voltage between the input terminals 1 and 2 is amplified to a predetermined value by the operational amplifiers 11, 12 and the resistors 13, 14, 15, and output. This output signal is converted into a differential single-end conversion circuit 20 consisting of an operational amplifier 21 and resistors 22, 23, 24, and 25.
The signal is converted into a single-ended signal and output to the output terminal 3 and the ground terminal 4.

[Problem to be solved by the invention]

The input/output characteristics of the conventional circuit shown in Figure 1 are V ₀ = (1 + R ₁₃ + R ₁₅ /R ₁₄ )・(R ₂₄ /R ₂₂ −
8/1+ _R22 / _R24 )・Vd−(δ/1+ _R22 / _R24 )・Vc…
…(1) Here, δ is the resistance ratio error of the differential single-end conversion circuit 20, and is expressed as δ=R ₂₅ /R ₂₃ /R ₂₄ /R ₂₂ −1 (2). Further, Vd is the difference voltage between input terminals 2 and 1, Vc is the average voltage between input terminals 1 and 2, and V ₀ is the voltage at output terminal 3.

Therefore, the amplification gain of the conventional circuit shown in FIG. 1 is the first term on the right side of equation (1), and the common mode rejection ratio (CMRR) is expressed as the second term on the right side. now,
For example, when R ₂₄ /R ₂₂ = 1, the change in gain is
To make it 0.1% or less, δ should be 0.2% or less. Also, when the coefficient of Vd in equation (1) above is 1, that is, the gain is 1, δ that makes the CMRR 80 dB or more is
Must have high accuracy of 0.02% or less.

Therefore, conventional circuits (e.g.
In BURRBROWN's INA101), a large number of precision resistors must be used, such as thin film resistors that are precisely adjusted by laser trimming, making it difficult to improve accuracy and reduce costs. It has some drawbacks.

An object of the present invention is to provide a differential amplifier circuit that can simplify adjustment of resistance accuracy and improve accuracy.

[Means to solve the problem]

In order to achieve the above object, the present invention has a pair of operational amplifiers 11 and 12 and two input terminals 1 and 2.
an amplifier circuit 10 that amplifies the voltage input from the operational amplifier 10 and outputs a differential voltage; and two switch elements 32, 33, 34, respectively at the output terminal of the operational amplifier 10.
A differential single-ended conversion circuit 30 is formed by connecting 35 series connected bodies and connecting the common connection point of the two switches via a first capacitor 31, the input terminals 1 and 2, the operational amplifier 11, two switch elements 5 each inserted between 12 and 12;
1, 52, and switch elements 53, 54/5, which are connected to enable short circuit between the input terminals 11, 12.
5, 57, /56, 58, a series connection body of the second capacitor 62 and the switch element 64 connected to one output end of the differential single-ended conversion circuit 30, and a common connection point of the series connection body. and the other output terminal 3 of the differential single-ended conversion circuit 30 are connected so as to be short-circuitable.
and control terminals 71, 72, 73, 74, 75, which input on/off control signals for each of the switch elements.
76.

[Effect]

With this configuration, according to the present invention, the above object is achieved through the following actions.

First, by turning on the two switch elements inserted between the two input terminals and the first and second operational amplifiers, differential amplified outputs of the two input voltages are output from the first and second operational amplifiers. . At this time, by turning on the two switch elements on the input side of the differential single-end conversion circuit, the first capacitor is charged to a voltage corresponding to the differential amplification output. Next, by turning on the two switch elements on the output side of the differential single-ended conversion circuit, the voltage of the first capacitor can be taken out as a differential amplified output. As described above, since the differential single-ended conversion circuit of the present invention can be constructed without using a resistor, the resistance ratio error corresponding thereto can be eliminated. As a result, adjustment of resistance accuracy is simplified and amplification accuracy can be improved.

By the way, the differential amplification output mentioned above includes the offset error of the first and second operational amplifiers,
According to the present invention, the offset voltage can be corrected by the following action. That is, prior to the above action, a switch element that shorts the input terminals of the first and second operational amplifiers, all switch elements of the differential single-ended conversion circuit, and the other output of the differential single-ended conversion circuit are connected. A switch element that short-circuits the end and the terminal of the second capacitor is turned on. As a result, the output of the amplifier circuit becomes a voltage corresponding to the offset of the operational amplifier, which is charged to the second capacitor. From this state,
When each switch element except the one on the input side of the differential single-ended conversion circuit is turned off, and the switch element between the input terminal and the operational amplifier is turned on, the differential amplified output of the input voltage becomes the first one. The capacitor is charged. Next, the input side switch element of the differential single-ended conversion circuit is turned off, the output side switch element is turned on, and the switch element connected to the output terminal of the second capacitor is turned on, so that the output side of this switch element is turned on. and,
The output voltage between the other output terminals of the differential single-ended conversion circuit is the difference between the voltage of the first capacitor and the voltage of the second capacitor. As a result, a highly accurate differential amplification output from which the offset voltage of the operational amplifier has been removed can be obtained.

〔Example〕

Examples of the present invention will be described below.

First, FIG. 2 shows an example of a differential amplifier circuit according to the main part of the present invention.

In the figure, an amplifier circuit 10 has the same configuration as the conventional example shown in FIG. 1, but its amplification factor is
It has an amplification factor that is the sum of the amplification factor of the conventional amplifier circuit 10 shown in FIG. 1 and the amplification factor of the differential single-end conversion circuit 20. FIG. 2 Illustrated amplifier circuit 10
A MOS transistor switch 32 is connected to the output terminal of the operational amplifier 11.
The transistor switch 32 includes a capacitor 31
and a MOS transistor switch 31 are connected. The other end of this MOS transistor switch 34 is connected to the output terminal 3. Furthermore, a MOS transistor switch 33 and a MOS transistor switch 35 are connected to the other end of the capacitor 31. The other end of the MOS transistor switch 35 is grounded, and the other end of the MOS transistor switch 33 is connected to the output terminal of the operational amplifier 12 of the amplifier circuit 10. this
A control terminal 41 is connected to the gates of the MOS transistor switch 32 and the MOS transistor switch 33.
However, the control terminal 4 is connected to the gates of the MOS transistor switch 34 and the MOS transistor switch 35.
2 are connected to each other. The MOS transistor switches 32, 33, 34, 35 and the capacitor 31 form a differential single-end conversion circuit 3.
0 is configured, and is connected to a so-called flying capacitor circuit. In addition, control terminal 4
1 and 42 are driven by pulse signals that do not overlap with each other as shown in FIGS. 3A and 3B.

Since it is configured like this, first of all,
At time t1 shown in FIG. ₃ , the MOS transistor switches 32 and 33 are ON and the MOS transistor switches 34 and 35 are OFF, so the output that amplifies the differential voltage input to the amplifier circuit 20 charges the capacitor 31. be done. Next, at time t ₂ in FIG. 3, MOS transistor switches 32 and 33 are turned on.
Since it is OFF and the MOS transistor switches 34 and 35 are ON, the voltage charged in the capacitor 31 at time _t1 in FIG. 3 is output to the ground terminal 4 and the output terminal 3. Since there is no discharge loop at this time, the voltage charged in the capacitor 31 at time t1 in FIG. ₃ is output as is.

Therefore, the voltage V ₀ at the output terminal 3 at time t ₂ in FIG. 3 is as follows: V ₀ =(1+R ₁₃ +R ₁₅ /R ₁₄ )·Vd (3). Here, Vd is the differential voltage between input terminals 1 and 2.

Therefore, according to the example shown in FIG. 2, the relationship between the input differential voltage and the output voltage does not depend on the average voltage Vc of the input terminals 1 and 2 as shown in equation (3) above, so that its accuracy is improved.

In addition, according to the example in Figure 2, only three expensive resistors that require precision and stability are needed, making it possible to reduce costs compared to conventional circuits, as well as reduce the resistance load and reduce power consumption. can be achieved.

Furthermore, according to the example in FIG. 2, since the output is sampled and held, it is easy to interface with an A/D converter.

FIG. 4 shows a differential amplifier circuit according to an embodiment of the present invention, the main part of which is shown in FIG.

In this embodiment, the amplifier circuit 10 and the differential single-end conversion circuit 30 have the same configuration as the circuit shown in FIG. In this embodiment, it is determined whether the input of the amplifier circuit 10 is the voltage of input terminals 1 and 2 or zero.
MOS transistor switch 51, 52, 53,
54 and a capacitor 62,
A configuration for correcting the offset voltages of operational amplifiers 11, 12, and 61 is connected to MOS transistor switches 63 and 64, and is also connected to output terminal 3 via an operational amplifier 61 having a buffer configuration.

Each MOS transistor switch 51, 52, 5
3, 54, 32, 33, 34, 35, 63, 64
Control terminals 71, 72, 73, 74, 75, 76
is driven by a signal as shown in FIG. 5A shows the control terminal 71, and FIG. 5B shows the control terminal 7.
2, FIG. 5C is the control terminal 73, FIG. 5D is the control terminal 74, and FIG. 5E is the control terminal 75.
FIG. F shows the respective signal waveforms of the control terminal 76. First, at time t ₁ in FIG. 5, the MOS transistor switches 32, 33, 34, 35, 53,
54 and 63 are on and the others are off, the differential input voltage of the amplifier circuit 10 becomes zero, and the sum of the offset voltage difference between the operational amplifiers 11 and 12 and the offset voltage of the operational amplifier 61 is the sum of the offset voltage of the operational amplifier 61.
It is charged to 2. This charging voltage V ₆₂ becomes V ₆₂ = (1+R ₁₃ + R ₁₅ /R ₁₄ ) (Vos ₂ −Vos ₁ )−Vos ₃ (4). Here, Vos ₁ , Vos ₂ and Vos ₃ are offset voltages of operational amplifiers 11, 12 and 61, respectively.

Next, at time _t2 in FIG. 6, MOS transistor switches 32, 33, 51, and 52 are turned on and the others are off, so the operation is the same as at time _t1 in FIG. Amplify the differential voltage Vd of
Charge the capacitor 31. This charge amount V ₃₁ is calculated as follows when considering the effect of offset voltage of the operational amplifiers 11 and 12: V ₃₁ = (1 + R ₁₃ + R ₁₅ /R ₁₄ ) (Vd + Vos ₂ - Vos ₁ ) (5).

Next, at time _t3 in FIG. 5, MOS transistor switches 34, 35, and 64 are on, and the others are off, so capacitor 31 and capacitor 62 are turned on.
The charging voltage difference becomes the input of the operational amplifier 61, and the voltage V ₀ of the output terminal 3 is as follows: V ₀ = V ₃₁ −V ₆₂ −Vos ₃ =(1+R ₁₃ +R ₁₅ /R ₁₄ )・Vd ……(6) . Therefore, operational amplifiers 11, 12, 6
1 offset voltage can be corrected. Further, since the offset correction is performed with the common mode sampling terminal 5 and the input terminal 1 connected and bias applied, the common mode rejection ratio (CMRR) characteristic of the amplifier circuit 10 is also corrected at the same time.

Therefore, according to this embodiment, the offset voltage of the operational amplifier can be corrected and the CMRR characteristic can be corrected, so that the accuracy is further improved.

Furthermore, according to this embodiment, since the input of the amplifier circuit 10 is shot when correcting the offset voltage,
When a multiplexer is provided at the input and multiple channels of input are switched, crosstalk between channels can be reduced.

Note that the function of the operational amplifier 61 is the output terminal 3,
This was inserted in order to prevent the differential single-end conversion circuit 30 from being affected by the load circuit connected to the differential single-end conversion circuit 30. Therefore, depending on the characteristics of the load circuit, the operational amplifier 61 can be omitted.

Another embodiment of the invention is shown in FIG.

In this embodiment, the amplifier circuit 10 and the differential single-end conversion circuit 30 are the same as the circuit shown in FIG.
64 and the configuration of the capacitor 62 and the operational amplifier 61
The configuration is the same as that shown in FIG. The difference from FIGS. 2 and 4 is that the input of the amplifier circuit 10 is connected to the input terminal 1,
2, swap input terminals 1 and 2, or set them to zero using MOS transistor switches 55 and 5.
6, 57, 58 and OR gates 59, 60 and the polarity of the difference voltage between the input terminals 1 and 2 are compared, and the MOS transistor switches 55, 5
6, 57, and 58 are provided.

Control terminal 81 of each MOS transistor switch,
82, 83, 73, 74, 75, 76, and 77 are driven by each signal shown in FIG. 7A to I.

Further, the comparator 90 consists of MOS transistor switches 92, 93, 80, a capacitor 91, and an inverting amplifier 95, and the control terminals 78, 79, 80 of each MOS transistor switch are connected to the terminals 78, 8A, and 80 of FIG.
It is driven by the B and C signals.

Next, the operation of this embodiment will be explained. First, at time t ₁ in FIG. 7, the MOS transistor switches 55, 57, 32, 33, 34, 35, 63
is on and the others are off. This configuration is the same as that at time _t1 in FIG. 5 in the embodiment shown in FIG. Therefore, the voltage V ₆₂ charged to the capacitor 62 is expressed by equation (4) above. Also,
The charging voltage V ₃₁ of the capacitor 31 at this time t ₁ is equal to the output of the amplifier circuit 10, and V ₃₁ = (1+R ₁₃ + R ₁₅ /R ₁₄ ) (Vos ₂ −Vos ₁ ) (7).

Next, at time _t2 in FIG. 7, MOS transistor switches 55, 56, and 36 are turned on, and the others are turned off. Therefore, input terminals 1 and 2 are connected to (+) input terminals of operational amplifiers 11 and 12, respectively. Differential output of amplifier circuit 10 at this time
In the embodiment shown in FIG. 4, V _dp is equal to the above equation (5), which is the voltage of the capacitor _{31 at time t 2 in} FIG. ₁ ) ...(8) becomes.

Further, one output terminal of the amplifier circuit 10 and one terminal of the capacitor 31 are connected by the MOS transistor switch 36. Furthermore, a comparator 90 compares the voltages at the other output terminal of the amplifier circuit 10 and the other terminal of the capacitor 31 . As a result, the signal POL at the output point 84 of the comparator 90 is as shown in (8) above.
Since it is determined by the difference between the output Vdo of the amplifier circuit 10 shown by the equation and the charging voltage V ₃₁ of the capacitor 31 shown by the above equation (7), it can be shown by the following equation.

POL="L" Vd0 "H"Vd<0 ...(9) From this, the output of the comparator 90 is not affected by the offset voltage of the operational amplifiers 11 and 12, and the polarity of the differential voltage Vd between the input terminals 1 and 2 is determined. It can be seen that this shows that

Here, the operation of the comparator 90 will be explained with reference to FIG. First, at time t ₁ in Figure 8,
MOS transistor switches 92 and 94 are on, and MOS transistor switch 93 is off. As a result, the input/output terminals of the inverting amplifier 95 are connected, so that the voltage at this input/output terminal is equal to the threshold voltage of the inverting amplifier 95. Therefore, the charging voltage of the capacitor 91 is increased by the amplifier circuit 10.
This is the difference between the voltage at the other output terminal of and the threshold voltage.

Next, at time _t2 in FIG. 8, MOS transistor switches 92 and 94 are turned off, and MOS transistor switch 93 is turned on. As a result, one of the capacitors 91 is switched to the other terminal of the capacitor 31, and the other terminal of the capacitor 91 is connected only to the input of the inverting amplifier 95 having a high input impedance. Here, since one of the capacitors 91 has high impedance, the capacitor 9
The charging pressure of 1 does not change. Therefore, the output voltage of the inverting amplifier 95 changes from the threshold voltage by the voltage difference between the other output terminal of the amplifier 10 and the other terminal of the capacitor 31. Thereby, the voltages at the other output terminal of the amplifier circuit 10 and the other terminal of the capacitor 31 can be compared.

Next, at the time _t3 in FIG. 7, the MOS transistor switch is switched to the output point 8 of the comparator 90 at the time _t2 .
The control circuit 96 determines that when POL="L", MOS transistor switches 55 and 56 are on, and when POL="H", MOS transistor switches 57 and 58 are off. MOS transistor switches 55 and 56 are off and MOS transistor switches 57 and 58 are on. Furthermore, regardless of the state of the signal POL at the output point 84, the MOS transistor switch 32,
33 is on, and the others are off.

As a result of the above, when POL="L", the circuit configuration in the embodiment shown in FIG. 4 is the same as that at time t ₂ in FIG. 5, and the charging voltage V ₃₁ of the capacitor 31 is equal to the equation (5) above. Become.

On the other hand, when POL="H", input terminals 1 and 2 are connected to the (+) inputs of operational amplifiers 12 and 11, respectively, so the charging voltage of capacitor 31 is V ₃₁
is the following formula.

V ₃₁ = (1 + R ₁₃ + R ₁₅ / R ₁₄ ) (-Vd + Vos ₂ - Vos ₁ ) ...(10) Next, at time t ₄ in Fig. 7, MOS transistor switches 34, 35, and 64 are turned on, and the others are turned on. Turn off. This is the embodiment shown in FIG. 4 and the embodiment shown in FIG.
The circuit configuration becomes the same as the state at time t ₃ . Therefore,
From equations (5), (6), (9), and (10), the voltage V ₀ of output terminal 3 is
It is shown by the following formula.

As a result, it can be seen that in the embodiment shown in FIG. 6 as well, the offset voltages of the operational amplifiers 11, 12, and 61 can be corrected, and the absolute value of the voltage difference between the input terminals 1 and 2 can be amplified.

Here, since the offset voltage is corrected with the two inputs of the differential output amplifier circuit 10 connected to the input terminal 1 and biased, the CMRR characteristics of the differential output amplifier circuit 10 can also be corrected at the same time.

Therefore, according to this embodiment, the offset voltage and CMRR characteristics of the operational amplifier can be corrected, and the absolute value of the input voltage can be amplified, so that it can be applied to a single power supply circuit system to improve accuracy.

Note that other embodiments of the present invention can be modified as follows, if necessary.

(1) Each MOS transistor switch has a junction field effect transistor, bipolar transistor,
Use relays, etc.

(2) Use an amplifier circuit that uses impedance as a feedback element.

〔Effect of the invention〕

As explained above, according to the present invention, adjustment of resistance accuracy can be simplified and accuracy can be improved, and offset errors of operational amplifiers can be corrected, so accuracy can be further improved. can.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a conventional differential amplifier circuit, Fig. 2 is a circuit diagram showing the main part of the present invention, Fig. 3 is a control waveform diagram of Fig. 2, and Fig. 4 is an implementation of the present invention. A circuit diagram showing an example, FIG. 5 is a control waveform diagram of the embodiment shown in FIG. 4, FIG. 6 is a circuit diagram showing another embodiment of the present invention, and FIGS. 7 and 8 are a control waveform diagram of the embodiment shown in FIG. FIG. 3 is an example control waveform diagram. 10... Amplifier circuit, 11, 12... Operational amplifier, 13, 14, 15... Resistor, 30,300...
...Differential single-ended conversion circuit, 31, 32, 3
3, 34, 35...MOS transistor switch.

Claims (1)

[Claims] 1. An amplifier circuit 10 having a pair of operational amplifiers 11 and 12 and amplifying voltages input from two input terminals 1 and 2 to output a differential voltage;
two switch elements 32 at the output ends of 0,
33, 34, and 35 are connected in series, and the common connection point of the two switches is connected to the first capacitor 31.
a differential single-end conversion circuit 30 connected via a differential single-end conversion circuit 30, two switch elements 51, 52 inserted between the input terminals 1, 2 and the operational amplifiers 11, 12, respectively, and the input terminals 11, 1
A switch element 5 formed by connecting 2 in a short-circuit manner.
3, 54/55, 57/56, 58, a second capacitor 62 and a switch element 64 connected to one output terminal of the differential single-ended conversion circuit 30.
a series connection body, a switch element 63 formed by connecting a common connection point of the series connection body and the other output terminal 3 of the differential single-end conversion circuit 30 so as to be short-circuitable; Control terminals 71, 72, 73, 74 for inputting on/off control signals,
75 and 76. 2. The differential amplifier circuit according to claim 1, characterized in that a buffer amplifier 61 is inserted into the other output terminal 3 of the differential single-end conversion circuit 30.