JPH0212744Y2 - - Google Patents
Info
- Publication number
- JPH0212744Y2 JPH0212744Y2 JP1983109760U JP10976083U JPH0212744Y2 JP H0212744 Y2 JPH0212744 Y2 JP H0212744Y2 JP 1983109760 U JP1983109760 U JP 1983109760U JP 10976083 U JP10976083 U JP 10976083U JP H0212744 Y2 JPH0212744 Y2 JP H0212744Y2
- Authority
- JP
- Japan
- Prior art keywords
- amplifier circuit
- differential amplifier
- input
- circuit
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000003321 amplification Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010408 sweeping Methods 0.000 description 1
Landscapes
- Amplifiers (AREA)
Description
【考案の詳細な説明】 ［産業上の利用分野］ 本考案はSN比を向上させた増幅回路に関する。[Detailed explanation of the idea] [Industrial application field] The present invention relates to an amplifier circuit with improved signal-to-noise ratio.
［従来の技術］
第１図は１個の演算増幅器OP、抵抗R1，R2，
R3，R4、入力源e1，e2から成る差動増幅回路で
ある。この様な増幅回路において、入力源e1から
入力電圧1/2Es、入力源e2から入力電圧1/2Esを印
加すると、（R2／R1）Esの電圧が出力される。[Prior art] Figure 1 shows one operational amplifier OP, resistors R 1 , R 2 ,
This is a differential amplifier circuit consisting of R 3 , R 4 and input sources e 1 and e 2 . In such an amplifier circuit, when an input voltage 1/2E s is applied from the input source e 1 and an input voltage 1/2E s is applied from the input source e 2 , a voltage of (R 2 /R 1 )E s is output.
［考案が解決使用とする課題］
さて、この様な増幅回路の入力換算ノイズは前
記演算増幅器の特性により決定されるので、この
増幅回路ではSN比の向上は望めない。即ち、該
演算増幅器の入力換算ノイズをenとすれば、こ
の増幅回路の出力ノイズは、ノイズに対する利得
が（１＋（R2／R1））なので、（１＋（R2／R1））
enとなる。ここで、該ノイズに対する利得をG1
とおけば、該増幅回路の出力ノイズはG1enと表
わせれる。[Problems to be solved by the invention] Now, since the input-referred noise of such an amplifier circuit is determined by the characteristics of the operational amplifier, it is impossible to expect an improvement in the SN ratio with this amplifier circuit. That is, if the input equivalent noise of the operational amplifier is en, the output noise of this amplifier circuit is (1+(R 2 /R 1 )) since the gain with respect to noise is (1+(R 2 /R 1 )).
It becomes en. Here, the gain for the noise is G 1
Then, the output noise of the amplifier circuit can be expressed as G 1 en.
又、回路の入力換算ノイズは、（回路の出力ノ
イズ）／（回路の利得）なので、回路の利得
R2／R1をG0とおけば、
G1en／G0
となる。 Also, the circuit input noise is (circuit output noise)/(circuit gain), so the circuit gain is
If R 2 /R 1 is set as G 0 , it becomes G 1 en /G 0 .
すると、この増幅回路のSN比は、 Es／（G1en／G0） 即ち、G0Es／G1en と表わせれる。 Then, the SN ratio of this amplifier circuit can be expressed as E s /(G 1 en /G 0 ), that is, G 0 E s /G 1 en.
この式において、G0，G1，Esは固定のものと
考えると、この回路のSN比は前記１個の演算増
幅器OPの入力換算ノイズenで決まつてしまう。 In this equation, assuming that G 0 , G 1 , and E s are fixed, the SN ratio of this circuit is determined by the input equivalent noise en of the one operational amplifier OP.
従つて、この様な増幅回路を、例えば、質量分
析装置等の磁場掃引系に用いると、分解能の向上
が望めない。 Therefore, if such an amplifier circuit is used in a magnetic field sweeping system of a mass spectrometer, for example, no improvement in resolution can be expected.
本考案はこの様な問題を解決することを目的と
したものである。 The present invention aims to solve such problems.
［課題を解決する為の手段］
本考案の増幅回路は、入力源からの入力を複数
の段階で増幅する様に成し、各段階に順次前の段
階の半数の差動増幅回路を設け、第１段階で増幅
する差動増幅回路としてそのゲインが他の段階の
差動増幅回路のゲインより大きいものを設け、且
つ該第１段階の各差動増幅回路各々の両入力端が
前記入力源に繋がつている事を特徴とする。[Means for solving the problem] The amplifier circuit of the present invention is configured to amplify the input from the input source in multiple stages, and each stage is sequentially provided with half the number of differential amplifier circuits of the previous stage, A differential amplifier circuit for amplification in the first stage is provided whose gain is larger than the gain of the differential amplifier circuits in the other stages, and both input terminals of each differential amplifier circuit in the first stage are connected to the input source. It is characterized by being connected to.
第２図は本考案の一実施例を示した増幅回路で
ある。図中１，２，３，４は演算増幅器OP1、抵
抗R1，R2，R3，R4から成るゲインG1例えば、１
０の差動増幅回路で、夫々第１、第２、第３、第
４差動増幅回路と名付ける。各増幅回路の正負の
端子には入力源１０からの入力電圧Esが印加され
ている。５，６は演算増幅器OP2、抵抗R5，R6，
R7，R8から成るゲインG2が前記第１、第２、第
３、第４差動増幅回路のゲインより可成小さい
（例えば１）の差動増幅回路で、各増幅回路の正
負の端子には前記増幅回路１，２の出力、３，４
の出力が夫々印加されている。尚、該各増幅回路
を第５，第６差動増幅回路と名付ける。７は該差
動増幅回路と同様に演算増幅器OP2、抵抗R5，
R6，R7，R8から成るゲインG3が前記第５，第６
差動増幅回路のゲインと同じ１の差動増幅回路で
ある。該回路の正負の端子には前記増幅器５，６
の出力が印加されている。尚該増幅回路を第７差
動増幅回路と名付ける。 FIG. 2 shows an amplifier circuit showing an embodiment of the present invention. In the figure, 1, 2, 3, and 4 are gain G 1 consisting of an operational amplifier OP 1 and resistors R 1 , R 2 , R 3 , and R 4. For example, 1
0 differential amplifier circuits, which will be named first, second, third, and fourth differential amplifier circuits, respectively. An input voltage Es from an input source 10 is applied to the positive and negative terminals of each amplifier circuit. 5 and 6 are operational amplifier OP 2 , resistors R 5 , R 6 ,
A differential amplifier circuit in which the gain G 2 consisting of R 7 and R 8 is considerably smaller (for example, 1) than the gains of the first, second, third, and fourth differential amplifier circuits, and the positive and negative polarities of each amplifier circuit are The outputs of the amplifier circuits 1 and 2, 3 and 4 are connected to the terminals.
The outputs of are applied respectively. Incidentally, each of the amplifier circuits will be named a fifth and a sixth differential amplifier circuit. Similarly to the differential amplifier circuit, 7 is an operational amplifier OP 2 , a resistor R 5 ,
The gain G 3 consisting of R 6 , R 7 and R 8 is
This is a differential amplifier circuit with a gain of 1, which is the same as that of the differential amplifier circuit. The amplifiers 5 and 6 are connected to the positive and negative terminals of the circuit.
The output of is applied. The amplifier circuit will be named the seventh differential amplifier circuit.
斯くの如き増幅回路において、第１、第２、第
３、第４差動増幅回路１，２，３，４の各正負入
力端子に入力源１０から入力電圧Esを印加する
と、該第１、第２、第３、第４差動増幅回路に
夫々＋10Es，−10Es，−10Es，＋10Esの電圧が出力
される。該各出力は夫々第５，第６差動増幅回路
５，６の正負入力端子に印加されるので、該各増
幅回路に夫々−20Es，＋20Esの電圧が出力される。
該出力は夫々第７差動増幅回路７の入力端子に印
加されるので、該増幅回路に＋40Esの電圧が出力
される。 In such an amplifier circuit, when an input voltage E s is applied from the input source 10 to each of the positive and negative input terminals of the first, second, third, and fourth differential amplifier circuits 1, 2, 3, and 4, , voltages of + 10Es , -10Es , -10Es , and + 10Es are output to the second, third, and fourth differential amplifier circuits, respectively. Since the respective outputs are applied to the positive and negative input terminals of the fifth and sixth differential amplifier circuits 5 and 6, respectively, voltages of -20E s and +20E s are output to the respective amplifier circuits.
Since the outputs are respectively applied to the input terminals of the seventh differential amplifier circuit 7, a voltage of +40E s is output to the amplifier circuits.
さて、この様な構成の増幅回路の出力ノイズを
計算してみると、各第１、第２、第３、第４差動
増幅回路の演算増幅器の入力換算ノイズ電圧分を
en1，en2，en3，en4とすると、
G1√1 2＋2 2＋3 2＋4 2
である。ここで、en1＝en2＝en3＝en4＝enなの
で、該出力換算ノイズは
2G1en
となる。尚、第５、第６差動増幅回路５，６での
ノイズ電圧分は、該増幅回路のゲイン（G2＝１）
が前記第１、第２、第３、第４差動増幅回路のゲ
イン（G1＝10）の1/10なので、出力ノイズは
夫々（1/10）2と極めて小さく無視出来る。第７差
動増幅回路７のノイズ電圧も同様に無視出来る。 Now, when calculating the output noise of an amplifier circuit with such a configuration, the input equivalent noise voltage of the operational amplifier of each of the first, second, third, and fourth differential amplifier circuits is calculated as follows:
If en 1 , en 2 , en 3 , en 4 , then G 1 √ 1 2 + 2 2 + 3 2 + 4 2 . Here, since en 1 = en 2 = en 3 = en 4 = en, the output conversion noise is 2G 1 en. Note that the noise voltage in the fifth and sixth differential amplifier circuits 5 and 6 is the gain (G 2 = 1) of the amplifier circuit.
is 1/10 of the gain (G 1 =10) of the first, second, third, and fourth differential amplifier circuits, so the output noise is (1/10) 2 and can be ignored. The noise voltage of the seventh differential amplifier circuit 7 can also be ignored.
又、この様な構成の増幅回路の入力換算ノイズ
は、
2G1en／4G0
即ち、G1en／2G0
と表わされる。 Further, the input equivalent noise of the amplifier circuit having such a configuration is expressed as 2G 1 en/4G 0 , that is, G 1 en/2G 0 .
そして、この結果、入力Esの40倍の出力が得ら
れるので、この増幅回路のSN比は
40Es／（G1en／2G0）
即ち、80G0Es／G1en
となり、従来の１個の差動増幅回路のものに対し
80倍となる。 As a result, an output that is 40 times the input E s is obtained, so the SN ratio of this amplifier circuit is 40E s / (G 1 en / 2G 0 ), that is, 80G 0 E s /G 1 en , which is different from the conventional one. For one differential amplifier circuit
80 times more.
尚、前記実施例では入力に対し、第１増幅段階
に４つの差動増幅回路を、第２段階に２つの差動
増幅回路を、第３段階に１つの差動増幅回路を
夫々設けたが、これに限定されず、第１段階に２
つ、第２段階に１つの差動増幅回路を夫々設けて
もよいし、増幅回路をふやして増幅段階をふやす
様にしてもよい。 In the above embodiment, four differential amplifier circuits were provided in the first amplification stage, two differential amplifier circuits were provided in the second stage, and one differential amplifier circuit was provided in the third stage for the input. , but not limited to, the first stage includes 2
One differential amplifier circuit may be provided in each of the second stages, or the number of amplification stages may be increased by increasing the number of amplifier circuits.
［考案の効果］
本考案の増幅回路は従来の１個の演算増幅器を
備えた増幅回路に比べ著しくSN比が改善される。
その為、この様な増幅回路を例えば質量分析装置
等の磁場掃引系に用いると、分解能を向上させる
ことが出来る。[Effects of the Invention] The amplifier circuit of the present invention has a significantly improved SN ratio compared to a conventional amplifier circuit equipped with one operational amplifier.
Therefore, if such an amplifier circuit is used in a magnetic field sweep system of a mass spectrometer, for example, the resolution can be improved.
第１図は従来の増幅回路、第２図は本考案の一
実施例を示した増幅回路である。
１：第１差動増幅回路、２：第２差動増幅回
路、３：第３作動増幅回路、４：第４差動増幅回
路、５：第５差動増幅回路、６：第６差動増幅回
路、７：第７差動増幅回路、１０：入力源。
FIG. 1 shows a conventional amplifier circuit, and FIG. 2 shows an amplifier circuit according to an embodiment of the present invention. 1: First differential amplifier circuit, 2: Second differential amplifier circuit, 3: Third differential amplifier circuit, 4: Fourth differential amplifier circuit, 5: Fifth differential amplifier circuit, 6: Sixth differential amplifier circuit. Amplifier circuit, 7: seventh differential amplifier circuit, 10: input source.
Claims (1)
成し、各段階に順次前の段階の半数の差動増幅回
路を設け、第１段階で増幅する差動増幅回路とし
てそのゲインが他の段階の差動増幅回路のゲイン
より大きいものを設け、且つ該第１段階の各差動
増幅回路各々の両入力端が前記入力源に繋がつて
いる増幅回路。 The input from the input source is amplified in multiple stages, and each stage is sequentially provided with half the number of differential amplifier circuits of the previous stage, and the gain of the differential amplifier circuit amplified in the first stage is an amplifier circuit having a gain greater than that of the differential amplifier circuits in the first stage, and both input ends of each differential amplifier circuit in the first stage are connected to the input source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10976083U JPS6019218U (en) | 1983-07-15 | 1983-07-15 | amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10976083U JPS6019218U (en) | 1983-07-15 | 1983-07-15 | amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6019218U JPS6019218U (en) | 1985-02-09 |
| JPH0212744Y2 true JPH0212744Y2 (en) | 1990-04-10 |
Family
ID=30255553
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10976083U Granted JPS6019218U (en) | 1983-07-15 | 1983-07-15 | amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6019218U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0821821B2 (en) * | 1991-10-30 | 1996-03-04 | 株式会社エヌエフ回路設計ブロック | amplifier |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS544593A (en) * | 1977-06-13 | 1979-01-13 | Epson Corp | Liquid crystal indicator by multiple pattern |
-
1983
- 1983-07-15 JP JP10976083U patent/JPS6019218U/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS544593A (en) * | 1977-06-13 | 1979-01-13 | Epson Corp | Liquid crystal indicator by multiple pattern |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6019218U (en) | 1985-02-09 |
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