JPH062335Y2 - Balanced amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a balanced amplifier for audio and the like.

[Prior Art] A conventional balanced amplifier has a configuration as shown in FIG.

The first input is input to the non-inverting input terminal of the first differential amplifier 2 via the first input resistor 1, and the amplified output is input to the first input.
Is output from the output terminal 3 of the first differential amplifier 2 and is negatively fed back to the inverting input terminal of the first differential amplifier 2 via the first feedback resistor 4. The second input is input to the non-inverting input terminal of the second differential amplifier 6 via the second input resistor 5, and its amplified output is output from the second output terminal 7 and Is negatively fed back to the inverting input terminal of the second differential amplifier 6 via the second feedback resistor 8.

The inverting input terminal of the first differential amplifier 2 is connected to the non-inverting input terminal of the second differential amplifier 6, and the inverting input terminal of the second differential amplifier 6 is connected to the above 1 to the non-inverting input terminal of the differential amplifier 2.

Further, 9 outputs the positive and negative power supply voltages VA and VB.
The power supply circuit supplies negative power supply voltages VA and VB to the first and second differential amplifiers 2 and 6, respectively.

Here, the first input resistance 1 and the second input resistance 5 are set to the same resistance value R1, and the first feedback resistance 4 and the second feedback resistance 8 are set to the same resistance value R2, respectively.

In such a configuration, as shown in FIG. 4, the first input voltage is e1, the second input voltage is e2, and the first output terminal 3 is
Output voltage of V1, the output voltage of the second output terminal 7 is V2, and the bare gains of the first and second differential amplifiers 2 and 6 are A1 and A2, respectively.
And the voltages at the non-inverting input terminals of the first and second differential amplifiers 2 and 6 are v3 and v4, respectively, the following equations are derived.

V1 = A1 (v3-v4)… (1) V2 = A2 (v4-v3) =-A2 (v3-v4)… (2) From equations (1) and (2), V1-V2 = (A1 + A2) (v3-v4)… (5) From equations (3) and (4), Substituting equation (6) into equation (5), Becomes If you organize this, Becomes Where A1 and A2 are on the order of 10 ⁵ and R2 /
Since R1 is at most several tens, if (A1 + A2) R1 >> R1 + R2, then the above formula becomes However, e1: first input voltage e2: second input voltage R1: first and second input resistance R2: first and second feedback resistance.

That is, in the balanced amplifier having such a configuration, when the first and second inputs are in-phase inputs, the output does not appear between the first and second output terminals 3 and 7.

Therefore, when used as an audio amplifier, the first differential amplifier 2 and the second differential amplifier 6 are configured to operate with anti-phase inputs.

[Problems to be Solved by the Invention] In such a configuration, as shown in FIG. 5, the input terminals are grounded and the input conversion offset voltages of the first and second differential amplifiers 2 and 6 are each Δe1. , Δe2, the first and second
The output offset voltages V10 and V20 with respect to the ground at the output terminals 3 and 7 are obtained.

The following equations are derived from the figure respectively.

V10 = A1 (v3-v4 + Δe1) = A1 (v3-v4) + A1Δe1 (7) V20 = A2 (v4-v3 + Δe2) = -A2 (v3-v4) + A2Δe2 (8) From equations (9) and (10), From equations (7) and (8), V10-V20 = (A1 + A2) (v3-v4) + A1Δe1-A2Δe2 (12) Substituting equation (11) into equation (12) gives If you organize this, Becomes Similarly, if (A1 + A2) R1 >> R1 + R2, then the above formula becomes Becomes

From equations (7) and (8), V10 + V20 = (A1 + A2) (v3-v4) + A1Δe1 + A2Δe2 (14) Substituting equation (11) into equation (14) gives Substituting equation (13) into equation (15), If you organize this, Here, similarly, if 2A2R1 >> R1 + R1 2A2R1 >> R1 + R2 (A1 + A2) R1 >> R1 + R2, then the above formula becomes Becomes

Also, according to equations (13) and (16), therefore, Similarly, Becomes

That is, the output offset voltages V10 and V20 have almost the same value, and the sum voltage (Δe1 + Δe2) of the input conversion offset voltages Δe1 and Δe2 of the first and second differential amplifiers 2 and 6 is (A1A
2 / (A1 + A2)) times.

Here, in general, A1 and A2 are on the order of 10 ^5, so (A1A2 / (A1 + A2)) is also on the order of 10 ^5, so even if | Δe1 + Δe2 | is several mV, the output The offset voltages | V10 | and | V20 | are theoretically values of several tens to several hundreds of volts, and these values are generally higher than the power supply voltages | VA | and | VB |.

Therefore, if (Δe1 + Δe2)> 0, the output offset voltages V10 and V20 are limited by the positive power supply voltage VA,
Both are fixed to the voltage VA. Conversely, (Δe1 + Δe2) <
When it is 0, the output offset voltages V10 and V20 are limited by the negative power supply voltage VB, and both are fixed to the voltage VB. Then, these states become the output bias voltage when there is no signal.

In this state (V10, V20 = VA ((Δe1 + Δe2)> 0)), input signals e1 (first input voltage e1) and e2 (second input voltage e2) to the first and second inputs. Think about when you do.

Even in this case, the above relationship is established.

For example, when (e1-e2)> 0, if it is normal operation,
The output voltage V1 should operate in the positive direction and the output voltage V2 should operate in the negative direction, but the output voltage V1 is not larger than the positive power supply voltage VA and is fixed. Therefore, eventually, only the output voltage V2 operates.

On the other hand, when (e1-e2) <0, the output voltage V2 is not larger than the positive power supply voltage VA and is fixed. In the end, only the output voltage V1 operates.

That is, even though the first differential amplifier 2 and the second differential amplifier 6 are configured to operate in opposite phases at the same time, the positive and negative half cycles of the input signal are respectively divided into the first and second half cycles. Since the first and second differential amplifiers 2 and 6 alternately perform the amplifying operation, and therefore the symmetrical amplifying operation is not performed, the balance is poor and the distortion increases.

[Means for Solving the Problems] The present invention comprises a first amplifier 2 for amplifying a first input and a second amplifier 6 for amplifying a second input, wherein the first amplifier is provided. In the balanced amplifier in which the output is taken out between the first output terminal 3 of No. 2 and the second output terminal 7 of the second amplifier 6, the first output terminal 3 and the second output terminal 7 are provided. First and second integration resistors 1 having the same resistance value connected in series between
1 and 12 are connected, and the first and second integration resistors 11 and 1 are connected.
The connection midpoint of 2 is connected to the inverting input terminal of the second differential type amplifier 14, and this inverting input terminal is connected to the output of the third differential type amplifier 14 via the integrating capacitor 13 and The non-inverting input terminal of the third differential amplifier 14 is supplied with a voltage obtained by equally dividing the power supply voltage to supply the Miller integrating circuit 10
And the ultra low frequency component and the direct current component of a predetermined frequency or lower, which are detected and amplified by the Miller integrating circuit 10,
The differential amplifier 2 and the second differential amplifier 6 are negatively fed back to the respective input sides.

[Operation] Hereinafter, in the first and second differential amplifiers 2 and 6, the case where the first and second inputs are in-phase inputs will be described.

From the ultra-low frequency region below a predetermined frequency to the direct current region, the Miller integrating circuit 10 causes the positive and negative power supply voltages V
A and VB divided equally The output voltage of the first and second output terminals 3 and 7 with reference to
Ultra-low frequency components and DC components below the predetermined frequency of the sum of the in-phase components of V1 and V2 (V1 + V2) are detected and amplified, and these components are input to the first and second differential amplifiers 2 and 6. Negative feedback to each side. Since this feedback amount βs is much larger than the feedback amount βf of the first and second differential amplifiers 2 and 6 as negative feedback amplifiers, the output voltage V1 of the first and second output terminals 3 and 7 is , V2 is from the very low frequency region to the DC region, Becomes

That is, since the output voltages V1 and V2 are fixed at the centers of the positive and negative DC power supply voltages VA and VB, the first and second differential amplifiers 2 and 6 are balanced and symmetrical. Amplify operation.

[Embodiment] (Embodiment I) This will be described with reference to FIG. In the figure, those parts that are the same as those corresponding to the conventional example shown in FIG. 3 are designated by the same reference numerals, and a description thereof will be omitted.

The first and second integrating resistors 11 and 12 (both having the same resistance 2R) connected in series are connected between the first output terminal 3 and the second output terminal 7, and the first and second integrating resistors 11 and 12 are connected to each other. The connection midpoint of the integrating resistors 11 and 12 is connected to the inverting input terminal of the third differential amplifier 14, and the inverting input terminal is connected via the integrating capacitor 13 (capacitance C) to the third differential amplifier 14 described above. Connect to the output of. And positive and negative power supply voltage
The first and second resistors 17 and 18 (having the same resistance value R ⁵ ) connected in series are connected between the positive and negative power supply terminals 15 and 16 to which VA and VB are supplied. 2 resistance 1
The Miller integrating circuit 10 is constructed by connecting the midpoint of connection of 7 and 18 to the non-inverting input terminal of the third differential amplifier 14.

Since the Miller integrating circuit 10 has a low-frequency enhancement characteristic that enhances at 6 dB / oct, the first and second differential amplifiers 2 and 2 described above are provided.
From the output of 6 (the sum (V1 + V2) of the in-phase components of the output voltages V1 and V2), the ultra-low frequency component and the direct current component below a predetermined frequency are detected and amplified.

This component is negatively fed back to the non-inverting input terminal of the first differential amplifier 2 via the third resistor 19, and a fourth feedback circuit is provided between the non-inverting input terminal and the first input resistor 7. Resistance 1
Connect 9.

Similarly, the ultra low frequency component and the direct current component are negatively fed back to the non-inverting input terminal of the second differential amplifier 6 via the fifth resistor 21, and the non-inverting input terminal and the second input are also fed back. The sixth resistor 22 is connected between the resistor 5 and the resistor 5.

Here, the first resistor 17 and the second resistor 18 have the same resistance value R ⁵ , the third resistor 19 and the fifth resistor 21 have the same resistance value R ³ , the fourth resistor 20 and the fourth resistor 20 have the same resistance value R ⁵ . The same resistance value R ^{4 as} that of the resistor 22 of 6 is set.

In the first and second differential amplifiers 2 and 6, the first and second differential amplifiers
The operation will be described for the case where the input is the in-phase input.

A potential obtained by equally dividing the positive and negative power source voltages VA and VB by the Miller integrator circuit 10 in the direct current region from the ultra-low frequency region of several Hz or less. Based on, the output of the first and second differential amplifiers 2 and 6 (the sum of the in-phase components of the output voltages V1 and V2 (V1 + V2) is detected as an ultra-low frequency component and a DC component below a predetermined frequency. Since this component is fed back to the input side of each of the first and second differential amplifiers 2 and 6, the amplification type including the Miller integrator circuit 10 in the ultra low frequency region to the DC region. The feedback amount βs by the negative feedback loop is much larger than the feedback amount βf by the first and second feedback resistors 4 and 8. Then, the total feedback amount is the total of the feedback amount βs and the feedback amount βf, It rapidly increases from the very low frequency region to the DC region.

Therefore, the total gain is significantly reduced from the very low frequency region to the DC region.

In the very low frequency range, the first and second inputs (common mode input)
With respect to the sum (V1, V2) of the output voltages V1 and V2 with respect to, the turnover frequency ω1 at which the total feedback amount of increases and the total gain begins to decay is as follows.

Here, ω1 is a turnover frequency for the in-phase input (e1 + e2) and the input conversion in-phase offset (Δe1 + Δe2).

The above characteristics will be briefly described below by obtaining the inter-terminal voltage (V1 + V2) of the first and second output terminals 3 and 7 with respect to the in-phase input (e1 + e2) and the input conversion in-phase offset (Δe1 + Δe2).

In FIG. 6, the first and second input voltages are designated as e1 and e, respectively.
2, the output voltage of the first and second output terminals 3 and 7, respectively
1, V2, the voltages at the non-inverting input terminals of the first and second differential amplifiers 2 and 6 are v3 and v4, respectively, the output voltage of the Miller integrating circuit 10 is v5, and the third difference forming the Miller integrating circuit 10 is The voltage at the connection point of the non-inverting input terminal of the dynamic amplifier 14 is Vc.

Further, the input conversion offset voltage (or input conversion noise) of the first, second, and third differential amplifiers 2, 6, and 14 is set to Δe1, Δe2, and Δe3, respectively.

When the voltage of each part is determined as described above, the following relational expressions are derived.

The bare gain of the first and second differential amplifiers 2 and 6 is A
Since 1 and A2 are large enough and the formula and its formula are considerably complicated, these naked gains are treated as (∞) from A1 and A2 because of other constant relations.

Vc = VA + VB / 2 From the above equations, the calculation in the middle is omitted, but (V1 + V2),
When (V1-V2) is calculated, However, ω0 = 1 / CR Becomes

Here, if the in-phase input 2ec, the anti-phase input 2ed, the input conversion in-phase offset 2Δec, and the input conversion in-phase offset 2Δed are defined as 2ec = e1 + e2 2ed = e2-e2 2Δec = Δe1 + Δe2 2Δed = Δe1-Δe2, respectively (22) , (23) is become that way.

If V1 and V2 are calculated from these equations (24) and (25), Becomes

From these expressions, the original amplification operation as the balanced amplifier, that is, the output voltage (V
As for 1-V2), as is clear from the equation (24), it operates as a DC amplifier that performs amplification operation up to the DC region, and
For the in-phase input component 2ec (= e1 + e2) of the input signal and the input conversion in-phase offset 2Δec (= Δe1 + Δe2), the total feedback amount increases in the ultra-low frequency region, and the total gain starts to attenuate from the turnover frequency ω1. The characteristic becomes a characteristic, and the components having the turnover frequency ω1 or less are attenuated.

Further, the DC bias of the output voltages V1 and V2 is ω = 0 in the above equation, and the in-phase input 2ec and the anti-phase input 2ed are ec = 0 ed = 0. Becomes

Therefore, the input conversion offset voltage Δe3 and the input conversion negative phase offset 2Δed of the third differential amplifier 14 are at most several.
Since it is mV, V1 (DC-OFFSET) ≈V2 (DC-OFFSET) ≈Vc.

That is, the output voltage V1, V2, from the ultra-low frequency region to the DC region, Therefore, since the direct current is fixed to the center of the positive and negative power supply voltages VA and VB, the first and second differential amplifiers 2 and 6 perform balanced and symmetrical amplification operation.

(Embodiment II) As shown in FIG. 2, this embodiment shows another embodiment in which the semiconductor amplifying element is incorporated in the first and second differential amplifiers 2 and 6 in a discrete form. The action and effect are the same as in (Example I).

In addition, in (Example I) and (Example II), in the first and second amplification type negative feedback loops, negative feedback to the input side of the first and second differential type amplifiers 2 and 6 is The present invention is not limited to the embodiment, and may be a location where the output common-mode potential can be varied and a location symmetrical in terms of circuit configuration.

[Advantages of the Invention] The present invention provides the first and second differential amplifiers 2 and 6 having the first and second differential amplifiers 2 and 6 in an ultra-low frequency region below a predetermined frequency and a direct current region.
Regarding the output voltages V1 and V2 of the second output terminals 3 and 7, the input conversion offset voltages Δe1 and Δe2 of the first and second differential amplifiers 2 and 6 are significantly attenuated and are small enough to be practically ignored. In addition, the DC offset voltage of the output voltages V1 and V2 is the voltage V that is obtained by dividing the positive and negative power supply voltages VA and VB into equal parts.
c, the input conversion offset voltage Δe3 of the third differential amplifier 14 and the input conversion negative phase offset voltage 2Δed (= Δe1−Δe2) of the first and second differential amplifiers 2 and 6, Since the input-converted offset voltage Δe3 and the input-converted reverse-phase offset voltage 2Δed are extremely small, the output voltages V1 and V2 are fixed at the centers of the DC voltages VA and VB, which are positive and negative in terms of DC. The second differential amplifiers 2 and 6 perform balanced and symmetrical amplification operation, and
Since the configuration is such that only one Miller integrating circuit 10 is added, there is an effect that the circuit configuration is simple and practical.

[Brief description of drawings]

1 is a diagram showing a configuration of a balanced amplifier of the present invention, FIG. 2 is a diagram showing a configuration of another embodiment of the present invention, FIG. 3 is a diagram showing a configuration of a conventional balanced amplifier, FIG. 4 and FIG. FIG. 5 is a diagram for analyzing the characteristic of the conventional balanced amplifier, and FIG. 6 is a diagram for analyzing the characteristic of the balanced amplifier of the present invention. 1 ... First input resistance, 2 ... First differential amplifier, 3
...... First output terminal, 4 ... First feedback resistance, 5 ... Second input resistance, 6 ... Second differential amplifier, 7 ... Second
Output terminal, 8 ... second feedback resistor, 9 ... power supply circuit,
10 ... Miller integrating circuit, 11 ... First integrating resistor, 1
2 ... second integration resistance, 13 ... integration capacitor, 14
...... Third differential amplifier, 15, 16 …… Positive and negative power supply terminals, 17 …… First resistance, 18 …… Second resistance,
19 ... third resistance, 20 ... fourth resistance, 21 ... fifth resistance, 22 ... sixth resistance.

Claims (1)

[Scope of utility model registration request] 1. A first input is input to a non-inverting input of a first differential amplifier (2), the amplified output is output from a first output terminal (3), and a first feedback resistor is also provided. Via (4), negative feedback is provided to the inverting input terminal of the first differential amplifier (2) to form a first negative feedback loop, and a second input having a phase opposite to that of the first input is provided. It is input to the non-inverting input of the second differential amplifier (6), the amplified output is output from the second output terminal (7), and the second feedback resistor (8) is used to output the second output. Negative feedback is provided to the inverting input terminal of the differential amplifier (6) to form a second negative feedback loop, and the first input is input to the inverting input terminal of the second differential amplifier (6). At the same time, the second input is input to the inverting input terminal of the first differential amplifier (2), and the first input of the first differential amplifier (2) is input. A balanced amplifier in which an output is taken out between the input terminal (3) and the second output terminal (7) of the second differential amplifier (6), The first and second integrating resistors (1 having the same resistance value connected in series with the second output terminal (7)
1) and (12) are connected, and the connection midpoint of the first and second integration resistors (11) and (12) is connected to the inverting input terminal of the third third differential amplifier (14). Then, the inverting input terminal is connected to the output of the third differential amplifier (14) through the integrating capacitor (13) and is connected to the non-inverting input terminal of the third differential amplifier (14). The Miller integrator circuit (10) is configured by supplying a voltage obtained by equally dividing the power supply voltage, and the ultra low frequency component and the direct current component of a predetermined frequency or lower detected and amplified by the Miller integrator circuit (10) are used as the first By performing negative feedback to the first input side of the differential amplifier (2), the feedback amount is sufficiently larger than that of the first feedback loop in the ultra-low frequency region and DC region below the predetermined frequency. In addition to configuring the first amplification type negative feedback loop, The ultra-low frequency component and the direct current component, which are detected and amplified by the Miller integrator circuit (10) and have a predetermined frequency or less, are negatively fed back to the second input side of the second differential amplifier (6). A balanced amplifier, comprising a second amplification type negative feedback loop having a feedback amount sufficiently larger than that of the second negative feedback loop in an ultra-low frequency region and a direct current region below a predetermined frequency.