JPH03113575A - Generation system for mounting components wiring information - Google Patents

Abstract

PURPOSE:To prevent the misgeneration of via holes and the mistake of a lead- out pattern wiring by regarding entire via holes as single components and producing a virtual parts to generate a net between each pin and its corresponding via holes. CONSTITUTION:A surface mount component 31 is selected out of the component data on a printed board stored previously in a data storage 3 from an input/ output device 1. Then the via hole information showing the via hole position is taken out of a component library which is already registered to the device 1 with the structure of the components 31 used as a key. The via hole position shows each correspondence between the pins 35 of the components 31 and the positions of via hole 33 and 34. These via hole 33, 34 are virtually regarded as pins and a virtual components 32 is set into the component data on the printed board. Thus the corresponding via holes 33 and 34 can be handled as the general component pins. Then a designer can design a lead-out pattern covering the pins of the components 31 through the via holes 33 and 34 with no special consciousness.

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a mounted component wiring information generation system, and in particular, mounted component wiring information when circuit wiring is formed from each pin (bad) of a surface mounted component on a printed circuit board via a corresponding via. It is related to the generation system.

Prior Art When connecting each pin (pad) of a surface-mounted component on a printed circuit board to another circuit, the wiring connection is often made through vias provided corresponding to each pin. Therefore, it becomes necessary to generate a lead-out pattern between each of these vias and the corresponding pins.

Conventionally, this type of drawing pattern and vias have been created manually. Therefore, pattern connection errors are likely to occur, and when a plurality of multi-pin components are mounted on a printed circuit board, the number of man-hours required for pattern design increases.

OBJECTS OF THE INVENTION The first object of the present invention is to automatically generate patterns using CAD technology by treating lead patterns between component pins and their corresponding vias in the same way as wiring processing between component pins. An object of the present invention is to provide a circuit wiring information generation system that enables the following.

Structure of the Invention According to the present invention, in order to relay lead-out patterns for circuit wiring from each pin of a surface mount component on a printed circuit board, a via provided corresponding to each pin and a via corresponding to each pin are provided. A mounted component wiring information generation system that generates a lead-out pattern between pins, the system includes means for generating a virtual component by regarding vias corresponding to each of the pins as a component pin, and means for generating a virtual component by regarding a via corresponding to each of the pins as a component pin; , and means for generating connection wiring information between the vias corresponding to each pin.

Embodiments Below, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a system block diagram showing the configuration of an embodiment of the present invention. This embodiment includes an input/output device 1, an arithmetic processing device 2,
It is composed of a data storage device 3 and a mounted component wiring information generation section 4.

The mounted component wiring information generation section 4 includes a virtual component generation section 5 and a net generation section 6. The virtual component generation unit 5 regards the vias corresponding to each pin of the mounted component to be matched as virtual pins of the component, and creates a virtual component. The net generation unit 5 generates a drawing pattern between the pins (vias) of the virtual component and the pins (pads) of the mounted component, and generates net information (a circuit consisting of component information and connection information between component pins). connection information).

FIG. 2 is a diagram showing an example of generation of a lead-out pattern 36 and vias 33, 34 from a pin (pad) 35 of a surface mount component 31, and FIG. 3 is a flowchart showing the operation of an embodiment of the present invention. .

Hereinafter, the operation of the embodiment of the present invention will be explained with reference to the specific example of FIG. 2 and the flowchart of FIG. 3. A surface mount component 31 is selected from the printed circuit board component data stored in advance in the data storage device 3 from the input/output device 1 (step 21).

Using the component structure of this surface mount component as a key, input/output device 1
The via information without indicating the via position is extracted from the registered parts library (step 22).

This via position is for each pin (pad) 35 of the mounted component 31.
Via 33. 34 position.

These vias 33 and 34 are virtually regarded as pins (pads), and the virtual component 32 is incorporated into the component data of the board (step 23).

Next, select each pin (pad) 35 of the mounted component from the net data of the board stored in advance from the input/output device 1 to the data storage device 3 (step 24);
Determine whether the pad is a used pin for signal, power/ground, etc. or an unused pin (step 25)
. If the pin is used, the virtual component 32 corresponding to that pin
The pins (V, IA) 33 are added to the net data of the board by incorporating them into the existing net (step 26). If it is an unused pin, pin 34 of the virtual component corresponding to that pin
A new net is generated between the two and added to the net data of the board (step 27).

As described above, by incorporating the vias corresponding to the pins (pads) of surface mount components into the net data as virtual components, the corresponding vias can be treated in the same way as other general component pins. This allows the designer to design the corresponding via and the extraction pattern from to this corresponding via without being particularly conscious of it.

Effects of the Invention As described above, according to the present invention, when generating a via corresponding to each pin (pad) of a surface mount component and a lead-out pattern up to this via, the entire via is regarded as one component and a virtual Since a component is generated and a net is generated between each pin and the corresponding via, it is possible to handle the wiring in the same way as wiring between other component pins, and prevents omission of via generation and lead pattern wiring mistakes. This also has the effect of reducing the number of man-hours required to design patterns around surface-mounted components.

Furthermore, since a via is always provided corresponding to each pin (pad), it is possible to create a lead-out pattern from the pad and wire from the via to the inner layer. This simplifies work such as jumper wiring, and has the effect of providing flexibility for design changes.

[Brief explanation of drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing an example of generation of a surface mount component's wiring pattern and a drawer pattern, and FIG. 3 is an operation flow diagram of the embodiment of the present invention. Explanation of symbols of main parts 5...Virtual component generation section 6...Net generation section 31...Surface mount component 32...Virtual component 33.34. ...Via 35...Pin (pad) 36...Drawer pattern

Claims (1)

[Claims] (1) In order to relay the lead-out patterns for circuit wiring from each pin of the surface-mounted component on the printed circuit board, the vias are provided corresponding to each pin, and the lead-out patterns between these vias and the corresponding pins. A mounted component wiring information generation system that generates a virtual component by regarding vias corresponding to each of the pins as component pins, and means for generating a virtual component by regarding a via corresponding to each of the pins as a component pin, and a means for generating a virtual component by regarding a via corresponding to each of the pins as a component pin; A mounting component wiring information generation system, comprising means for generating connection wiring information between corresponding vias.