JP2580986B2 - Design processing method for printed circuit boards with surface mount components - Google Patents

Design processing method for printed circuit boards with surface mount components

Info

Publication number
JP2580986B2
JP2580986B2 JP5313359A JP31335993A JP2580986B2 JP 2580986 B2 JP2580986 B2 JP 2580986B2 JP 5313359 A JP5313359 A JP 5313359A JP 31335993 A JP31335993 A JP 31335993A JP 2580986 B2 JP2580986 B2 JP 2580986B2
Authority
JP
Japan
Prior art keywords
component
wiring
printed board
pad
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5313359A
Other languages
Japanese (ja)
Other versions
JPH07168869A (en
Inventor
和之 飯島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP5313359A priority Critical patent/JP2580986B2/en
Publication of JPH07168869A publication Critical patent/JPH07168869A/en
Application granted granted Critical
Publication of JP2580986B2 publication Critical patent/JP2580986B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は表面実装部品(SMD)
を搭載したプリント板の設計処理方式に関し、特に表面
実装部品を搭載するパッド(SMDパッド)と表面実装
部品リードの接続をX線検査するためにパッド下を配線
パターンが走行することなくプリント板配線処理を行な
う表面実装部品搭載プリント板の設計処理方式に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount device (SMD).
Design processing method of printed circuit board mounted with PCB, in particular, to perform X-ray inspection of the connection between the pad for mounting the surface mounted component (SMD pad) and the lead of the surface mounted component without the wiring pattern running under the pad for the printed circuit board wiring The present invention relates to a design processing method for a surface-mounted component mounting printed board to be processed.

【0002】[0002]

【従来の技術】表面実装部品を搭載するプリント板で
は、表面実装部品を搭載した後に基板上のパッドと表面
実装部品ピンの装着をX線を用いて検査している。
2. Description of the Related Art In a printed circuit board on which surface mount components are mounted, mounting of pads on the substrate and pins of the surface mount components is inspected using X-rays after mounting the surface mount components.

【0003】この検査において、パッド下に内層の配
線、ベタパターン等の内層パターンが存在するとX線の
透過力を低下させるので、プリント板の配線処理におい
てはパッド下の内層領域にはこのような内層パターンを
発生させない配線処理を必要としている。
In this inspection, if an inner layer pattern such as an inner layer wiring or a solid pattern exists under the pad, the X-ray transmission power is reduced. Wiring processing that does not generate an inner layer pattern is required.

【0004】従来、この処理は、配線処理の都度パッド
下を人間が認識、判断してパッド下の配線禁止領域を各
内層ごとに設定する手法がとられていた。
Heretofore, in this processing, a method has been adopted in which a human recognizes and judges under a pad each time wiring processing is performed, and sets a wiring prohibited area under the pad for each inner layer.

【0005】[0005]

【発明が解決しようとする課題】このように表面実装部
品のリードとパッドのX線による接続検査を行う目的で
パッド下の配線禁止領域を設定するのに、従来は人間の
認識、判断により行っていたのでその設定に多大な工数
がかかり更には設計ミスが容易に発生しやすいという問
題があった。
Conventionally, the setting of the wiring prohibited area under the pad for the purpose of inspecting the connection between the lead of the surface mount component and the pad by the X-ray is conventionally performed by human recognition and judgment. Therefore, there is a problem that the setting takes a lot of man-hours, and further, a design error easily occurs.

【0006】[0006]

【課題を解決するための手段】本発明の表面実装部品搭
載プリント板の設計処理方式は、プリント板の層数、層
名及び実装部品の部品名称、部品タイプ、ピン番号、パ
ッド形状等の層構成情報及び部品情報を含むプリント板
ライブラリと、プリント基板形状、実装部品の部品名、
配置座標、配置層名、ピン番号等の部品実装情報及び配
線情報を含むプリント板設計ファイルとを有し、当該プ
リント板ライブラリとプリント板設計ファイルとから対
象部品を抽出し、当該対象部品の有するパッド形状を所
定の幅だけ広げたパッド拡大形状を作成する配線禁止情
報生成手段と、前記対象部品を実装配置し、前記パッド
拡大形状を内層の全層に渡って展開し、当該パッド拡大
形状を配線禁止領域として各層に設定する表面実装部品
配置手段と、各層に設定された前記配線禁止領域を避け
て配線処理を行う配線処理手段とを有することを特徴と
する。
According to the present invention, there is provided a design processing method for a printed circuit board on which surface mounting components are mounted. The number of layers of the printed circuit board, the names of the layers and the component names of the mounted components, the component types, the pin numbers, the pad shapes, etc. Printed board library including configuration information and component information, printed circuit board shape, component names of mounted components,
A printed circuit board design file including component mounting information such as layout coordinates, layout layer names, and pin numbers, and wiring information; a target component is extracted from the printed board library and the printed board design file; Wiring prohibition information generating means for creating an enlarged pad shape by expanding the pad shape by a predetermined width; mounting and disposing the target component; developing the enlarged pad shape over all inner layers; It is characterized by having surface mounting component arranging means set on each layer as a wiring prohibited area and wiring processing means performing wiring processing avoiding the wiring prohibited area set on each layer.

【0007】[0007]

【実施例】次に図を用いて本発明を説明する。BRIEF DESCRIPTION OF THE DRAWINGS FIG.

【0008】図1は本発明に係る表面実装部品搭載プリ
ント板の設計処理方式の一実施例の構成を示すブロック
図でありプリント板設計に関する各種情報データを入出
力する入出力装置1、この入力したデータおよび設計中
の設計データを格納する記憶装置3、記憶装置3に格納
された各種データを用いて表面実装部品搭載プリント板
設計処理装置4を制御する中央演算処理装置2を示す。
表面実装部品搭載プリント板設計処理装置4は配線禁止
情報生成機構41、表面実装部品配置機構42、および
配線処理機構43からなる。
FIG. 1 is a block diagram showing the configuration of an embodiment of a design processing method for a printed circuit board on which surface mount components are mounted according to the present invention. The input / output device 1 inputs and outputs various information data relating to the design of the printed circuit board. 1 shows a storage device 3 for storing the data obtained and the design data being designed, and a central processing unit 2 for controlling a surface-mounted component-mounted printed board design processing device 4 using various data stored in the storage device 3.
The surface mount component mounted printed board design processing device 4 includes a wiring prohibition information generation mechanism 41, a surface mount component placement mechanism 42, and a wiring processing mechanism 43.

【0009】図2はプリント板の層数、層名等の層構成
情報やプリント板に搭載される表面実装部品を含む部品
の部品名、部品タイプ、ピン番号、パッド形状等の情報
を格納するプリント板ライブラリの構成例である。
FIG. 2 stores layer configuration information such as the number of layers and layer names of the printed circuit board, and information such as component names, component types, pin numbers, and pad shapes of components including surface mounted components mounted on the printed circuit board. It is a structural example of a printed board library.

【0010】図3は同じくプリント板に搭載される表面
実装部品を含む部品の部品名、配置座標、配置層名、ピ
ン番号等の実装情報、配線情報およびプリント基板形状
などの設計情報を表現するプリント板設計ファイルの構
成例である。
FIG. 3 also shows mounting information such as component names, layout coordinates, layout layer names, and pin numbers of components including surface mounting components mounted on a printed circuit board, wiring information, and design information such as the shape of a printed circuit board. It is a structural example of a printed board design file.

【0011】図4は表面実装部品搭載プリント板設計処
理装置の動作を示すフローチャートであり図1〜図4を
用いてその動作を説明する。
FIG. 4 is a flowchart showing the operation of the printed circuit board design processing apparatus mounted with surface mount components. The operation will be described with reference to FIGS.

【0012】入出力装置1から入力されたプリント板の
各種データと部品データは中央演算処理装置2により記
憶装置3に図2および図3の構成で格納される。
Various data and component data of the printed board input from the input / output device 1 are stored in the storage device 3 by the central processing unit 2 in the configuration shown in FIGS.

【0013】まず配線禁止情報生成機構41の動作を説
明する。
First, the operation of the wiring prohibition information generating mechanism 41 will be described.

【0014】記憶装置3に格納された図2に示すプリン
ト板ライブラリから層構成情報を入力する(S1)。
The layer configuration information is input from the printed board library shown in FIG. 2 stored in the storage device 3 (S1).

【0015】次に同様に図3に示すプリント板設計ファ
イルから搭載部品データを抽出する(S2)。
Next, similarly, mounted component data is extracted from the printed board design file shown in FIG. 3 (S2).

【0016】搭載部品名称からプリント板ライブラリの
部品名称を探しその部品タイプを抽出する。
A component name of the printed board library is searched for from the mounted component name and its component type is extracted.

【0017】この部品タイプから搭載部品が表面実装部
品か否かを識別する(S3,S4)。
From this component type, it is determined whether or not the mounted component is a surface mounted component (S3, S4).

【0018】表面実装部品である場合はプリント板ライ
ブラリから当該部品ピンのパッド形状を入力する(S
5)。次にこのパッド形状を所定の幅だけ広げた領域を
作成する(S6)。
If the component is a surface mount component, the pad shape of the component pin is input from the printed board library (S
5). Next, an area in which the pad shape is expanded by a predetermined width is created (S6).

【0019】この領域をこれに続く処理で用いる配線禁
止領域として設定しておく。
This area is set as a wiring prohibited area to be used in subsequent processing.

【0020】以上が配線禁止情報生成機構41の動作で
ある。
The above is the operation of the wiring prohibition information generating mechanism 41.

【0021】次に、表面実装部品配置機構42の動作に
ついて説明する。
Next, the operation of the surface mount component placement mechanism 42 will be described.

【0022】ここでは部品をプリント板上に搭載する配
置座標を決定する。配置する部品が表面実装部品以外の
場合は所定の位置座標上に配置する(S10)。
Here, the arrangement coordinates for mounting the component on the printed board are determined. If the component to be arranged is not a surface-mounted component, it is arranged on predetermined position coordinates (S10).

【0023】一方、表面実装部品である場合は部品の配
置座標から全ピン(パッド)について前記配線禁止領域
形状を全層に渡り展開する(S8)。
On the other hand, if the component is a surface mount component, the above-described wiring prohibited area shape is developed for all pins (pads) over all layers from the arrangement coordinates of the component (S8).

【0024】更に、この領域を各層における配線禁止領
域として説明する(S9)。
Further, this area will be described as a wiring prohibited area in each layer (S9).

【0025】まだ搭載部品があるか否かを判断する(S
11)。
It is determined whether or not there are still components to be mounted (S
11).

【0026】まだ搭載すべき部品がある場合は、ひき続
きプリント板設計ファイルから搭載部品を抽出する(S
2)動作からを繰り返す。
If there is still a component to be mounted, the component to be mounted is subsequently extracted from the printed board design file (S
2) Repeat from the operation.

【0027】部品が無い場合は配線処理に移る。If there is no component, the process proceeds to wiring processing.

【0028】ここでは上記で設定された配線禁止領域を
配線パターンを走行させずに配線処理を行う(S1
2)。
Here, the wiring processing is performed without running the wiring pattern in the wiring prohibited area set above (S1).
2).

【0029】さて、本発明の表面実装部品搭載プリント
板の設計処理方式により得られた配線禁止領域例を図5
に示す。
FIG. 5 shows an example of the wiring prohibited area obtained by the design processing method of the printed circuit board on which the surface mount components are mounted according to the present invention.
Shown in

【0030】4層構造のプリント板5の上に配置された
表面実装部品6のリードピン7はパッド8にてプリント
板に接続される。
The lead pins 7 of the surface mount component 6 arranged on the four-layered printed board 5 are connected to the printed board by pads 8.

【0031】内層の全層に渡って当該パッド8の形状を
拡大した配線禁止領域81〜83が展開される。
The wiring prohibited areas 81 to 83 in which the shape of the pad 8 is enlarged are developed over all the inner layers.

【0032】[0032]

【発明の効果】以上説明したように、本発明に係る表面
実装部品搭載プリント板の設計処理方式は表面実装部品
のパッド形状とプリント板の層構成情報および表面実装
部品の配置座標から自動的にパッド下の配線禁止領域を
全層に渡り生成することができるので、パッド下の配線
禁止領域の設定が容易に行うことができ、さらに設計ミ
スをなくすことができるという効果を有する。
As described above, the surface mount component mounting printed board design processing method according to the present invention is automatically performed based on the pad shape of the surface mount component, the layer configuration information of the printed board, and the arrangement coordinates of the surface mount component. Since the wiring prohibited area under the pad can be generated in all layers, the wiring prohibited area under the pad can be easily set, and the design error can be eliminated.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の表面実装部品搭載プリント板の設計処
理方式の一実施例の構成を示すブロック図。
FIG. 1 is a block diagram showing the configuration of an embodiment of a design processing method for a printed board on which surface-mounted components are mounted according to the present invention.

【図2】プリント板ライブラリの構成例を示す図。FIG. 2 is a diagram illustrating a configuration example of a printed board library.

【図3】プリント板設計ファイルの構成例を示す図。FIG. 3 is a diagram showing a configuration example of a printed board design file.

【図4】本発明の表面実装部品搭載プリント板の設計処
理方式の動作を示すフロー図。
FIG. 4 is a flowchart showing the operation of the design processing method for a surface-mounted component-mounted printed board according to the present invention.

【図5】多層構造プリント板に設定された、表面実装部
品のパッド形状を拡大した配線禁止領域を表わす斜視
図。
FIG. 5 is a perspective view showing a wiring prohibition region in which a pad shape of a surface mount component is set on a multilayer structure printed circuit board;

【符号の説明】[Explanation of symbols]

1 入出力装置 2 記憶装置 3 中央演算処理装置 4 表面実装部品搭載プリント板設計処理装置 41 配線禁止情報生成機構 42 表面実装部品配置機構 43 配線処理機構 S1〜S12 本発明の動作フロー 5 多層構造プリント板 6 表面実装部品 7 リードピン 8 パッド 81〜83 内層に展開された配線禁止領域 REFERENCE SIGNS LIST 1 input / output device 2 storage device 3 central processing unit 4 surface mounted component mounted printed board design processing device 41 wiring prohibition information generating mechanism 42 surface mounting component placement mechanism 43 wiring processing mechanism S1 to S12 Operation flow of the present invention 5 multilayer structure printing Board 6 Surface mount component 7 Lead pin 8 Pad 81 to 83 Wiring forbidden area developed in inner layer

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 多層構造のプリント板に実装する表面実
装部品のパッド形状を当該プリント板の全層に渡って配
線禁止領域として設定してから配線処理する表面実装部
品搭載プリント板の設計処理方式において、 前記プリント板の層数、層名及び実装部品の部品名称、
部品タイプ、ピン番号、パッド形状等の層構成情報及び
部品情報を含むプリント板ライブラリと、 プリント基板形状、前記実装部品の部品名、配置座標、
配置層名、ピン番号等の部品実装情報及び配線情報を含
むプリント板設計ファイルとを有し、 前記プリント板ライブラリと前記プリント板設計ファイ
ルとから対象部品を抽出し、当該対象部品の有するパッ
ド形状を所定の幅だけ広げたパッド拡大形状を作成する
配線禁止情報生成手段と、 前記対象部品を実装配置し、前記パッド拡大形状を内層
の全層に渡って展開し、当該パッド拡大形状を配線禁止
領域として各層に設定する表面実装部品配置手段と、 各層に設定された前記配線禁止領域を避けて配線処理を
行う配線処理手段とを有することを特徴とする表面実装
部品搭載プリント板の設計処理方式。
1. A design processing method for a surface-mounted component-mounted printed board in which a pad shape of a surface-mounted component mounted on a multilayer-structured printed board is set as a wiring-prohibited area over all layers of the printed board, and then wiring is performed. In the number of layers of the printed board, the layer name and the component name of the mounted component,
A printed board library including layer configuration information such as component types, pin numbers, pad shapes and component information, a printed board shape, component names of the mounted components, arrangement coordinates,
A printed circuit board design file including component mounting information such as an arrangement layer name and a pin number and wiring information; extracting a target component from the printed board library and the printed circuit board design file; and forming a pad shape of the target component. Wiring prohibition information generating means for creating a pad enlarged shape by expanding the pad by a predetermined width, mounting and arranging the target component, expanding the pad enlarged shape over all the inner layers, and prohibiting wiring of the pad enlarged shape A surface mounting component placement means for setting each area as an area, and a wiring processing means for performing wiring processing while avoiding the wiring prohibited area set for each layer, a design processing method for a surface mounting component mounting printed board, .
JP5313359A 1993-12-14 1993-12-14 Design processing method for printed circuit boards with surface mount components Expired - Lifetime JP2580986B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5313359A JP2580986B2 (en) 1993-12-14 1993-12-14 Design processing method for printed circuit boards with surface mount components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5313359A JP2580986B2 (en) 1993-12-14 1993-12-14 Design processing method for printed circuit boards with surface mount components

Publications (2)

Publication Number Publication Date
JPH07168869A JPH07168869A (en) 1995-07-04
JP2580986B2 true JP2580986B2 (en) 1997-02-12

Family

ID=18040313

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5313359A Expired - Lifetime JP2580986B2 (en) 1993-12-14 1993-12-14 Design processing method for printed circuit boards with surface mount components

Country Status (1)

Country Link
JP (1) JP2580986B2 (en)

Also Published As

Publication number Publication date
JPH07168869A (en) 1995-07-04

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