JPH03109749A - Testing method for integrated circuit device - Google Patents

Abstract

PURPOSE:To enable an array pitch of an output terminal to be reduced by using a probe for testing which is equipped with a common contactor and by performing test based on a signal value which is taken out of the common contactor while an input signal corresponding to the test details is given to an input terminal through the individual contactor. CONSTITUTION:In performing a test, a testing probe 30 is moved onto each chip 10 to be tested in sequence, is pushed to the chip 10 with a specified pressure after positioning, and an individual contactor 31 is connected to an input terminal 13 and a common contactor 32 is connected to an output terminal 14. In this state, voltage and input signal corresponding to the details and items of test are given to the input terminal 13 through the individual contactor 31 and a collective output signal of a plurality of output circuits 12 is taken out of each common contactor 32. In this case, since a plurality of output terminals 14 can be tested by means of the common contactor 32 while they are short- circuited, this situation is equivalent to multiple array pitches of the output terminal in terms of test, thus reducing the array pitch of the output terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for testing an integrated circuit device in which a large number of output circuits of the same configuration are incorporated, such as those for driving printing elements of a printer or pixels of a display panel.

[Conventional technology]

Recently, there has been an increase in the number of applications in which integrated circuit devices are used to directly drive external loads, and in particular when driving the above-mentioned printing elements and pixels, recent advances have been made so that a single integrated circuit device can drive a large number of these loads. Using highly integrated technology, at least several dozen output circuits with the same configuration are incorporated together with a common input circuit. During mass production of such integrated circuit devices, it is of course necessary to conduct tests to determine pass/fail.
As is well known, this test is usually performed on the wafer before it is isolated into chips using automatic test equipment.

In this automatic test, it is necessary to sequentially connect each integrated circuit device within the wafer to a test apparatus, and a test probe is used for this purpose. This probe is equipped with a large number of contacts, usually needles, which can be connected to the test equipment by bringing their tips into contact with input/output terminals such as connection pads or bump electrodes of each integrated circuit device. FIG. 2 shows such a connection state.

An input circuit 11 and a number of output circuits 12 are built into the rectangular integrated circuit device chip 10 shown in the center of FIG. For example, in the case of driving a printing element of a printer, print data is sent from the input terminal 13 to a shift register in the input circuit 11 as an input signal. The output of each stage of this shift register controls the output state of the corresponding output circuit 12. Each output circuit 1
Output terminals 14 for driving a load are provided corresponding to the output terminals 2 and are generally arranged along the two long sides of the chip 10.

The test probe 30 is equipped with a large number of contacts 31 which are needles corresponding to the input/output terminals 13 and 14 of the chip 10, and the contact state of the tips of these needles with the input/output terminals can be easily confirmed from above the figure. The window 34 is opened. Each contactor 31 is connected to a test device via a connection portion (not shown) of the test probe 30, and is sequentially moved in the vertical and horizontal directions in the figure after the test of one integrated circuit chip 10 is completed.

FIG. 3 is an enlarged sectional view of the contact portion of the contact 31 that connects with the input/output terminal. FIG. 2(a) shows a case where the terminal is a bump electrode, and the semiconductor region 1 of the silicon substrate of the chip 10, etc.
A bump electrode is provided so as to be connected to the end of the wiring 113 made of aluminum or the like disposed on the oxide film 2 covering the surface of the oxide film 2. As is usual, a window is opened in the protective film 4 made of silicon nitride or the like. A metal electrode made of gold or the like for a bump electrode 6 is provided protruding inside the portion through a base metal film 5, and the tip of the contactor 31 is brought into contact with the top surface of the bump electrode 6 as shown in the figure. Same figure (
(g))) indicates the case where the input/output terminal is a connection pad, and in this case, the wiring &1I exposed in the window opened in protection 1II4.
A connection pad 7 is formed by the end of WA3, and the contact 3
1 is brought into contact with this connection pad 7.

In addition, a highly elastic tungsten wire or the like is used for the needle of the contactor 31 (!), and its tip is plated with gold or the like to ensure a good connection between the input and output terminals. The test probe 30 is used with a predetermined pressure applied to it so that it bends slightly with its tip in contact with the terminal.

[Invention tries to solve it! I! ! [Problem] However, with recent advances in high-integration technology, it has become possible to incorporate a large number of output circuits into a small semiconductor chip, and the number of output terminals increases accordingly. It has become impossible to line up the contacts, and there is a problem in testing that limits high integration.

In other words, with recent advances in integrated circuit technology, it is possible to easily integrate more than 100 output circuits in a small chip of several squares, and the number of bumps and connection pads for input/output terminals can be reduced to 30.
They can be miniaturized to a size of approximately μ and arranged at a narrow pitch of approximately 50 nm. However, the contact needle needs to have a minimum strength to apply sufficient contact pressure with the terminal, and its tip can be narrowed to about 20 to 30 pm, but even if high elastic material is used, At the base, about 10 times that amount, 200-3
It is necessary to have a thickness of 00n. For this reason, even if the contacts are arranged three-dimensionally instead of in a single row as shown in FIG. 2, it is difficult to reduce the pitch between the tips to about 100 nm or less.

In view of the current situation where high integration is restricted by the pitch of the contactor arrangement on a test probe as described in the second point, an object of the present invention is to obtain a method for testing an integrated circuit device that is not subject to such restrictions.

[! Means to solve problem I]

This purpose is, according to the present invention, for testing an integrated circuit device in which a large number of output circuits and a common input circuit are incorporated, and is provided with an output terminal for each output circuit, an input terminal for an input circuit, and an input terminal for a power supply. , using a test probe equipped with an individual contact that contacts each input terminal individually and a common contact formed by shorting together multiple protrusions that contact each output terminal, and test the input terminal via the individual contact. This is accomplished by testing based on signal values taken out via a common contact that contacts a plurality of output terminals while applying a voltage or signal value depending on the content.

Note that needles can be used as usual for the individual contacts in the above configuration, and it is advantageous to use a common contact that has protrusions and short circuits formed by photo-etching a metal film. .

[Effect]

In the case where a large number of output circuits incorporated in an integrated circuit device to be tested have the same configuration, it is not necessarily necessary to test them individually (although it is not necessary to test multiple output circuits together). This design focuses on the ability to judge pass/fail, and as described in the above configuration, for the output circuit, by using a common contactor made by short-circuiting multiple protrusions that contact the output terminals, the output terminals can be determined. This makes it possible to perform tests even when the test pieces are arranged at a narrow pitch, and also to shorten the test time.

However, when testing multiple output circuits at once like this, the input signals to the input circuits and the power supply voltage to the output circuits must not be given particularly accurately and must be able to be precisely controlled. As mentioned in the configuration, individual contacts that make individual contact with the input terminals are used. Under such accurate input conditions, pass/fail judgment can be made with the degree of accuracy required for mass production from the analog values of the voltage and current signals obtained from the short-circuited output terminals.

The number of output circuits that are tested together in the method of the present invention, that is, the number of output terminals that are short-circuited by a common contact, is selected depending on the required test accuracy, but in practice it is, for example, several to 10. It is reasonable to set it at a certain level. As a result, it is possible to determine the pass/fail of so-called DC characteristics and AC characteristics stipulated in normal standards and commercial tests with sufficient accuracy, and when arranging common contacts on test probes, the arrangement pitch of output terminals can be increased by several to ten times. Therefore, the arrangement pitch of the output terminals can be significantly reduced.

〔Example〕

Embodiments of the present invention will be specifically described below with reference to FIG. FIG. 1(a) is a top view of a state in which a test probe 30 is superimposed on one integrated circuit device chip 10 in a wafer 20. is shown with part of it cut away. FIG. 1B is an enlarged sectional view of the common contact 32 in FIG. Portions in these figures corresponding to those in FIG. 2 described above are given the same reference numerals.

The integrated circuit device chip 10 shown in FIG. 1(a) has a common input circuit 11. A plurality of output circuits 12, input terminals 13 arranged along their short sides. The output terminals 14 arranged along the two long sides are incorporated in this as in the conventional case of FIG. 2, but the output terminals 12 and the corresponding output The difference is that the number of built-in terminals 14 is 100 or more, which is more than twice that of the conventional one.As usual, this chip 10 is mounted on a wafer 20.
A large number of them are arranged side by side in the top, bottom, left and right directions of the figure.

In this embodiment, the size of the output terminal 14 is, for example, 20~
The size is 30n square, and the arrangement pitch is about 30 to 50p. As can be easily understood, the number of input terminals 13 remains the same as before regardless of the number of output circuits, and the size of the input terminals 13 is 100n square or more as before, and the arrangement pitch is 150μ.
This is considered to be the above. Note that these input terminals 1 in the present invention
3 includes a power supply terminal for input signals to the input circuit 11, and the input/output terminal 1 in this embodiment
Assume that bump electrodes 3 and 14 are used.

The test probe 30 is in the form of a printed wiring board, which is attached to a moving and positioning mechanism of an automatic test device (not shown) via its support portion 30a, as in the conventional case.
Individual contact 31° for input terminal 13 Common contact 32 for output terminal 14. and a connecting conductor 33 for connection to automatic test equipment, and a window 34 similar to the conventional one but with a slightly different shape is provided in the center so that the chip 1O can be easily confirmed from above the figure.

Highly elastic needles made of tungsten or the like are used as the individual contacts 31 as in the past, and their bases are fixed to the test probe 30 and connected to the corresponding connection conductors 33. The tips of the input terminals 13 and the input terminals 13 are arranged at the same pitch. The procedure for bringing the tip of the needle into contact with the input terminal 13 is the same as that shown in FIG. 3. The common contact 32 is connected to the six output terminals 1 in this embodiment.
Correspondingly, six protrusions 32a each having a circular cross section in this example are provided, and each protrusion 32a is connected to a corresponding connection conductor 33.

FIG. 1(b) shows an example of the structure of this common contact 32 and its contact state with the output terminal 14. The common contact 32 in this embodiment is made of a flexible film 41 made of an insulating material such as plastic. By performing photo-etching twice on a very thin metal sheet made of copper or the like bonded to the protrusions 32a, in this example, six protrusions 32a and the short-circuit portion 3 that short-circuits them are formed.
2b, the size and height of each protrusion 32a are, for example, about 10 to 2 On, and the short circuit part 32a is
The thickness is also about 10 to 20 IIN. It is desirable that the common contact 32 is entirely plated with gold.

The common contactor 32 carried by this flexible film 41 is fixed to a printed wiring board or the like that is the main body 43 of the test probe 30 via a soft rubber elastic body 42 such as silicone rubber. Of course, the protrusions 32a are arranged at the same arrangement pitch as the output terminals 14, and when the test probe 30 is pressed against the chip 10 with a predetermined pressure, the flexible film 41 and the rubber elastic body 42 are deformed appropriately to protrude. A uniform conductive contact is obtained between 32a and output terminal 14.

During the test, the test probe 30 is first placed on the wafer 20.
The probe is placed on a specific chip 1G in the test device, and the probe is accurately positioned while confirming the position through the window 34, and then the automatic test equipment is started to operate. During automatic testing, as is customary, the test probe 30 is sequentially moved over each chip 10 to be tested and, after being accurately positioned, is pressed against the chip 10 with a predetermined pressure.

As a result, the individual contacts 31 and the common contacts 32 are connected to the input terminal 13 and the output terminal 14, respectively.

In this state, apply a voltage and input signal to the input terminal 13 via the individual contactor 31 according to the content or item of the test,
In the method of the present invention, the combined output signals of a plurality of output circuits 12 are taken out from each common contactor 32, and the quality of the characteristics corresponding to the test content is automatically determined from the analog signal value thereof.

Note that depending on the content of the test, especially the test items of DC characteristics, a predetermined voltage or current is also applied from the common contactor 31 side to the output terminal 14, and in response, a signal indicating the current or voltage taken by the output circuit 12 is the same common signal. It may also be taken out from the contactor 31.

Furthermore, even when a digital input signal is given from the individual contactor 31 side for AC characteristics or digital operation testing, in the method of the present invention, the analog value of the signal obtained from the common contactor 31 side has meaning, and the analog value of the signal obtained from the common contactor 31 side is meaningful. The number of output terminals 14 to be short-circuited by the common contactor 31 is selected so as to obtain the test accuracy necessary for pass/fail determination. By appropriately selecting the number of shorted output terminals, the method of the present invention can accurately determine the pass/fail of test items stipulated in normal standards and commercial tests that must be performed during mass production of integrated circuit devices with sufficient accuracy. .

〔Effect of the invention〕

As explained above, the method of the present invention uses a test probe equipped with a common contact formed by short-circuiting a plurality of individual contacts that individually contact each input terminal and a plurality of protrusions that contact each output terminal. The following effects can be achieved by conducting a test based on the signal value taken out from the common contact while giving an input signal corresponding to the test content through the individual contact.

(a) Even when the number of output terminals of an integrated circuit device is large and arranged at narrow pitches that cannot be tested using conventional methods, testing can be performed with multiple output terminals short-circuited using a common contact. According to tests, this is equivalent to increasing the arrangement pitch of the output terminals by several times or more, and by utilizing this, it is possible to reduce the arrangement pitch of the output terminals of the integrated circuit device to a fraction of that of the conventional method.

(b) Although the method of the present invention requires automatic test equipment to have the precision to accurately evaluate the analog value of the signal taken from the common contact, it is possible to simultaneously process signals from multiple output terminals, so It is possible to reduce the time required for testing and improve the efficiency of determining whether the integrated circuit device chip is good or bad.

As described above, the method of the present invention solves the problem of conventionally restricting the high integration of integrated circuit devices due to the contact array pitch on the test probe, and makes it possible to utilize high integration technology without such restrictions. It is possible to improve the efficiency of pass/fail judgment tests.

[Brief explanation of drawings]

FIG. 1 is a top view of a test probe placed on a wafer and an enlarged sectional view of a common contact portion, showing an embodiment of the integrated circuit device testing method according to the present invention. Figure 2 and subsequent figures relate to the prior art; Figure 2 is a top view of the contactor of the test probe in contact with the input/output terminal of the integrated circuit device chip, and Figure 3 is the contact of the contactor with the input/output terminal. It is an enlarged sectional view showing a state. In these figures, l: semiconductor region where the integrated circuit is built, 2 dioxide film, 3:
Wiring film, 4: Protective film, 5: Base metal film, 6: Metal for bump electrode, 7: Connection pad, chip for 10i integrated circuit device, 11: Input circuit, 12+Output circuit, 13: Input terminal,
14: Output terminal, 20: Wafer, 30: Test probe, 3Ga: Test probe support, 31: Individual contactor or needle, 32: Common contact, 32a: Protrusion of common contact, 32b: Common contact 33: Connection conductor, 34: Window, 41: Flexible film, 42: Rubber elastic body, 43: Test blow Figure 2 Figure 3

Claims (1)

[Claims] A wafer state before isolation into chips of an integrated circuit device in which a large number of output circuits and common input circuits are incorporated, and which includes an output terminal for each output circuit, and an input terminal for the input circuit and the power supply of the output circuit. This method uses a test probe equipped with a common contact made by shorting together individual contacts that contact each input terminal and a plurality of protrusions that contact each output terminal. An integrated circuit characterized in that a test is performed based on a signal value taken out through a common contact that contacts a plurality of output terminals while applying a voltage or signal value according to the test content through individual contacts. Test method for circuit devices.