JPH03108871A - Picture forming device - Google Patents

Abstract

PURPOSE:To simplify the constitution and to improve the print speed by giving a switching signal to 1st and 2nd switching elements for each block of a print data generated from a data generating source so as to switch the storage order to the memory elements alternately for each block. CONSTITUTION:A print data from a data generating source is stored in plural memory elements F1-F64 in forward and reverse directions by one block each with the operation of 1st switching elements 77-82 and 2nd switching elements 83-88. The storage output of the memory elements is given to one terminal of a print element to decide a predetermined level and a level of common signal lines VK1-VK40 of a relevant block is decided to the other level. Thus, each print element is energized based on a print data sequentially along with the arrangement direction. Thus, the constitution is simplified in comparison with a conventional device, the rearrangement of the print data is not required and the print speed is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image forming apparatus that can be implemented in connection with, for example, a light emitting diode (abbreviated as LED) head and a thermal head.

2. Description of the Related Art A conventional light emitting diode head has a plurality of blocks each consisting of a plurality of light emitting diodes arranged in a row, and one terminal of a printing element located at a symmetrical position in each adjacent block receives an individual signal. The individual signal lines are bent in a zigzag shape, and the other terminals of the light emitting diodes are connected to the common signal line for each block, thus forming a so-called dynamic drive matrix wiring pattern. A driving means is provided at one end in the arrangement direction of the blocks, and sequentially selects common signal lines in the blocks, and sequentially supplies power to the light emitting diodes distributed in the selected blocks via individual signal lines. supply This driving means includes
Print data to be recorded individually corresponding to each light emitting diode is given to the block, that is, from one end to the other end in the arrangement direction of the light emitting diodes, and the driving means selectively drives the light emitting diodes as described above. Drive.

Problems to be Solved by the Invention In such prior art, printing data sequentially given to each printing pixel element along the arrangement direction must be alternately reversed for each block and led to individual signal lines. Otherwise, it is impossible to drive each printing pixel element sequentially in accordance with the image data along the arrangement direction.The driving means must rearrange the given image data for each block. Image data is once stored in a memory for each block, and the image data stored in this memory is addressed in the forward or reverse direction and is led out to individual signal lines.

Therefore, in the prior art, it is necessary to prepare a memory for sorting the print data, which makes the configuration complicated and expensive, and requires a relatively long time to sort the print data. Therefore, there is a limit to increasing the printing speed.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image forming apparatus that eliminates the need to rearrange print data for print elements such as light emitting diodes, thereby simplifying the configuration and improving printing speed. That's true.

Means for Solving the Problems In the present invention, a plurality of printing pixels are arranged in a line and divided into a plurality of blocks, and one terminal of the printing pixels located at symmetrical positions in each adjacent block is connected to an individual signal line. A printing means is connected to the printing means, and the other terminal of the printing element is connected to a common signal line for each block, and a printing means is provided individually corresponding to each of the plurality of printing elements included in one block, and the store output is connected to the printing element. a plurality of memory elements for applying a predetermined one potential to the one terminal; and a data generation source for sequentially outputting printing data to be applied to each printing element of the printing means in the order in which the printing elements are arranged. , the output of the memory element in the previous stage is applied to the input of the memory element in the next stage, and the input of the memory element in the first stage is connected to a first switching element which supplies printing data from a data source, and the output of the memory element in the latter stage is applied to the input of the memory element in the next stage. , to the input of the memory element in the previous stage, and to the input of the memory element in the final stage, the second switching element supplies the print data from the data generation source to the input of the memory element in the last stage; means for sequentially setting the common signal line of corresponding blocks to the other predetermined potential;
and a switching signal generation source applied to the second switch printing element to alternately switch the order of storing into the memory elements for each block, thereby energizing the printing elements in the order of arrangement. It is a device.

The present invention also provides a latch circuit interposed between the memory element and the printing element, which latches the output of the memory element and applies it to the one terminal of the printing element, and a store output of the latch circuit to the printing element. and means for supplying print data of the next block to be printed to the memory element during this period.

According to the present invention, the individual signal lines to which one terminals of printing elements such as light emitting diodes or heating resistors of thermal heads are connected at symmetrical positions in adjacent blocks are bent in a zigzag manner. The printing data to be given to each printing pixel element is sequentially output from the data generation source, and the printing data from this data generation source is 1
For each block, one block is stored in the memory element in the forward and reverse directions by the action of the plurality of memory elements, the first switching element, and the second switching element. By applying the store output of the memory element to one terminal of the printing element to set it to one predetermined potential, and setting the common signal line of the block corresponding to that one block of print data to the other predetermined potential in block order. , each printing pixel element sequentially along its arrangement direction,
Power can be activated based on print data.

Therefore, as described in connection with the prior art, the configuration is simplified compared to the configuration in which printing data is once stored and addressing is alternately performed in blocks sequentially in the forward and reverse directions to read it. Furthermore, since there is no need to rearrange the printing data, the printing speed can be improved.

Embodiment FIG. 1 is an overall block diagram of an embodiment of the present invention. This image forming bag: is a light emitting diode lpl~lρ64;...;40p1~40 included in the printing means 70.
The p64 is sequentially dynamically driven block by block in the order of its arrangement from the left to the right in FIG. The photoreceptor, which is conveyed in the vertical direction in the figure, is exposed to light to form an image.

FIG. 2 is a simplified plan view of this printing means 70.
~40P64 constitute one block for each total of 64 light emitting diodes, and these blocks are indicated by reference numbers A1 to A40.

FIG. 3 is a simplified plan view of this printing means 70. Common signal lines VK1 to VK40, which are electrodes, are formed for each block A1 to A40.

FIG. 4 is a perspective view of a part of this printing means 70, and FIG.
The figure is a cross-sectional view taken along the section line ■--■ in FIG. 2. The substrate 21 is made of an electrically insulating material such as ceramic or glass, and the individual signal lines 11 to 164 are formed on its surface in a zigzag or crank shape. These individual signal lines 11 to 164 are connected to one of light emitting diodes, such as lpl, 2p64, which are located symmetrically to the left and right in FIG. Light emitting diode ip2.2p6 with terminals connected and in its symmetrical position
One terminal of 3 is connected respectively.

On the board 21, individual signal lines! 1 to 164 are partially formed with electrical insulation 7128, and common signal lines VKI to VK40 are formed thereon. These common signal lines VK1 to VK40 are connected to each block A1-
Light emitting diode IP1 to IP64 for each A40;...4
The other terminals of 0P1 to 40P64 are commonly connected.

As clearly shown in FIG.
2 and the individual signal line 12 are mutually connected by a bonding wire 33. The other light emitting diodes have similar configurations.

The common electrodes VKI to VK40 are individually electrically connected to a conductor 34 formed on one surface of the flexible film 36.

Referring again to FIG. 1, the driving means DR for driving the printing means 70 is provided on the substrate 21, and based on the sequential printing data output from the processing circuit 73, the driving means DR Each light emitting diode IP1~ of the printing means 70
IP64; . . . 40P1 to 40P64 are sequentially driven block by block from left to right in FIG. 1 in the arrangement direction.

The driving means DR is provided with D-type flip-flops F1 to F64, which are memory elements that individually correspond to the light emitting diodes of each block A1 to A40. Processing circuit 73
The printing data DA passing through the line 74 from the buffer 7
The signal is applied from the first switching element 77 to the input terminal of the first stage 7 lip-flop F64 via a line 76. The output Q of the flip-flop F64 further passes through the first switching element 78 to the next stage flip-flop F6.
The first switching elements 79 to 82 are provided in the same manner.

Further, the printing data via the line 76 is given to the input of the final stage flip-flop F1 via the second switching element 83, and the output Q of this final stage flip-flop F1 is
is applied to the input of the memory element F2 at the previous stage via the second switching element 84, and second switching elements 85 to 88 are provided in the same manner.

The outputs of the flip-flops F1 to F64 are respectively applied to the inputs of the D-type flip-flops F1 to L64 included in the latch circuit 89. These flip-flops 1 to L64 are each flip-flop of the latch circuit 89 that performs a latch operation when the latch signal LA applied from the processing circuit 73 to the line 9o is applied from the inverting circuit 91 via the line 92. The outputs of 1 to L64 are respectively given to one input of AND gates 01 to G64, and the outputs of these AND gates G1 to G64 are given to current sources PW1 to PW64.

Current sources PWI to PW64 are connected to individual signal lines 11 to 164
A current is supplied with one potential at one side, and power for driving the light emitting diode is thus supplied.

The AND gate 94 receives an activation signal E from the processing circuit 73.
NB is provided via line 95 and inverting circuit 96;
The AND gate 94 is also supplied with a signal EO, which becomes high level after the power is turned on, from the processing circuit 73 via a line 97. The output of AND gate 94 is provided on line 98 to the other inputs of AND gates G1-G64.

The switching signal generation source 100 is a JK flip-flop 10.
1, and its truth table is shown in Table 1.

Table 1 Here, the input terminal J of the flip-flop 101.

K is connected to a power supply and is always kept at a high level.

An enable signal ENB is applied to the clear input terminal CLR from a line 95 via an inversion circuit 102.

Furthermore, a latch signal LA is input to the clock input terminal CK. The output from the output terminal Q is applied as a switching signal from the buffer 103 to the first switching elements 77 to 82, respectively, via the line 104, and these first switching elements 77 to 82 receive a high level signal from the line 104. It becomes conductive when a low level signal is applied, and is cut off when a low level signal is applied. buffer 10
The switching signal from 3 is inverted by the inverting circuit 105, and is given to the second switching elements 83 to 88 as another inverted switching signal from line 106, and when the inverted switching signal on line 106 is at a high level, At some point, these second switching elements 83 to 8
8 is conductive and is cut off when it is at a low level.

The light emitting diodes of each block A1-A40 are connected to switches SW1-5 via common signal lines VKI-VK40.
W40 respectively, and these switches SWI~
5W40 is connected to ground potential, and the latch signal LA is applied to the block switching circuit 108 via line 107. This block switching circuit 108 responds to the latch signal LA and switches from lines C1 to C40 to switches SWI to 5W.
A block switching signal is applied to 40, thereby sequentially turning on the switches SWI to 5W40 of each block A1 to A40 one by one.

The operations of the printing means 70 and the driving means DR will be explained with reference to FIG. In order to start image formation, the processing circuit 7
3 gives a high level signal to line 97, and
The activation signal ENB is changed from a high level to a low level as shown in FIG. 6(1), and thereby the signal led out from the AND gate 94 to the line 98 goes to a high level, making it possible to start image formation. Also, switching signal generation source 1
00 flip-flop 101 passes through the inversion circuit 102 when the ENB signal is at high level, so it goes to low level and is cleared, and its output Q is held at high level.

When the ENB signal becomes low level, it is inverted by the inverting circuit,
Output Q is toggled by the clock. In this state, the flip-flop 101 is in a state where it can receive the latch signal LA at the clock input terminal CK. flip 1
The waveform of the output Q of the line 101, and therefore the waveform of the line 104, is shown in FIG.
2 remains conductive.

Therefore, the print data DA of the processing circuits 73 to 64 is
As shown in FIG. 3, the serial bits are sequentially led out to line 74 to become ready for transfer, and the clock signal CLK shown in FIG. Flip 7 operates in sync with
In 0tsu1F1 to F64, the data of the light emitting diode is
1 block, total 64 dots, flip-flop F
64 and is transferred to the flip-flop F1 from the left to the right in FIG. 1 and stored therein. After one block of printing data has been transferred in this way, the latch signal LA is applied from the processing circuit 73 as shown in FIG.
The print data of the flip-flops F1 to F64 are transferred in parallel to the flip-flops F64 and latched therein.

This latch signal LA is applied to the clock input terminal CK of the flip-flop 101 of the switching signal generation source 100, and the output Q switches from high level to low level at the falling edge of the latch circuit LA.

Therefore, the first switching elements 77 to 82 are cut off, the second switching elements 83 to 88 are made conductive, and the flip-flops F1 to F64 are switched to a state in which input can be made sequentially from the right to the left in FIG. Therefore, the block switching signal 108
responds to the latch signal LA and sends the block switching signal shown in FIG. 6(6) to the switch SWI via line C1.
, which causes the switch SWI to conduct during the period W1 when the line C1 is at a low level. In this way,
Light emitting diode 1P1 included in the first block A1
~IP64 is energized by the current from the current sources PWI~PW64 and lights up, and printing is performed. During the period W1 during which the switch SWI is conductive, the print data DA for the second block A2 of the processing circuit 73 is
is led out to the line 74, and the second switching elements 83 to
88, and stored in flip-flops F1 to F64 in this order. The print data of the light emitting diode 2P1 of this second block A2 is stored in the flip 70 knob F1, and the print data of the light emitting diode 2P64 is stored in the flip-flop F64.

Then, by generating the latch signal LA,
The block switching signal generating circuit 108 is connected to the sixth line C2.
A low level signal shown in FIG. 7 is derived to turn on the switch SW2, and the light emitting diodes 2P1 to 2P64 of the second block A2 are energized based on the output of the latch circuit 89.

In this way, the light emitting diode I of the first block A1
During the period when P1 to IP64 are energized, the print data of the light emitting diodes 2P1 to 2P64 of the second block A2 is stored in the flip-flops F1 to F64, and this operation is repeated to print data for all the blocks A1. ~A4
0 light emitting diodes are sequentially driven. FIG. 6(8) shows a signal applied to switch SW3 from line C3 for block A3 to make switch SW3 conductive.

The present invention can be implemented not only in connection with an image forming apparatus using light emitting diodes, but also in conjunction with an image forming apparatus using light emitting diodes.
The present invention can also be implemented in connection with an image forming apparatus equipped with a thermal head using a heating resistor, and the present invention can be implemented using printing elements having other structures.

Effects of the Invention As described above, according to the present invention, the configuration can be simplified and realized at low cost, and the printing speed can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a plan view showing a simplified structure of the printing means 70, FIG. 3 is a plan view showing a further simplified structure of the printing means 70, and FIG. 4 is a perspective view of a part of the printing means 70, FIG. 5 is a sectional view taken along the section line V--■ in FIG. 2, and FIG. 6 is a waveform diagram for explaining the operation. 71...Printing means, 73...Processing circuit, 77-82
... first switching element, 83-88 ... second switching, 89 ... latch circuit, 100 ... switching signal generation source, 101 ... JK flip-flop, 1
08...Block switching signal generation circuit, A1-A40
...Block, IPI~IP64;...;40P1
~40P64...Light emitting diode, 11~164...
- Individual signal lines, VKI to VK40... common signal lines, F1 to F64. Ll~L64...Flip-flop

Claims (2)

[Claims] (1) A plurality of printing pixels are arranged in a row and divided into a plurality of blocks, one terminal of each printing device located at a symmetrical position in each adjacent block is connected to an individual signal line, and the other terminal of the printing device is connected to an individual signal line. is provided individually corresponding to the printing means connected to the common signal line for each block and each of the plurality of printing pixels included in one block, and a store output is applied to the one terminal of the printing pixel element to predetermined. On the other hand, a plurality of memory elements for setting the potential, a data generation source that sequentially outputs printing data to be given to each printing element of the printing means in the order in which the printing elements are arranged, and an output of the previous stage memory element, A first switching element which supplies print data from a data source to an input of a memory element in the next stage, and a first switching element which supplies printing data from a data source to an input of a memory element in the first stage; and a second switching element that supplies printing data from the data generation source to the input of the final stage memory element, and a common signal line of the block corresponding to the printing data generated from the data generation source. means for sequentially setting the other potential to a predetermined potential;
and a switching signal generation source applied to the second switching element to alternately switch the order of storing into the memory elements for each block, thereby energizing the printing elements in the order in which they are arranged. Device. (2) A latch circuit interposed between the memory element and the printing element, which latches the output of the memory element and applies it to the one terminal of the printing element, and a period during which the store output of the latch circuit is applied to the printing element. 2. The image forming apparatus according to claim 1, further comprising means for supplying print data of a block to be printed next to a memory element.