JPS61234653A - Optical write head for led printer - Google Patents

Abstract

PURPOSE:To print out data with an LED printer at a high speed, by successively and continuously supplying voltages which are almost inversely proportional to the luminous luminance of each chip to the leading wires which are independently connected with common side electrodes of each chip constituting an LED array from a decoder. CONSTITUTION:Data of one line quantity stored in a buffer RAM 21 is read out by a readout address generator 20 and successively drive monolithic chips 21-2n containing 128 pieces of LEDs 2a of an LED array 1 through a driving circuit 3. Common side electrodes of each chip 21-2n are independently led out and successively made to '1' by a decoder 9. The time required for becoming '1' is controlled by the decoder 9, ROM 10, and counter 11 so that it can become inversely proportional to the luminous luminance of the LED of each chip. Similarly, the address generator 20 is also switched. When such an arrangement is made, deterioration of the LED of each chip can be prevented and, at the same time, high-speed printing out becomes possible.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to an optical writing head for an LED printer using electrophotography.

(Technical Background of the Invention) FIG. 7 shows a conventional optical writing head of this type. That is, this optical writing head comprises an LED array l, which includes chips 21 to 2n and 2', each including a plurality of, for example 128, LEDs 2a.
2'n (see FIG. 1O) are arranged in a negative row. These chips 21~2n
A drive circuit 3.3 is connected to the LEDs 2' and 2'n and 2a, respectively, by signal lines DO to DIff arranged in a matrix. These drive circuits 3 include a drive section 4 directly connected to the signal line D ow D +2r, a latch circuit 5 connected in parallel to this drive section 4, and further connected in parallel to this latch circuit 5. It consists of a shift register 6.

Meanwhile, reporters lunch 2. The common side electrodes of ~2n and 2'1 to 2'n are arranged in a matrix! It is connected to the leader lines COM l to COM n, respectively.

In the optical write head having such a structure, the shift register 6 of each drive circuit 3 manually inputs data serially transmitted from the host computer using a clock. The latch circuit 5 receives a latch signal from the shift register 6 when the shift register 6 takes in the data.
The drive section 4 is driven based on the data latched by inputting a timing signal. Since the drive section 4 is composed of, for example, a transistor array, the launch circuit 5 drives only predetermined transistors and supplies signal currents corresponding to the signal lines DO to D12γ. On the other hand, as shown in FIG. 8, the leader lines COM, ~C0Mn are connected to COM+, C0
A voltage of constant pulse width T is applied in the order of M2 and C0Mn. Therefore, each chip 2. ~2n LED2
A emits light in the order of lunch 25, chip 22, chip 23-1-chip 2n, and L of each chip 2' to 2'n.
ED2a has chip 2'4, chip 2'2, depth 2'
Since the light is emitted in the order of 3-1-lamp 2'n, as shown in FIG.
'n is formed corresponding to the chips 21 to 2n and 2'1 to 2'n.

By the way, Fig. 10 shows the monolithic additional ED chip 2.
(or 2') - example is shown, and the main body 2A has 12
Eight LEDs 2a (light emitting parts) are provided in the - column, and each LED
Signal lines Do-D and 27 are connected to D2a, respectively. The substrate of the chip 2 forms a common side electrode 2B.

Now, since such chips 2 have variations in manufacturing characteristics, the luminance of the LEDs differs even if the same current is supplied between the chips 2.

Therefore, as described in ``-'', when an LED array l is constructed from a plurality of chips 2I to 2n and 2'1 to 2'n, for example, the luminance of each LED 2a of the chip 21 and the luminance of each LED 2a of the chip 2'1 are The luminance will be different from the luminance.

□If the amount of light emitted from the LED/D2a differs between the chips 21 to 2n and 2'1 to 2'n, uneven exposure will occur on the photoreceptor 7, resulting in shading in the printed image, etc. Resulting in.

Therefore, conventionally, the transistor array constituting the drive section 4 of the drive circuit 3 is connected to each chip 21 to 2n and 2', to
The amount of current supplied was controlled in accordance with 2'n, and thereby the luminance of the LED 2a was corrected for each chip 21 to 2n and 2' to 2'n.

That is, for example, when the luminance of each LED 2a of the chip 21 is high, as shown in FIG. The luminance of the LED is 21 chips.
If l/2 of 2a is the smallest, each t'ED2
A was supplied with current at a current density of 1/2 for 1 hour. Also, for example, chip 2. and each LED 2a of the chip 22
When the luminance of the LEDs 2a of the chip 23 is large, as shown in FIG. 22) When LED 2 a (7), 1/2, was the smallest, a current was supplied to each LED 2 a for 1 hour at a current density of I×2.

In addition, conventionally, the LE of each chip was changed by changing the pulse width of the pulse voltage applied to the common side electrode of each chip.
It is also practiced to keep the amount of light emitted from Dza constant. That is, for example, chip 2. When the luminance of each LED 2a is high, as shown in FIG. 12 (A'), a pulse voltage of l/2 is applied to the common side electrode of the chip 22.
'o The luminance of each LED 2a is l/ that of the chip 21.
2, the Norms voltage of T was applied to each LED 2a. For example, if the luminance of each LED 2a of chips 2 and 22 is high, as shown in FIG.
When the luminance of each LED 2a of the chip 23 is 1/2 of that of the chip 21 (22) and is the smallest, a pulse voltage of T is applied to the common side electrode. .

(Problems with Background Art) Now, it is necessary to form an image on the photoreceptor 7-1 by exposing it to a predetermined amount of light. Therefore, in an LED printer, a predetermined amount of light is emitted from each LED 2a based on a chip having 44 LEDs with the lowest luminance.
The above-mentioned time T is set in relation to the current supply current so that However, conventionally, only the time T is secured for each chip, so the time TXn(
number of chips), and therefore, it takes a lot of time to print out.

By the way, the LED 2a of each chip used in an LED printer has a small light emitting area and needs to produce a sufficient amount of light in a short time, so it is necessary to supply a larger current than in normal usage to make it emit light with high brightness. ing. For this reason,
Each chip's LED deteriorates in a short period of time. In order to prevent this deterioration, the supply current can be reduced, but if the supply current is reduced, the above-mentioned time T must be increased in order to obtain a predetermined amount of light. It takes time.

(Object of the Invention) The object of the present invention is to create an LED that can be printed out at high speed without deteriorating the LED of each chip.
An object of the present invention is to provide an optical writing head for a D printer.

(Summary of the Invention) The present invention connects independent leader lines, not in a matrix, to the common side electrode of each chip constituting an LED array, and applies a voltage to each leader line via a decoder. At the same time, the decoder control means lowers the output voltage from the decoder in approximately inverse proportion to the luminance of the LED of the corresponding chip, and at the same time continuously decodes the common code corresponding to the next chip to be scanned. It is characterized by outputting to.

(Embodiments of the Invention) Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

The optical writing head of the LED printer according to the present invention has a first
As shown in the figure, an LED array l is provided. This L
The ED array 1 is formed by arranging monolithic tops 21 to 2n including 128 LEDs 2a in a line, and each chip 21 to 2n is connected to a respective common side electrode (Fig. 10). ) are electrically isolated. The LEDs 2a of each of these chips 21 to 2n are connected to signal lines Do to D, 2 which are wired in a matrix.
．． A drive circuit 3 is connected to the drive circuit 3 via. This drive circuit 3 includes a drive section 4 that is directly connected to the signal lines D O" and DI27, a latch circuit 5 that is connected in parallel to this drive section 4, and a latch circuit that is further connected in parallel to this latch circuit 5. The shift register 6 is connected to a shift register 6.Data is serially transmitted from a host computer (not shown) to the shift register 6.The latch circuit 5 is connected to the number of LEDs on one chip, that is, 12.
It is formed from eight clip-flops and latches the data in the shift register 6. The drive section 4 is formed from a transistor array, each transistor being connected to the output side of each free-flop forming the latch circuit 5.

Each chip 2. A plurality of lead wires COM I" COM n are each independently, that is, directly connected to each of the common side electrodes of C to 2n.
OM I" COM n are each connected in parallel to a decoder 9 via a buffer gate 8. ROM10 is connected to the input side of this decoder 9, and RO
A counter 11 is connected to M10. counter t
i counts clocks from a clock generator (not shown).

A read address generator 20 is connected to the output side of the ROM10, and a buffer RAM 21 for temporarily storing data from the host computer is connected to the output side of the read address generator 20. The output side of this buffer RAM 21 is connected to the shift register 6 of the drive circuit 3.

Further, a write address generator 22 is connected to this buffer RAM 21.

Next, the manner of use of the optical writing head according to the present invention will be explained.

First, when all data in one direction for making each LED 2a of the chips 21 to 2n emit light is serially transmitted from a host computer (not shown) to the buffer RAM 21, the buffer RAM 21 is connected to the write address generator 22 which operates on clock input. Since a write address is input from S, all data for this - line is stored in a predetermined position. −
When the transmission of the data for the row is completed, as will be described later, the read address generator 20 controls each LED 2 of the chip 2° according to the scanning timing of the common side electrode of the chip 21.
A read address indicating the storage location of data corresponding to a can be output to the buffer RAM 21. Therefore, from the buffer RAM 21, chip 2. Data corresponding to the LED 2a is input to the shift register 6. The read address generator 20 outputs a shift clock for inputting the above data to the shift register 6, and at the same time outputs a shift clock 128.
Since a latch signal is output to the latch circuit 5 at the time when the shift clock is outputted, each flip-flop forming the latch circuit 5 latches the data. A timing signal is input to the latch circuit 5 when data is latched, and each transistor of the drive unit 4 is driven by this signal input.

On the other hand, the decoder 9 has chips 2. A common code indicating the chip 21 is input in parallel with the data transmission of each LED 2a. Therefore, this decoder 9 decodes the common code, and the leader line COM
, apply voltage to .

Similarly, the common code indicating each chip 22, 23--2n is input from the ROM 10 to the decoder 9 in parallel with the transmission of data corresponding to the chips 22, 23--2n. 9 outputs voltage in a time-division manner.

By the way, if a pulse voltage with a small width is applied to a chip including an LED 2a with a large luminance of 1ii11 degrees, and conversely a pulse voltage with a large width is applied to a chip containing an LED 2a with a small luminance, the luminescence of each LED 2a of these chips will be reduced. The amount of light remains almost constant.

Therefore, in the present invention, the following data is stored in the ROM10. That is, this ROM 10 stores a common code and an address code indicating the storage location of data in the buffer RAM 21, and pulse width data approximately inversely proportional to the luminance of each LED 2a of each chip 21 to 2n is stored in each chip. The common codes 21 to 2n are stored in one-to-one correspondence. And R
At the start of the clock counting operation of the counter 11, OM10 first outputs a common code indicating chip 2 to the decoder 9, and also outputs a common code indicating chip 2 to the read address generator 20. An address code indicating the storage location of data corresponding to each LED 2a is output. Therefore, the read address generator 20 decodes this address code and outputs the read address to the buffer RAM 21 as described above.
D2a emits light.

Next, when the counter 11 counts a predetermined clock, the ROM 10 causes the read address generator 20 to instruct the read address generator 20 to correspond to each LEDZa of the chip 22 based on the stored pulse width data corresponding to the common code of the chip 2I. An address code indicating the data storage location is output, and at the same time, a common code indicating the chip 22 to be scanned next is output to the decoder 9. Therefore, COM from decoder 9
The voltage applied to +' falls, and a pulse voltage inversely proportional to the luminance of the LED 2a is applied to the common side electrode of the chip 21, and at the same time, the voltage applied to the decoder 9
A voltage is applied to the common side electrode of the chip 22 from .

That is, when the chip 21 includes the LED 2a with the highest luminance, the ROM 10 outputs a common code indicating the two words of the chip to the decoder 9, and outputs a common code from the decoder 9 to the leader line C.
A voltage is applied to OM + , and when the counter 12 has counted T/2 time clocks, it outputs a common code indicating the chip 22 and an address code indicating the data storage position. Therefore, the voltage to COM + drops by W, and the second
As shown in the figure and FIG. 3, the pulse voltage P1 has a pulse width of T/2, and each LED 2a of the chip 21 emits light for 172 hours. Further, a voltage is continuously applied to the chip 22, and each LED 2a of the chip 22 starts emitting light.

Next, when the chip 22 includes an LED 2a having normal brightness, the ROM10 controls the chip 23 when the counter 11 counts a time clock slightly larger than T/2.
At the same time, it outputs an address code indicating the storage location of data corresponding to each LED 2a of the chip 23 to the read address generator 20. Therefore, the voltage applied to COM 2 becomes a pulse voltage P2 with a slightly larger pulse width, and each LED 2 a of the chip 22 emits light only during the period when the pulse voltage P2 is applied. Further, a voltage is continuously applied to the chip 23, and the chip 23
Each LED 2a starts emitting light.

Further, when the chip 23 includes the LED 2a with the lowest luminance, the ROM10 outputs a common code indicating the chip 24 to the decoder 9 at the time when the counter 12 has counted approximately T time clocks, and also outputs a common code indicating the chip 24 to the read address generator. 20, an address code indicating the storage location of data corresponding to each LED 2a of the chip 24 is output. Therefore, the voltage applied to C0M3 becomes the pulse voltage P3 with the largest width, and each LED 2a of the chip 23 emits light for one hour. Incidentally, pulse voltages P1 to P3, etc., which are approximately inversely proportional to the luminance of the LED 2a of each chip, are also applied to the other leads COM4 to COMn, and the lead lines COM, to
A voltage is continuously applied to COM n.

Therefore, a time pulse voltage that is approximately inversely proportional to the luminance of the LED 2a of each chip is applied to the common side electrode of each chip 21 to 2n. Therefore, each chip 2. ~2n LED
Since the light beams 2a each emit light with a substantially constant amount of light, a latent image is formed on the photoreceptor 7 with the same amount of light. As a result, no shading occurs in the printed image on the transfer paper. Further, as described above, pulse voltages P, -P3, etc. are continuously applied to the leader lines COMI - CO, Mn, and accordingly, each LED 2 a of each chip 21 - 2n is As shown in the figure, since light is emitted continuously, the scanning time for - lines is shortened, and since there is no dead time, the formation of latent images for - lines is completed in a short time. Therefore, the amount of poems required for printing out can be significantly shortened.

By the way, each chip 2, ~2n in the LED printer
It is necessary for the LED 2a to have a small light emitting area and to obtain a sufficient amount of light in a short time, so as mentioned above, each chip 2.
A large current is supplied to the ~2n LEDs 2a. For this reason, conventionally, the LED 2a deteriorates significantly and the LED array 1 has to be replaced in a short period of time, which is very uneconomical. However, in the present invention, as described above, the pulse voltages P1 to P3, etc. are continuously applied to the chip 2. Since each of the ~2n LEDs Za is made to emit light continuously, the scanning time for - rows can be shortened.

Therefore, 1 is connected to the common side electrode of each chip 21 to 2n.

Chip 2. By increasing the scanning time of ~2n slightly, each chip 2
A small current density 1 is applied to each LED 2a from 1 to 2n.
1 supplies current for a slightly longer time, which allows each chip 2
．． It is also possible to obtain the amount of light necessary for exposure while preventing deterioration of the ~2n LED 2a. Therefore, in this case, the time required for printing out can be significantly shortened compared to the conventional method, and the LED array 1 can be used for a long period of time, which is economical.

Another embodiment of the invention is shown in FIG. That is,
In this example, LED array l is chip 2. The chips 2I-2n and 2'1-2'n are each connected to a drive circuit 3.3 via a signal line D OD +2r. On the other hand, a plurality of lead wires COM + to COM n are independently connected to the common side electrodes of the chips 21 to 2H, and a plurality of lead wires COM + to COM n are independently connected to the common side electrodes of the chips 2'1 to 2'n. Leader lines COM'+ to COM'n are independently connected. Leader line COM + ~C0M
n is connected to the decoder 9 via the buffer gate I.8, and the lead lines COM'+ to COM'n are connected to the buffer gate 8.
The decoder 9' is connected to the decoder 9' via the decoder 9'. ROMs 10 and 10' are connected to the input sides of the decoders 9 and 9', respectively, and read address generators 20 and 20' are connected to each output side of the ROMs 10 and 10'.

On the output side of each read address generator 20, 20', there is a buffer RAM 21 for storing data of each LED 2a of chips 2 and 2n, and a buffer RAM 21 for storing data of each LED 2a of chips 2'+ to 2'n.
A buffer RAM 21' for storing data 2a is connected thereto. Further, a write address generator 22 is connected to each buffer RAM 21, 21'. and,
The ROM10 contains a common code for each chip 21 to 2n, an address code indicating a data storage location in the RAM 21, and a common code for each chip 2. ~2n pulse width data approximately inversely proportional to the luminance of the LED 2a is stored in one-to-one correspondence with each common code. In addition, ROM10' contains the common code and buffer RAM of each chip 2'1 to 2'n.
21' address code indicating the storage location of the data,
Pulse width data that is approximately inversely proportional to the luminance of the LED 2a of each chip 2' to 2'n is stored in one-to-one correspondence to each common code.

In this embodiment as well, the counting operation of the counter 11 causes the ROM
l0 and lO' are the decoder 9, the read address generator 20, and the decoder 9' and the read address generator 20.
', and from each decoder 9 and 9'
+ - Since the LED 2a of each chip is made to emit light continuously while pulse voltages P1 to P3 of a predetermined width (see Figure 2) are continuously applied to COM n, COM', and COM'n, it is possible to Images without shading can be printed in a short time.

FIG. 5 shows still another embodiment of the present invention, in which L
The ED array l is divided into chips 21-2n and 2'1-2'n, and the chips 21-2n have signal lines DO-D+2.
Drive units 12A to 12D are connected to chips 2'1 to 12D via
Drive units 12'A to 12'D are similarly connected to 2'n. Each of these drive units 12A-120, 12'A-1
2'D has the configuration shown in FIG. That is, each drive section includes a shift register 14, as shown in FIGS. 5 and 6. Each shift register 14 receives 32-bit data, and writes latch paths 151 to 151, respectively.
15n are connected in parallel. These write latch circuits l'5, ~15n, for example, include 32 flip latch circuits l'5, ~15n.
It consists of a flop and can latch 32 bits of data. Each write latch circuit 15. The output side of the decoder 16 that decodes the write address is connected to the gate terminal G of 15n. Drive latch circuits 17+ to 17n are connected to the output side of each write latch circuit 151 to 15n, and these drive latch circuits 17+ to 17n similarly have a configuration to latch 32-bit data. ing. Each drive latch circuit 17+~1
The output side of a decoder 18 for common code decoding is connected to the output enable terminal OE of 7n. Each driving latch circuit 17. A driver circuit 19 is connected to the output side of 17n. The driver circuit 19 of each drive unit is composed of 32 transistor arrays, and signal lines DO to D12r are divided into four and connected to the output side, respectively. Each shift register 14 of the drive section 12AN12D is connected in series by a data line 13, as shown in FIG.
The D shift registers 14 are connected in series by data lines 13'. Gates 20 and 20' are respectively connected to the counter 11', each decoder 16 of the drive units 12A-12D is connected to the output side of the gate 20, and the drive units 12'A to 12' are connected to the output side of the gate 20'. 'D decoders 16 are connected. The gate 20 is opened while the "L" signal is output from the control terminal of the counter 11' to the gate terminal G, and 1/2 of the value to be counted is counted, and the highest value of the counted value is reached. It closes when the bit switches to rHj and "H" is output from the control terminal. On the other hand, the gate 20' opens when rHJ is output from the control terminal of the counter 18 via the input 21.

Meanwhile, each chip 2. Leader lines COM, ~C0Mn and COM independently connected to ~2n and 2'1 to 2'n
ROM10 and 10' are connected to '+' to COM'n via decoders 9 and 9'. these,
The ROMs 10 and 10' store the same contents as those in the embodiment shown in FIG.

Next, the operation of the optical writing head according to the embodiment shown in FIG. 5 will be explained.

When the counter 11' is reset, rLJ is output from the control terminal.
is output and the gate 20 is opened. When a data group corresponding to the LED 2a of the chip 21 is serially transmitted to the data line 13 from the host computer (not shown), the shift register 14 of the drive unit 12A is synchronized with the clock input. and sequentially captures data from the input SI, and transfers the captured data to shift register 1 of the next drive unit 12B.
4 from the output SO. The shift register 14 of the next drive unit 12B also takes in data sequentially in synchronization with the clock input, and sends it to each shift register 14.14 of the next drive units 12c and 12D.

Each shift register 14 can accept 32-bit data input. Therefore, each shift register 14 of the drive units 12A to 12D first has 128 LEDs 2 of the chip 21.
The data corresponding to a is divided into four parts and input.

On the other hand, the counter 11' is set to frequency division by 128 and counts the clock in synchronization with the data transmission corresponding to the LED of the chip 21, so when the count reaches r128'', each of the driving units 12A-12D and 12'A- 12'D decoder 16
A code specifying the write latch circuit 151 is output. Therefore, each decoder 16 decodes this, and the write latch circuit 15 . Since the latch signal applied to the gate G of each drive section 12A is set to "H",
-12D, each write latch circuit 15
1, the data group corresponding to the 128 LEDs 2a of the chip 21 is divided into four parts every 32 bits and latched. Below, similarly, 128 LEDs of chips 2+ to 2n (7)
The data group corresponding to 2a is divided into four parts every 32 bits and latched into each write latch circuit 151-15n.

In this way, chip 2. When l/2 of the data group corresponding to ~2n LEDs 2a, that is, all the data for - rows, is latched, the counter ll' is set so that the highest value bit of the count value is rH.
J and outputs rHJ from the control terminal, so the game)
20 closes and the other gate 20' opens. Therefore,
When the data corresponding to the LEI) 2a of the chip 2'1 is continuously sent from the host computer, the data regarding the chip 2'1 is sent to each drive unit 12' via the data line 13' in the same way as described above. It is input to each shift register 14 of A to 12'D. And counter 11'
When it counts 128, it outputs a code specifying the write latch circuit 151 to the decoder 16, so the decoder 1
6 outputs a latch signal. Therefore, each drive unit 12'A
-1, 2'D respective write latch circuits 15+
Next, the data group corresponding to the 128 LEDs 2a of the chip 2' is divided into four parts every 32 bits and latched. Similarly, the data groups corresponding to the LEDs of the other chips 2'1 to 2'n are divided into four parts and latched by the write latch circuits 15+ to 15n of each of the drive units 12'A to 12'D. Therefore, the respective write latches 151 to 15n of each of the driving units 12A to 120 and 12'A to 12'D are provided with each chip 2. ~2n and 2'
, ~2'n is divided into four parts and latched.

In this way, when all data for a row is latched, a latch signal from the host computer is transmitted to each drive unit 12A.
The signals are input to respective driving latch circuits 171 to 17n of 12D and 12'A to 12'D. Therefore, each write latch circuit 15. The divided data of ~15n are stored in each driving latch circuit 17. ~17n, and the latch position is changed.

When the latch position is changed, a reset signal is sent from the host computer to the other counter 11, and the counter 11 counts the clock. ROM10 and 1
0' first outputs a common code indicating the chips 21 and 2'1 to the decoders 9 and 9' at the start of the clock counting operation of the counter 11, and also outputs each common code to each drive unit 12A to 12D and 12'. A-12'D decoder 1
Also output to 8. Therefore decoder 9.9' is chip 21
and 2'1, and the decoder 18 of the drive units 12A-12D and 12'A-12'D first outputs a pulse voltage to each common side electrode of the drive latch circuit 17. Outputs an enable signal to

In this case, each moving part 12A-12D and 12'A to 12'
Each driving latch circuit 171 of D includes a chip 2.
．． Since the divided data corresponding to 128 LEDZa and 2'1 are latched, when an "H" or "L" signal is output from each drive latch circuit 17 upon input of the enable signal, each The driver circuit 19 starts operating,
Signal lines Do-031, D32~D a3, D64~D
95 and D96-DI27 via chip 2. and 2
'n each of 128 LEDZa is made to emit light.

ROM10 and io' each indicate a chip 22 to be scanned next at the time when the counter 11 counts a predetermined clock.
and 2'2 are continuously outputted to the decoders 9, 9' and the decoders 18 of each driving section, and similarly, -common codes indicating the chips 23 to 2'n are continuously outputted. Therefore, by making the time for outputting each common code approximately inversely proportional to the luminance of the LED Za of each chip, a latent image can be formed on the photoreceptor in a short time with the same amount of light based on all the data for one row. be able to. As a result, images and the like can be quickly printed out on transfer paper without causing any shading.

In this way, by using the drive units 'l' 2A-12D and 12'A-12'D having the above configuration, the removal drive latch in which all the data for - rows is sequentially latched in the writing latch circuits 151 to 15n. When the circuits 171 to 17n are latched again, data transmission and scanning of each chip 21 to 2n and 2', to 2'n can be performed asynchronously. Therefore, even when the scanning time of each chip is arbitrarily set using the ROMs 10 and 10' as in the present invention, there is no need to synchronize the timing of the operation of the data transmission circuit and the chip scanning. The scanning time of each chip can be set to be approximately inversely proportional to the luminance of the LED Za without using a control circuit.

(Effects of the Invention) According to the present invention, lead wires are independently connected to the common side electrodes of each chip forming the LED array, and a voltage is applied to the decoder from ′ to these lead wires based on the common code. At the same time, the output voltage from the decoder is controlled by the decoder control means consisting of ROM etc.
By making it fall in approximately inverse proportion to the ED luminance □, and simultaneously outputting the common code corresponding to the next chip to be scanned continuously to the □ decoder, each ED can be In addition to being able to cause the LED of the chip to emit light with a substantially constant amount of light, it is also possible to scan the chip for a short period of time based on data for -1 rows.

Therefore, it is possible to provide an optical writing head of an LED printer at a low cost, which is capable of displaying characters, etc., on transfer paper at a constant density, and is also capable of printing out quickly. Furthermore, by relatively increasing the pulse width of each pulse voltage applied to the common side electrode of each chip, it is possible to obtain the amount of light necessary for exposure even if the current density supplied to the LED is reduced. Deterioration of the LEDs on the chip can be effectively prevented, and therefore the LED array can be used for a long period of time.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the optical writing head according to the present invention, FIG. 2 is a timing chart for explaining the operation of the optical writing head of the present invention, and FIG. 3 shows the fluctuation of the current supplied to the LED of each chip. 4 and 5 are respectively circuit configuration diagrams of optical writing heads according to other embodiments of the present invention, and FIG. 6 is a diagram of the driving section according to the embodiment of FIG. 5. 7 is a circuit diagram of a conventional optical writing head, FIG. 8 is a conventional operation timing chart, FIG. 9 is a diagram showing a latent image formation state, and FIG. 1O is a perspective view of a chip. Figures 11 (A) and (B) are timing charts showing conventional current supply mode, Figure 12 (A)
, (B) is a timing chart showing a conventional manner of voltage application to the common side electrode. 1--------1----LED array, 21-2
n ---------- Chip, 2'1~2'n------
--tt, 3------=-- one drive circuit, 9.9'----------decoder, 10.10'
--------ROM, 11.11'-----Ichiriki Tsunta, COM + -
C'OM n---One leader line, COM' 1~COM
'n--//. 9 q ＼＄dispersion Q Cf9 ′+hand +, shrimp also collect+, (+I ・to〈

Claims (1)

[Scope of Claims] 1. An LED array formed by arranging chips including a plurality of LEDs in a row, and an LED array of each of the chips;
an optical writing head for an LED printer, comprising: a drive circuit that supplies current based on predetermined data; A decoder whose lead wires are connected in parallel and which decodes a common code and applies a voltage to the common side electrode of a corresponding chip via the lead wire, and an LED whose corresponding chip has a voltage output from the decoder. 1. An optical writing head for an LED printer, comprising: a decoder control means for decreasing the power level at a time width approximately inversely proportional to the luminance of the light emitted by the LED printer, and simultaneously outputting a common code corresponding to a chip to be scanned next. 2. Optical writing of the LED printer according to claim 1, characterized in that the fall time of the voltage output from the decoder is delayed overall, and the current supplied from the drive circuit is lowered. head.