JPH02235659A - Printer - Google Patents

Abstract

PURPOSE:To simplify circuit configuration by causing a clock generating means to carry out a specific turning action and printing one line in a main scanning direction. CONSTITUTION:A printer controller circuit 20' is composed of an oscillator 22, a clock control part 23 and a timing control circuit 24; the clock control part 23 consists of a 128-notation counter 30, a timer 31, flip-flops 32 and 33, an AND gate 34, and an OR gate 35. When a print clock signal PCLK, a vertical synchronizing signal VSYN and a horizontal synchronizing signal HSYN input to a video data control part 21, it outputs video data VDATA to a shift register 25 and a video clock signal VCLK both to a shift register 25 and to the counter 30 in the clock control part 23. The signal VCLK increments count data in the counter 30 in order, and after 128 pieces of data are input, a latch signal is output to a latch circuit 26.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a printing device, such as an LED printer, an EL printer, or a facsimile machine, in which light emitting elements are arranged in an array.

[Conventional technology]

2. Description of the Related Art Printing devices are known that have light emitting elements arranged in an array inside and print on paper using an electrophotographic method. For example, L.E.
D (Light Emitting Diode) LED printers, which have light emitting elements arranged in rows, selectively emit light from the LEDs based on the print data, write light onto the photoconductor line by line, and transfer the image to paper using an electrophotographic process. This is a device that is created in

However, the light-emitting elements used in the above-mentioned devices are extremely small, and a large number of light-emitting elements are formed, and these light-emitting elements require a large current (for example, 10 to 15 mA per one light-emitting element) to drive. Therefore, the light emitting elements are driven by time division.

FIG. 6 is a printing control circuit diagram in a conventional printing device for time-divisionally driving LED elements arranged in one row, and FIG. 7 is a time chart of time-divisionally controlling the LED elements. In both figures, the shift register section 1 is constructed by cascading four shift registers (la to id), and serially inputs video data (DATA) from the shift register 1d in conjunction with a clock signal (CLK). Then, the video data that is input sequentially in synchronization with the clock signal is shifted to the shift registers 1d → IC → 1b → 1a in order, and the video data (
For example, when 2,560 pieces of video data are input, the video data is output in parallel to the latch circuit 2 in synchronization with the launch signal (LA) and latched by the latch circuit 2. The video data latched in the latch circuit 2 is sent as a strobe signal STR1 to a NAND gate 3.
Corresponding to the output of STR4, it is outputted from NAND gate 3 to corresponding LED array 5. That is, when the strobe signal STR 1 is output to the NAND gate 3a, the NAND
The video data input to the D game 3a is outputted to the corresponding LED array 5a via the driver 4a, and each LED in the LED array 5a is controlled to be turned on or off according to the video data. Next, strobe signal STR2
When output to the NAND gate 1-3b, the video data input to the NAND gate 3b is output to the corresponding LED array 5b via the driver 4b, and each LED in the LED array 4b is driven and controlled in accordance with the video data. The following strobe signal STR. NAND by the output of 3
Drive control of each LED in the LED array 5C according to video data inputted to the game 3c, and a strobe signal ST
The output of R4 drives and controls each LED in the LED array 5d in accordance with the video data input to the NAND gates 1-3d.

Therefore, the strobe signals STR 1 to 4 are sequentially NANDed.
Time division driving is performed by outputting to gates 3a-→3b→3C→3d, sequentially selecting LED arrays 5a→5b→5C→5d, and driving and controlling the LEDs in each LED array 5a to 5d according to video data. It is carried out.

For this reason, in conventional printing devices, for example, the strobe signal ST
A number of signal lines corresponding to the above-mentioned time division number are connected between the printer controller that outputs R1 to STR4 and the print head incorporating the circuit shown in Fig. 6 above, and a strobe signal (selection signal) is sent from the printer controller to the print head. It is necessary to supply

[Problems with conventional technology]

In the conventional printing device as described above, in addition to signal lines for video data, clock signals, and latch signals output to the print head, there are a number of wires (corresponding to the number of time divisions) between the printer controller and the print head. For example, in the above example, it is necessary to connect four (4) signal lines for the strobe signals STR1 to STR4, which increases the number of wiring lines between the printer controller and the print head, causing an increase in the cost of the apparatus.

On the other hand, in order to input and hold one line of video data, shift registers and latch circuits require a large number of circuits (the number of LEDs) to be connected serially, which also reduces the cost of equipment. Cause.

[Purpose of the invention]

In view of the above conventional drawbacks, the present invention provides a printing device that reduces the number of signal lines for strobe signals, simplifies the circuit configuration of shift registers, etc., and makes it possible to time-divisionally drive light emitting elements. The purpose is to

[Key points of the invention]

According to the present invention, the above object is achieved by an optical dot generating means in which a large number of light emitting elements are arranged in an array in the main scanning direction, and an n-bit clock provided in a print control section to supply a clock of n bits per operation to a character development control section. a clock generation means for sending out, n-bit print data sent from a character expansion control section to the optical dot generation means in synchronization with the clock, and a storage device provided in the optical dot generation means to hold the n-bit print data. and a driving means that drives the light emitting element based on the print data held in the data holding means, and prints one line in the main scanning direction by operating the clock generating means m times. This is achieved by providing a printing device characterized by performing the following.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

This embodiment describes an example of an LED printer as a printing device of the present invention.

FIG. 2 is an overall configuration diagram of the LED printer. In the figure, the LED printer P includes a photoconductor drum 6, a charger 7 arranged in sequence near the circumferential surface of the photoreceptor drum 6, and an LED.
A head 8, a developing device 9, a transfer device 10, a cleaner 11, a slip roll 14 for conveying the paper T carried out by a paper feed roller 13 from a paper feed cassette 12, and a resist plate 15.
, fixing roll 16, wandering paper roll 17, guide plate 18a~
It is composed of 18c. Furthermore, an interface controller board 19 provided with an interface controller circuit and a printer controller board 20 provided with a printer controller circuit are disposed at the bottom of the LED printer P.

The charger 7 is a device that applies an initial charging voltage to the specular surface of the angry photo drum 6 rotating in the direction of arrow A, and the LED head 8 is a device that exposes the specular surface based on video data. The developing device 9 is a device that converts the electrostatic latent image formed on the photosensitive surface by the above-mentioned exposure into a toner image, and the transfer device 10 is a device that transfers this toner image onto the sleeve T. Further, the cleaner 11 is a device for removing toner remaining on the light-separating surface, and the fixing roll 16 is a device for conveying the paper onto which the toner image has been transferred and thermally fixing the toner image on the paper.

FIG. 1 shows the liquid crystal head 8, the interface controller board 19, the head control circuit 8' in the printer controller board 20, and the interface controller circuit l.
9' is a diagram showing the circuit configuration of the printer controller circuit 20' and the signal input/output relationship between the circuits. A video data control section 21 is provided inside the interface controller circuit 19' for receiving print data output from a host device (not shown) and converting it into video data. The printer controller circuit 20' is a circuit that controls various parts including the LED elements inside the LED head according to the video data, and is composed of an oscillator 22, a clock control section 23, and a timing control section 24. The head control circuit 8' is a circuit that controls the lighting of the LED elements in the LED head 8 according to the video data, and is composed of a shift register 25, a latch circuit 26, an LED array 27, a driver 28, and a division control section 29. .

Further, as shown in FIG. 3, the clock control section 23
128-decimal counter 30, timer 31, flip-flops (hereinafter referred to as F/F) 32, 33, and (AND)
It is composed of a gate 34 and an OR gate 35.

A clock signal output from an oscillator 22 composed of a crystal resonator (not shown) is output to an AND gate 34, and when an output signal from F/F 3 2, which will be described later, is at a high level (F/F 3 2 is In the set state) a print clock signal (PCLK) is output to the video data controller 21. In addition, the timing control unit 24 generates a vertical synchronization signal (VSYN) and a horizontal synchronization signal (HSYN) based on data such as the paper size used by the liquid crystal printer P and paper feeding timing.
is output to the video data control section 21. The video data control unit 21 includes a print clock (PCLK), a vertical synchronizing signal (VSYN), and a horizontal synchronizing signal (HSYN).
When input, the video data (VDATA) is output to the shift register 25, and the video clock signal (VCLK) is output.
is output to the shift register 25 and the counter 30 in the clock control section 23. The specific circuit of the head control circuit 8' is constructed as shown in FIG.
DATA) is sequentially input into the shift register 25 from the terminal I2 in synchronization with the video clock signal VCLK input from the terminal I3. Further, the video clock signal (VCLK) input to the counter 30 sequentially increments the count data in the counter 30, and the video clock signal (VCLK) is input to the counter 30.
When 128 K) are input, a latch signal (LA) is output to the latch circuit 26. The shift register 25 is 12
The video data (V
The video data (V DATA) in the shift register 25 is latched into the latch circuit 26 in synchronization with the launch signal (LA) inputted from the terminal 1.

Further, the horizontal synchronization signal (HSYN) is also input to F/F 3 3 in the clock control unit 23, and F/F 3
3 to the head control circuit 8 as a reset signal (RS).
' from the terminal I5 of the division control unit 29 via the buffer 36.
A set (S) of data type flip-flops (hereinafter referred to as DF/F) 38-1 forming a part of
/F38-2 to 3B-20 are supplied to the reset (R) terminals.

By inputting this reset signal (RS), the D F/F38
-1 is set to the set state (logic “1”) and the DF/F
38-2 to 38-20 are set to a reset state (logic "0"). On the other hand, the counter 30 receives the aforementioned latch signal (L
The timer start signal (TS
) is output to the timer 31, and the timer 31, which is in the reset state by inputting the reset signal (RS), outputs the strobe signal (ST) for a preset predetermined time from the terminal I6 of the head control circuit 8' via the inverter 37. DF/F
3 8 - 1 to 38 - 20 clock (CK) terminals and an OR gate 39 - 1 forming part of the division control section 29
~39-20-・Output. This strobe signal ST
In synchronization with the output of DF/F38-
The corresponding OR gate 39 Hello (L) {i is output from any one of the LED arrays 27-1 to 27-20 through the corresponding driver 28. select. The lighting of the LEDs in the selected LED array is controlled by the video data VDATA latched by the latch circuit 26 described above.

Next, the printing operation will be explained in detail using the time chart shown in FIG. First, when a print start signal is input from the host computer, the printer controller 20
' starts controlling the image forming portions such as the photosensitive drum 6, the charger 7, and the developer 9. Thereafter, when the paper is fed and reaches the registration plate 15, the timing control unit 24 outputs a vertical synchronization signal (VSYN), and then the timing control unit 24 outputs a horizontal synchronization signal (VSYN) that instructs writing of print data for each line. HSYN) is output to the video data control section 21. In addition, the video data control unit 21
At this time, the horizontal synchronization signal (HSY
A set signal (S) is input to the F/F 32 via the OR gate 35 by human power of the A. By turning on the ND gate 34, the print clock signal (PCLK) output from the clock control section 23 is input. The video data control unit 21 uses this print clock signal (pCL
A video clock (VCLK) and video data (VDATA) are output in synchronization with K). This video clock signal (VCLK) is the video data (VDAT) as described above.
A) is used as a synchronizing signal to sequentially input to the shift register 25, and is also input to the counter 30 to sequentially increment the count data. Then the video clock signal (
When 128 pieces of VCLK) are output, input of video data (VDA 1''A') is completed to all 128-bit data areas in the shift register 25, and the 128-decimal counter 30 starts counting up. ,
The latch signal (LA1) is output to the latch circuit 26, and the video data (VDATA) in the shift register 25 is latched into the latch circuit 26. Also, at this time, the F/F is reset by the reset signal (RS) output from the counter 30
32 is temporarily in a reset state. Next, the strobe signal (ST+
) as described above < D F/F 3 8 -1 to 3B-2
0 and output to OR game 1-39-1 to 39-20. At this time, as mentioned above, the DF/F38-1 is set to the set state (logic "]"), and the DF/F38-2
~3 8-2 0 is reset state (logical tl O ++
), the input of this signal causes the DF to
/F38 1 page output only mustard signal is OR game}3
Output to 9-1 and other DF/F38-2 to 38-20
From the page output of , the H signal corresponds to the OR gate 39-2 ~
39-20. For this reason, the OR game}39-1
The mustard signal is output to the driver 28, and the voltage VDD applied to the LED array 27-1 via the terminal 4 is supplied to select only the LED array 27-1.

Therefore, as described above, 12 latched by the latch circuit 26
8-bit video data (VDATA) is an LED array.
27-1 to the corresponding terminal, and this video data (
LED in LED array 27-1 according to VDATA)
Controls the lighting of LI to Ll2g. Next, L E in the LED array 27-1 as described above.
While DLI~LEDLl21 is being driven and controlled,
The next 128 pieces of video data (VDATA) are input to the shift register 25. At this time, the timer 31 controls the output of video data (VDATA) to the shift register 25.
The strobe signal (s'r.) output from the counter 30 is input to the F/F 32 via the OR gate 35, and the F/F 32 is reset once by the reset signal (RS) from the counter 30.
By setting F 3 2 to the set state again and outputting a print crotter signal (PCLK) from the AND gate 34 to the video data control section 21, the same process as above is performed using this print crotter signal (PCLK). That is, when the 128-bit video clock signal (VCLK) is input to the counter 30 again, the counter 30 counts up, the next 128-bit video data in the shift register 25 is latched in the latch circuit 26, and then the timer 31 outputs the data for a predetermined period of time. Output strobe signal STz
Based on the logic "1" set in DF/F3B-2, a signal is output from the output page to OR gate 39-2, and a voltage (
+Voo) is applied and LED array 27-2 is selected (
Note that the L signal is input to DF/F3B-1 from the D terminal, and at this time, the output from the page output of DF/F 27-1 becomes an H signal). Therefore, at this time, the 128 videos latched in the latch circuit 26? data (VDATA) is LE
LED L. in the LED array 27-2. (2) Control the lighting of ~L2 and 6.

Hereinafter, after the counter 30 counts up in the same manner, the strobe signals ST3 to ST are output from the timer 31.
LED array 27-3 → 27-4 →... by zo
are sequentially selected to control the lighting of the LEDs in each LED array. Then, the lighting of the LED array 27-20 is controlled according to the output of the last 20th strobe signal STzo.
When all the driving and movement of the D arrays 27-1 to 27-20 are completed, the above-mentioned optical writing of one line on the optical surface is completed.

Thereafter, when the horizontal synchronization signal (HSYN) is output, the LED drive control process is repeated in the same way, and optical writing can be sequentially performed on the photosensitive surface in accordance with the video data VDATA.

As described above, in this embodiment, each LED array 27-1 to 27-2
printer controller 20' to select 7-20.
It is only necessary to output a heliset signal (RS) and a strobe signal (STR) from the head control circuit 8' to the printer controller board 20 and the LED head 8, and a shift register 25 with a 128-bit configuration can be configured with fewer signal lines. , latch circuit 26, and 128-decimal counter 30
The video data VDATA is input to the shift register 25 every 128 bits using
This is to sequentially control the lighting of D arrays 27-1 to 27-20.

In this embodiment, the shift register 25 and latch circuit 26 are
Although it is constructed using a 28-bit configuration and a counter 30 for 128 counts, it is of course not limited to 128 bits.Also, although the case where an LED is used as a light emitting element has been explained, it is not limited to an LED. Of course, the present invention can also be applied to a device in which light emitting elements are arranged in a row.

〔Effect of the invention〕

As described in detail above, according to the present invention, the circuit configuration is simplified because a large number of signal lines for transmitting strobe signals as in the conventional method are not used. Furthermore, since a shift register/later circuit with a small data area capacity can be used, the circuit configuration can be simplified and the cost of the device can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a liquid crystal printer according to an embodiment of the present invention, FIG. 2 is an overall configuration diagram of a liquid crystal printer according to an embodiment of the present invention, FIG. 3 is a circuit diagram of a cloth control section, and FIG. 4 is a circuit diagram of a liquid crystal printer according to an embodiment of the present invention. A specific circuit diagram of the head control circuit, Figure 5 is L.
A time chart explaining the light emission control of the ED, FIG. 6 is a conventional light emission control circuit diagram of the LED, and FIG. 7 is a diagram of the conventional L.D. 3 is a time chart illustrating light emission control of ED. 6... Photosensitive drum, 7... Charger, 8... LED bed 8'... Head control circuit, 9... Developing device, 10... Transfer device, J1... Cleaner, 12 ...Paper feed cassette, 16...Fixing roll, l9...Interface controller board, 19'
・・Interface controller circuit, 2v・・
-Printer controller board, 20'... Printer controller circuit, 21... Video data control section, 22... Oscillator, 23... Cronk control section, 24... Timing control section, 25... Shift register , 26...Latch circuit, 27, 27-1 to 27-20...LED array-28...Driver, 29...Divided control section, 30...Counter, 31...Timer , 32, 33 ・ ・ ・ F/F, 34 ・ ・ ・AND gate, 38-1 to 38-20 ・ ・ ・D F/F, 39
-1~39~20 ・ ・ ・OR gate. Patent applicant Casio Electronics Industries Co., Ltd. Above Casio Computer Co., Ltd. Figure 2

Claims (2)

[Claims] (1) An optical dot generation means in which a large number of light emitting elements are arranged in an array in the main scanning direction, and a clock generation means provided in the print control section and sending out an n-bit clock per operation to the character development control section. , n-bit print data sent from the character expansion control unit to the optical dot generation means in synchronization with the clock, and data holding means provided in the optical dot generation means and holding the n-bit print data; and a driving means for driving the light emitting element based on the print data held in the data holding means, and printing one line in the main scanning direction by operating the clock generating means m times. printing device. (2) The printing device according to claim 1, wherein the number of the light emitting elements is m×n.