JPS62275759A - Led array drive circuit - Google Patents

Abstract

PURPOSE:To facilitate correction of the dispersion of the quantity of light for every optical printer, by a method wherein a plurality of LED array chips arranged lengthwise are divided into two or more blocks and the number of the LED array chips in the each block as well as the conduction time thereto can be arbitrarily set. CONSTITUTION:After picture element data signals DS corresponding to LED elements are inputted and successively stored in respective shift register portions in drive circuits IC 71-7n, a latch signal L1 is emitted to latch the picture element data DS to respective latch portions in the drive circuits. By receiving a reference clock phi, a chip number set circuit 8, consisting of a DIP switch 801 and a counter 802, sends a dividing clock phi2 to a conduction time set circuit 9 and a latch circuit 11. In the conduction time set circuit 9, the ON/OFF information for a DIP switch 901 is inputted into a counter 902 as an initial value and set when the latch signal L1 is inputted. Thereafter, the counter steps on at every input of the dividing clock phi2, for example, to a value '16'; then, a CA terminal output from the counter terns to 'H' and the polarity is inverted in an inverter circuit 903, thereafter being outputted as a timing pulse TP to a shift register 10, and simultaneously bringing a stepping action of the counter to stop.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention (Field of Industrial Application) The present invention is a light emitting diode (LED)! The present invention relates to an LED play drive circuit in an optical glintter used as a light emitting element.

(Prior Art) In recent years, semiconductor radars, which are easy to control directly, have been increasingly used as light sources in recording devices that fully utilize xerography.

Furthermore, recently, an LED array light source has been developed with the aim of reducing the size of a mechanical scanning total combing device by 74%, and a 'fc device incorporating this has been announced. In the LED array chip used here, the resolution of the light emitting part directly becomes the resolution at the time of printing, but since the above-mentioned optical printers are generally characterized by high resolution, for example, if the resolution is 10 lines / cabinet, the arrangement of the light emitting parts The pitch is 0.1
It has a small value called ran. However, since there is a limit to the size of the GaAa wafer used as a base material, there is a limit to the length of a single LED array chip. For this reason, when manufacturing all the long print heads used for printing wide forms, etc.,
Multiple LEs depending on the desired length of the glint head.
D array chips must be connected and used.

FIG. 2 is a conceptual diagram in which a plurality of LED array chips are mounted and wired on an insulating substrate.

In the figure, 1 is an insulating substrate, 2 is an LED array chip arranged and mounted on this substrate l, and 3 is a wiring group formed on the substrate l, including an LED array drive circuit (not shown).
It is connected to the output.

Reference numeral 4 denotes a ending wire for electrically connecting the individual electrodes of the LED array 2 and the wiring group 3. 5 is a conductive adhesive layer for fixing the LED array chip 2 onto the insulating substrate l, and resin or solder is usually used.

A common electrode of the LED array chip 2 is normally formed on the lower surface of the LED array chip 2 and led to a common power supply wiring section 6 via a conductive adhesive layer 5. In such a high-density LED play that has a large number of light-emitting parts, an image is formed on the photoreceptor according to the light-emission energy (light-emission amount x light-emission time) of the LED, but if the light-emission time is lengthened, the resolution will increase. It's great for getting good images. The reason for this is that the dot diameter increases with the elapse of light emission time. In order to eliminate all of these print quality problems, there is a technique in which the driving method of the LED is reviewed. This type of technology is disclosed in Japanese Patent Laid-Open No. 59-55770.

In this method, a plurality of LED elements are divided into blocks, each block is connected to all the individual switching elements on the common electrode side, and the individual electrodes are wired in a matrix, so that each block is sequentially driven.

(Problems to be Solved by the Invention) However, according to the LED array driving method disclosed in the above-mentioned document, firstly, in order to electrically separate the common electrode portions between blocks, it is necessary to In the LED array structure diagram shown in Figure 2, it is necessary to divide the blocks into at least integral multiples of the LED array chips, and at this time, limit the amount of resin so that the die pint adhesive does not protrude to the adjacent block side. Another problem is that it requires complicated work such as repairing the protruding portion later.Secondly, it requires materials and space for matrix wiring on the individual electrode side, which increases costs and increases the size of the LED head. Thirdly, there was the problem that i4 warp vises such as switching elements were required for the number of divided blocks, increasing the cost.

An object of the present invention is to eliminate all of the above-mentioned problems and to provide an LED array drive circuit for an optical printer that has high print quality, is inexpensive, and has high productivity.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a plurality of LED array chips electrically connected to each of a plurality of LED array chips arranged in an elongated manner. LE with drive circuit IC
In the D array drive circuit, the plurality of LED array chips are divided into a plurality of blocks, and the LE in each block is
The pre-drive circuit IC is equipped with means for setting the number of D array chips and means for setting the energization time of the LED array chips in each block, and is adapted to drive each of the LED array chips. .

The chip number setting means and the energization time setting means may be set so that the energization time between adjacent blocks is partially overlapping.

(Function) According to the present invention, the number of LED array chips in each block can be arbitrarily set, and the energization time of the LED array chips in each block can also be arbitrarily set. Light intensity sensitivity variations can be easily corrected.

In addition, by setting the energization time between adjacent blocks so as to partially parallelize each other, the power supply current can be smoothed.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a circuit block diagram of an LED array head according to the present invention, where A represents LED array chips 21, 2□, . . . + 2n-1+ each having 64 LED elements.
2n LED array, B is a drive circuit for driving the LED array A. This drive circuit B is for each LE
A plurality of drive circuits I each connected to the D array chip.
It consists of C71, 7□, -, 7, 4, 7n, a chip number setting circuit 8, an energization time setting circuit 9, a shift register IO, and a latch circuit 11.

As shown in the block diagram of FIG. 3, the drive circuit IC71
, 7□, . . . +7n are 64-pit shift resistor sections 701. Consisting of a latch section 702 and a driver section 703, 64 output terminals 0U of this driver section 703
T1. ..., 0UT64 is connected to the LED element of the corresponding LED array chip.

Further, as shown in the block diagram of FIG. 4, the chip number setting circuit 8 includes a dip switch 801 and a counter 802, receives the reference clock φ1, and sends the branch clock φ2 to the energization time setting circuit 9 and the latch circuit 11.

In addition, as shown in FIG. 5, the energization time setting circuit 9 includes a dip switch 901, a counter 902, an inverter circuit 903, a latch signal 4, and a branch clock φ2.
'f! : Receive it and send it to No9rus TPi Shift Reno Star IO.

FIG. 6 is an operation timing chart of signals of each part.

The operation of this embodiment will be described below with reference to FIG. 1 and FIGS. 3 to 6.

First, when input of the pixel data signal D3 corresponding to each LED element is started, the data is sequentially stored in each shift register section 701 of the drive circuits IC71 to 7n. After all the pixel data signals D3 are stored in the shift register section 701, the pixel data D is latched into each latch section 702 in the drive circuit IC7, to 7n by the latch signal L1 manually.

By the way, the chip number setting circuit 8
2nf - This is to set the number of LED array chips in one block when dividing into blocks, and in FIG. 5, the on/off state setting output from the dip switch 801 is input to the counter 802 and 802
Corresponds to the initial value of This counter 802 is manually incremented by the reference clock φ1 from the initial value, and when it has incremented to, for example, 16, a carry signal is output from the CA terminal.
At the same time as the counter 802f is set to the initial value again, a carry signal is output to the frequency divided clock φ2. For example, by setting the depth inch 801f so that the initial value of the counter 802 is 13, the counter 802 becomes 16-13=3, that is, a ternary counter, and the frequency of the reference clock φ1 is divided by 3 and output as the divided clock φ2. do.

FIG. 6 shows a timing diagram of φ1 and φ2 in this embodiment, and it goes without saying that the frequency division number can be varied by setting the dip switch 801.

Further, the energization time setting circuit 9 sets the energization time for each block in which the LED array A is divided into a plurality of blocks, and as shown in FIG. be done.

The initial value of this counter 902 is manually set by the aforementioned latch signal L1, and thereafter, an increment operation is performed every time the frequency divided clock φ2 is input. After that, when the counter 902 advances to, for example, 16, the CA terminal output of the counter 902 becomes "H" level, and after the polarity of this output is inverted by the next stage inverter circuit 903, this polarity inverted output is output at the timing/J pulse TP.
(shift) is output to the register 10, and the incrementing operation of the counter 902 is stopped.

By setting the dip switch 901 so that the initial value of the counter 902 is 14 as the number is 11.
16-14=2 In other words, from the initial setting time of the counter 902, the CA terminal output i is at "L" level for two clocks of the divided clock φ2, that is, the timing Norse output TP
An output result of setting the timing node TP to "H" level is obtained, and this timing node TP is input to the shift register 10.

FIG. 6 shows the frequency-divided clock φ2 and the timing diagram TPO in this embodiment, and it goes without saying that the time width of the timing i4 TP can be varied by setting the dip switch 901.

In FIG. 2, the timing pulse TP set by the energization time setting circuit 9 is input to a serial-in-parallel-out type shift register 10, and data is sequentially shifted in synchronization with the reference clock φ1. The output of the shift register 1° is input to the latch circuit 11, and the latch operation to the silatch section 11 is performed by the divided clock φ2 output frequency-divided by the chip number setting circuit 8.

In this embodiment, i? of the timing pulse TP?
Since the pulse width has a time width of 6 clocks of the reference clock φ1 and a time width of 2 clocks of the divided clock φ2, the block 1 shown in FIG.
2, 3. ... can be obtained as the output of the latch section 11. In this case, the lunch section 11
Output terminals 1 and 2 have a timing waveform shown in block 1, output terminals 3 and 4 have a timing waveform shown in block 2, and so on.

The output of this latch section 11 is connected to the STB terminal of the driver section 703 of each drive IC 7, to 7n corresponding to the corresponding LED array chinogs 21 to 2n.

The driver section 703 of each drive circuit IC has its driving operation controlled according to the state of the STB input signal. For example, the drive operation is controlled according to the output result of the latch section 702 only during the period when the STB input signal is at "H" level. The driver section 703 is placed in an active or non-active state, and as a result, the energization time of the corresponding LED element is controlled.

Further, the output of the launch circuit 11 is outputted to block 1 (output terminals 1 and 2 outputs), block 2 (output terminals 3 and 4 outputs), block 3 (
Output terminals 5, 6 output), etc. are sequentially output, so the LF2D array A is connected to the LED array chip 24,
2□, LED array chip 2.2. The LED array chips 25 and 26 are sequentially driven in an overlapping manner by a division clock φ21 clocks.

Therefore, the energization time of each LED array chip can be controlled independently for each block.

(Effects of the Invention) As detailed above, according to the present invention, the following advantages can be obtained.

First, since the drive circuit ICC is fully integrated for each LED array chip in the LED array head, there is no need to electrically isolate the common electrode between each block, and there is no need for individual switching elements. A highly productive and low cost LED array head can be realized.

Second, since matrix wiring members and space on the individual electrode side between each block are required, a small LED array head can be realized at low cost.

Third, since the means for independently setting the number of LED array chips in one block and the means for independently setting the timing of energization start and end for each block are biased, the amount of light for each optical printer device is different. Variations in sensitivity can be absorbed with simple force operation.

Fourth, by variably setting the chip number setting circuit and the energization time setting circuit so that the energization time is partially parallel between adjacent blocks, it is possible to reduce the amount of change in the energization current to the LED array. It is possible to smooth the power supply current.

Fifth, since the LED array is driven in all blocks, the resolution after printing is sharp and high print quality can be expected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
A perspective view of the D array head, Fig. 3 is a block diagram of the drive circuit IC, Fig. 4 is a block diagram of the chip number setting circuit, Fig. 5 is a block diagram of the energization time setting circuit, and Fig. 6 is a block diagram of the drive circuit IC. Operation timing chart of signals of each part. 21, ? 2. −． 2n-4, 2n-LED array chip, 71.72, "" n-1r 7n "' Drive circuit ICl3... Chip number setting circuit, 9... Energization time setting circuit, 10... Shift register, 11 ...Latch circuit, 701...Shift register section, 702...
・Latch part, 703...Driver part, 801, 90
1...Delag switch, 802.902...Counter, 903...Inverter circuit. , 100th month of the present invention - 1st day of the 1st month of the 1st month of the 1st month of the 1st month of the 1st month of the 1st month of the 1st month of the 1st month of the 1st month of the 1st month of the 1st month of the 1st month of the 1st month of the 1st month of the 1st month of the 1st month of the 1st month of this year Along with Kapape

Claims (2)

[Claims] (1) In an LED array drive circuit including a plurality of drive circuit ICs electrically connected to each of a plurality of LED array chips arranged in an elongated manner, the plurality of LED array chips are connected to a plurality of LED array chips. It is equipped with means for dividing into blocks and setting the number of LED array chips in each block, and means for setting the energization time of the LED array chips in each block, and for output and print data input of each of the means. The LED array drive circuit, wherein the drive circuit IC drives each of the LED array chips accordingly. (2) The number of chips setting means and the energization time setting means are set so that the energization times between adjacent blocks partially overlap.
) The LED array drive circuit described in item 1.