JPH07108573B2 - LED array drive circuit - Google Patents

Description

The present invention relates to an LED array driving circuit in an optical printer using a light emitting diode (LED) as a light emitting element.

(Prior Art) In recent years, a semiconductor laser, which is technically easy to control, is increasingly used as a light source of a recording device to which xerography is applied.
Furthermore, recently, an LED array light source has been developed for the purpose of eliminating the mechanical scanning of the light source and miniaturizing the device, and a device mounting this has been announced. LE used here
In the D array chip, the resolution of the light emitting part becomes the resolution when printing as it is, but since the above-mentioned optical printer is generally characterized by a high resolution, for example, a resolution of 10 lines / m
In the case of m, the arrangement pitch of the light emitting parts is as small as 0.1 mm. However, since the LED array chip has a limited size such as a GaAs wafer used as a base material, there is a limit to the length of the LED array chip that can be formed in a single piece. For this reason, when manufacturing a long print head used for printing a wide form or the like, a plurality of LED array chips must be spliced in accordance with the desired length of the print head.

FIG. 2 is a conceptual diagram in which a plurality of LED array chips are mounted and wired on an insulating substrate.

In the figure, 1 is an insulating substrate, 2 is an LED array chip aligned and mounted on the substrate 1, and 3 is a wiring group formed on the substrate 1, which is connected to an output of an LED array drive circuit (not shown). It is what is done. A bonding wire 4 electrically connects the individual electrodes of the LED array 2 to the wiring group 3. Reference numeral 5 denotes a conductive adhesive layer for fixing the LED array chip 2 on the insulating substrate 1 by die-bonding, and usually resin or solder is used. The common electrode of the LED array chip 2 is usually formed on the lower surface of the LED array chip 2 and led to the common power supply wiring portion 6 via the conductive adhesive layer 5. In an LED array with such a high density and a large number of light emitting parts, an image is formed on the light emitting body according to the light emitting energy (light emitting amount x light emitting time) of the LED. I can't get a good image. The reason is that the dot diameter increases as the light emission time elapses. There is a technology in which the LED driving method is reviewed to eliminate such a problem in print quality. This type of technology is disclosed in Japanese Patent Laid-Open No. 59-55770. This is one in which a plurality of LED elements are divided into blocks, the common electrode side of each block is connected to an individual switching element, and the individual electrode side is matrix-wired so that each block is sequentially driven.

(Problems to be Solved by the Invention) However, according to the LED array driving method disclosed in the above-mentioned literature, firstly, in order to electrically separate the common electrode portion between the blocks, In the LED array structure diagram shown in Fig. 2, it is divided into blocks at least every integer multiple of the LED array chip. At this time, the resin amount is limited so that the die bond adhesive does not protrude to the adjacent block side. Or, it requires complicated work such as improving the protruding portion later. Second, it requires matrix wiring members and space on the individual electrode side, leading to cost increase and LED head size increase. Thirdly, there is a problem that power devices such as switching elements are required for the number of divided blocks, resulting in cost increase.

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned problems and provide an LED array driving circuit for an optical printer which has high printing quality and is inexpensive and highly productive.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a driving circuit of an LED array head, which is arranged in a long shape and has respective common electrodes electrically connected in common. An LED provided with a plurality of drive circuit ICs provided corresponding to each of the plurality of LED array chips that are provided, and performing drive control of the LED array chips by applying a drive signal to the corresponding individual electrodes of the LED array chips. An array driving circuit for dividing the plurality of LED array chips into a plurality of blocks and setting the number N (where N is a positive integer) of the LED array chips in each block. Of the reference clock φ ₁ of each of the LED array chips in each block, that is, a chip number setting means for outputting a divided clock φ ₂ divided by the numerical value N, and energization of the LED array chips in each block. For setting a time, a timing pulse TP having a pulse width that is an integer multiple of the period T of the divided clock φ ₂ in response to the divided clock φ ₂ is set as the energized time, and the energized time is set. And a plurality of output terminals corresponding to the respective drive circuit ICs, the timing pulse TP is used as an input signal, and the input timing pulse is the reference clock φ ₁
Shift register means for sequentially shifting in synchronism with each other and outputting from each output terminal thereof, and a plurality of input terminals and a plurality of output terminals corresponding to each of the drive circuit ICs, and from each output terminal of the shift register means Output signal is input from each of the input terminals, the input signal is latched based on the divided clock φ ₂ , and the latched signal is used as a strobe signal from each output terminal of the corresponding drive circuit IC. Latch means for outputting to the strobe terminal, a shift register section provided corresponding to each of the LED array chips, and storing the respectively inputted print data signals while sequentially shifting, and the shift register section. A latch unit for latching the stored print data signal, the print data signal stored in the latch unit, and the latch unit for latching the print data signal. A drive circuit IC comprising a driver unit for controlling drive of a corresponding LED array chip based on a strobe signal input to a lobe terminal, wherein shift register units of the respective drive circuit ICs are connected in series. A plurality of the drive circuit ICs, and the drive control of each of the LED array chips is performed in the block unit.

In addition, the LED in the block in the chip number setting means
The setting of the number of array chips and the setting of the energization time in the energization time setting means may be set so that the energization times of adjacent blocks partially overlap.

(Operation) According to the present invention, the number of LED array chips in each block can be arbitrarily set, and further, the energization time of the LED array chips in each block can be arbitrarily set, so that each device in the optical printer device can be set. Variations in light amount sensitivity can be easily corrected.

Further, the power supply current can be smoothed by setting the energization times between the adjacent blocks so as to partially overlap each other.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit block diagram of an LED array head according to the present invention. A is an LED array consisting of LED array chips 2 ₁ , 2 ₂ , ..., 2 _n-1 , 2 _n each having 64 LED elements. Yes,
The common electrodes of the LED array chips 2 _{1 to} 2 _n are all electrically commonly connected and grounded. Further, B is a drive circuit for driving the LED array A. This drive circuit B
Are a plurality of drive circuit ICs 7 ₁ , 7 ₂ , ..., 7 _n-1 , 7 _n connected to each LED array chip, a chip number setting circuit 8, an energization time setting circuit 9, a shift register 10, a latch circuit 11. Consists of.

As shown in the block diagram of FIG. 3, the drive circuit ICs 7 ₁ , 7 ₂ ,
, 7 _n each include a 64-bit shift register unit 701, a latch unit 702, and a driver unit 703.
64 an output terminal OUT ₁ of, ..., OUT ₆₄ is connected to the individual electrodes of the LED element of the corresponding LED array chips. Further, the shift register section 701 of each drive circuit IC is connected in series as is clear from FIGS. 1 and 3.

Further, as shown in the block diagram of FIG. 4, the chip number setting circuit 8 comprises a dip switch 801 and a counter 802, which receives the reference clock φ ₁ and sends the divided clock φ ₂ to the energization time setting circuit 9 and the latch circuit 11. send.

Further, as shown in FIG. 5, the energization time setting circuit 9 comprises a dip switch 901, a counter 902, and an inverter circuit 903, which receives a latch signal L ₁ and a divided clock φ ₂ to generate a pulse TP.
To the shift register 10.

FIG. 6 is an operation timing chart of signals of each part. Less than,
The operation of this embodiment will be described with reference to FIGS. 1 and 3 to 6.

First, when the pixel data signal D _S of the corresponding LED elements is initiated input, a sequential data in the shift register unit 701 of the drive circuit IC 7 ₁ to _7-n are stored. After storing all the pixel data signal D _S is in the shift register unit 701, a latch signal L ₁ input, pixel data D _S is latched to the latch portion 702 of the drive circuit IC 7 ₁ to 7-a _n.

By the way, the chip number setting circuit 8 sets the number of LED array chips in one block when the LED array 2 ₁ ... 2 _n is divided into blocks, and in FIG. The state setting output is input to the counter 802 and corresponds to the initial value of the counter 802. This counter 802 advances from the initial value by the reference clock φ ₁ input, and when it advances to 15, for example, a carry signal is generated.
The carry signal output from the CA terminal is output to the next stage as the divided clock φ ₂ . Further, the counter 802 is set to the initial value again at the timing when the carry signal is output from the CA terminal and the next reference clock φ ₁ is input. By setting the dip switch 801 so that the initial value of the counter 802 is 13, for example, the counter 801 sequentially counts 13, 14 and 15 3
It becomes a progressive counter and outputs a divided clock φ ₂ (however, its period is T) obtained by dividing the reference clock φ ₁ input by 3. The number of divisions of the reference clock φ ₁ corresponds to the number of LED array chips in one block. That is, in this chip number setting circuit 8,
When the number of LED array chips is set to 3, for example, the divided clock φ obtained by dividing the reference clock φ ₁ by 3 as described above is used.
₂ is output, or when the number is 4, for example, it is set to output a divided clock φ ₂ obtained by dividing the reference clock φ ₁ by 4. FIG. 6 shows a timing chart of φ ₁ and φ _{2 in} the case of the present embodiment, but it goes without saying that the frequency division number can be changed by setting the dip switch 801.

The energization time setting circuit 9 sets the energization time for each block in which the LED array A is divided into a plurality of chips. As shown in FIG. 5, ON / OFF information of the DIP switch 901 is input to the counter 902 as its initial value. To be done.

The counter 902 is set to an initial value by inputting the latch signal L ₁ described above, and thereafter, a stepping operation is performed every time the divided clock φ ₂ is input. Due to this step operation, the counter 902 C
The A terminal output is at "L" level, but then, for example, 1
When stepped to 5, the CA terminal output of the counter 902 becomes "H" level. The polarity of the “L” level output signal output from the CA terminal is inverted by the inverter circuit 903 in the next stage and output to the shift register 10 as a timing pulse TP.
Next, the CA pin output changes from "L" level to "H" as described above.
When the level becomes high, this "H" level output signal is also inverted in polarity by the inverter circuit 903 at the next stage, and is input to the EN terminal (enable terminal) of the counter 902 as an "L" level signal. When the "L" level signal is input to the EN terminal, the counter 902 stops its stepping operation.

As an example, by setting the dip switch 901 so that the initial value of the counter 902 is 13, the counter 9
02 is 15−13 = 2, that is, two clocks of the divided clock φ ₂ from the time when the initial value of the counter 902 is set (in other words, twice the cycle T of the divided clock φ ₂ , that is, the time of 2T) CA
An output in which the terminal output is set to the “L” level, that is, the timing pulse TP output is set to the “H” level is obtained, and this timing pulse TP having a pulse width of 2T is input to the shift register 10.

FIG. 6 shows a timing chart of the divided clock φ ₂ and the timing pulse TP in the case of the present embodiment, but it goes without saying that the time width of the timing pulse TP can be changed by setting the dip switch 901.

In FIG. 1, the timing pulse TP set by the energization time setting circuit 9 is data-input to the serial-in-parallel-out type shift register 10 to sequentially shift data in synchronization with the input of the reference clock φ ₁ . The output of the shift register 10 is input to the latch circuit 11, and the latch operation to the latch unit 11 is performed by the output of the divided clock φ ₂ divided by the chip number setting circuit 8.

In this embodiment, the pulse width of the timing pulse TP has a time width of 6 clocks of the reference clock φ ₁ and a time width of 2 clocks of the divided clock φ ₂ . Therefore, the blocks 1, 2, 3, ... Shown in FIG.
Can be obtained as the output of the latch section 11. In this case, the output terminals 1, 2 of the latch section 11,
The output from 3 becomes the timing waveform shown in block 1, and the output from its output terminals 4, 5, 6 is block 2
The timing waveforms shown in FIG.

The output of the latch unit 11 is used as a strobe signal (hereinafter referred to as STB signal) corresponding to the corresponding LED array chips 2 ₁ to 2
_n is input to the corresponding strobe terminal of the driver portion 703 of the drive IC 7 ₁ to _7-n (STB terminal).

The driving operation of the driver unit 703 of each drive circuit IC is controlled according to the state of the STB signal. For example, the driver unit 703 is driven according to the output result of the latch unit 702 only in the section where the STB signal is at “H” level. The section 703 is activated or deactivated, and as a result, the operation is performed so as to control the energization time of the corresponding LED element.

Further, as shown in FIG. 6, the output of the latch circuit 11 corresponds to the output corresponding to the block 1 (output terminals 1, 2 and 3) and the output corresponding to the block 2 (output terminal 4, according to the divided clock φ ₂ ).
5 and 6 outputs), output corresponding to block 3 (output terminals 7 and 8,
9 outputs), ..., and so on, so LED array A is LED array chips 2 ₁ , 2 ₂ , 2 ₃ (block 1), LED
Array chip 2 _4, 2 _5, 2 ₆ (Block 2), LED array chip 2 _7, 2 _8, 2 ₉ (block 3), if the divided clock phi ₂ is one clock (in other words in each block order ...... , One cycle of the divided clock φ ₂ , that is, T) are sequentially overlapped and driven.

(Effects of the Invention) As described in detail above, according to the present invention, the following advantages can be obtained.

First, since the drive circuit IC is provided for each LED array chip of the LED array head, it is not necessary to electrically isolate the common electrode section between the blocks, and the individual switching elements are not required. High productivity and low cost LE
D array head can be realized.

Second, since no matrix wiring member or space on the individual electrode side between the blocks is required, a small-sized LED array head can be realized at low cost.

Thirdly, since the means for setting the number of LED array chips in one block and the means for setting the timing of starting and ending the energization of each block are provided, variations in the light amount sensitivity of each device in the optical printer device are caused. Can be absorbed with a simple operation.

Fourth, it is possible to reduce the amount of change in the energization current to the LED array by variably setting the chip number setting circuit and the energization time setting circuit so that the energization times between adjacent blocks partially overlap. As a result, the power supply current can be smoothed.

[Brief description of drawings]

1 is a block diagram of an embodiment of the present invention, FIG. 2 is a perspective view of an LED array head, FIG. 3 is a block diagram of a drive circuit IC, FIG. 4 is a block diagram of a chip number setting circuit, and FIG. FIG. 6 is a block diagram of the energization time setting circuit, and FIG. 6 is an operation timing chart of signals of respective parts in FIG. 2 ₁ , 2 ₂ , ..., 2 _n-1 , 2 _n ...... LED array chip, 7 ₁ , 7 ₂ , ...,
7 _n-1 , 7 _n ...... Driving circuit IC, 8 ・ ・ ・ Chip number setting circuit, 9
...... Energization time setting circuit, 10 ...... Shift register, 11 ......
Latch circuit, 701 ... shift register section, 702 ... latch section, 703 ... driver section, 801,901 ... DIP switch, 802,902 ... counter, 903 ... inverter circuit.

Claims (2)

[Claims] 1. The LEs are arranged corresponding to each of a plurality of LED array chips which are arranged in a long shape and whose common electrodes are all electrically commonly connected.
An LED array drive circuit comprising a plurality of drive circuit ICs for applying drive signals to individual electrodes of a D array chip to control the drive of the LED array chip, wherein the plurality of LED array chips are divided into a plurality of blocks. For setting the number N (where N is a positive integer) of LED array chips in each block, and the predetermined reference clock φ ₁ is set to the number of LED array chips in each block, that is, the numerical value N. A chip number setting means for outputting a divided clock φ ₂ that has been divided, and a unit for setting the energization time of the LED array chips in each block, which receives the divided clock φ ₂ and receives the divided clock φ _2. An energization time setting means for setting and outputting a timing pulse TP having a pulse width that is an integer multiple of the cycle T of ₂ as the energization time, and a plurality of output terminals corresponding to each of the drive circuit ICs are provided. The timing pulse TP is used as an input signal, and the input timing pulse is used as the reference clock φ ₁
Shift register means for sequentially shifting in synchronism with each other and outputting from each output terminal thereof, and a plurality of input terminals and a plurality of output terminals corresponding to each of the drive circuit ICs, and from each output terminal of the shift register means Output signal is input from each of the input terminals, the input signal is latched based on the divided clock φ ₂ , and the latched signal is used as a strobe signal from each output terminal of the corresponding drive circuit IC. Latching means for outputting to the strobe terminal of the LED array chip, a shift register section provided corresponding to each of the LED array chips and storing the input print data signals while sequentially shifting the same, and a storage section for storing the shift register section in the shift register section. A latch unit for latching the generated print data signal, the print data signal stored in the latch unit, and the latch unit for storing the print data signal. A drive circuit IC having a driver unit for controlling the drive of a corresponding LED array chip based on a strobe signal input to a servo terminal, wherein the shift register unit of each drive circuit IC is connected in series. A plurality of the above-mentioned drive circuit ICs, and drive-controls each of the LED array chips in the block unit. 2. The setting of the number of LED array chips in a block in the chip number setting means and the setting of the energization time in the energization time setting means partly overlap the energization time between adjacent blocks. The LED array drive circuit according to claim (1), wherein the LED array drive circuit is set.