JP2003054041A - Optical printing head and driver ic used in the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To favorably wire between a driver and a light-emitting element and improve wire bonding characteristics between the light-emitting element and the driver. SOLUTION: There are provided on a circuit board 10, light-emitting elements 22 of a type driven in a time sharing manner having a plurality of common electrodes and a plurality of discrete electrodes 28 corresponding to the number of time divisions, drivers DR for common electrodes which are connected to the plurality of common electrodes, and drivers 1 for discrete electrodes which are connected to the plurality of discrete electrodes. The driver 1 for discrete electrodes has a wiring SL formed to its upper face for connecting between the driver for common electrodes and the plurality of common electrodes. Moreover, the circuit board 20 has wiring patterns IP formed to its upper face for connecting between the drivers DR for common electrodes and the plurality of common electrodes. The wiring patterns IP are set to the opposite side to the light-emitting elements seen from the drivers 1 for discrete electrodes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical print head and a driver IC used therein.

[0002]

2. Description of the Related Art A time-division drive (dynamic type) optical print head has a smaller wire bond density than a static type and can reduce the number of wire bonds. Recently, it has been proposed to make the internal structure of a light emitting element formed by an LED array compatible with time-division driving. That is, a plurality of L's in the light emitting element
The ED is divided into a plurality of groups according to the number of time divisions, and a plurality of common electrodes for selecting this group and individual electrodes for selecting the LEDs in the group are formed on the upper surface of the light emitting element. Then, in correspondence with the time-division drive compatible light emitting element, the driver I for performing the drive
Cs are arranged in a one-to-one correspondence with the light emitting elements (for example, Japanese Patent Laid-Open No. 10-202947).

The driver IC incorporates a common electrode driver (driving section) for selecting a plurality of common electrodes in the light emitting element, so that one IC can drive one light emitting element. ing.

As described above, when each driver IC has a built-in driver for selectively driving the common electrode, a dedicated 1
Compared to the case where two drivers are provided, the current flowing in the circuit that selects the common electrode can be dispersed. However, on the other hand, when the amount of current per LED is large, the light emitting state varies greatly among the light emitting elements depending on the lighting pattern of the light emitting elements, which easily causes variations in the heat generation state of each driver. However, it adversely affects the characteristics of the driver and causes a disproportionation of the light intensity of the light emitting element. In order to solve this, it is necessary to improve the heat dissipation of the driver IC, and it is necessary to increase the shape of the heat dissipation fin, which tends to lead to an increase in size.

Therefore, in such a case, it is preferable to separately provide a driver for selecting the common electrode. As a case where it is preferable to separately provide a driver for the common electrode, as described above, when the heat generation amount per LED of the light emitting element is large, or the number of time divisions of the light emitting element is relatively small as 2 to 4, There is a case where the ratio of the time-division wiring is small, and a case where it is possible to perform the optimized design by designing according to the required characteristics by separating the driver for the common electrode. it can.

[0006]

The main object of the present invention is to solve various problems in the case where a driver for selecting a common electrode is separately provided as described above. That is, it is an object to satisfactorily perform wiring between the driver and the light emitting element. Another object is to improve wire bond characteristics between the light emitting element and the driver IC. Another object is to reduce the adverse effect of the wire bonding wiring on the light emitting state of the light emitting unit and to improve the printing quality of the optical printer incorporating this optical printer head. One of the challenges is to improve the heat problem caused by the heat generated by the driver. Another object is to prevent the width of the light emitting element or the optical print head from increasing.

[0007]

According to a first aspect of the present invention, an optical print head according to the present invention has a light emitting element having a common electrode terminal commonly connected to a plurality of light emitting portions on its upper surface, and driving the light emitting element. And a wiring pattern formed on the upper surface of the driver IC so as to cross the driver IC from the side facing the light emitting element to the opposite side.

According to a second aspect of the present invention, there is provided an optical print head comprising a time division drive type light emitting device having a plurality of common electrodes corresponding to the number of time divisions and a plurality of individual electrodes, and the plurality of common electrodes. And a driver for an individual electrode connected to the plurality of individual electrodes, wherein the driver for the individual electrode has a driver for the common electrode and the plurality of common electrodes on an upper surface thereof. It is characterized in that a wiring for connecting the two is formed.

According to a third aspect of the present invention, there is provided an optical print head in which a time-division drive type light emitting element having a plurality of common electrodes corresponding to the number of time divisions and a plurality of individual electrodes, and the plurality of common electrodes. A common electrode driver connected to the plurality of individual electrodes, and an individual electrode driver connected to the plurality of individual electrodes on a circuit board, the individual electrode driver having the common electrode driver and the driver Wiring for connecting between a plurality of common electrodes is formed, the circuit board,
A wiring pattern for connecting between the driver for the common electrode and the plurality of common electrodes is formed on the upper surface, and this wiring pattern is provided on the side opposite to the light emitting element with the driver for the individual electrode as a reference. It is characterized by being arranged.

The optical print head of the present invention is defined in claims 4 to 7.
The driver for the individual electrode may include an output terminal for a control signal to be given to the driver for the common electrode, and the driver for the common electrode may be provided for the driver for the individual electrode. A signal that is common to the signal can be controlled, and a circuit that controls the driver for the common electrode can be configured by a counter, and the number of signals given to the counter is common to the light emitting elements. It can be smaller than the number of electrodes.

As described in claim 8, the driver IC of the present invention is connected to the individual electrodes of the time division drive type light emitting device having a plurality of common electrodes and a plurality of individual electrodes corresponding to the number of time divisions. The driver IC is characterized in that wiring having terminals for wire bonding at both ends is formed on the upper surface.

According to the ninth and tenth aspects of the driver IC of the present invention, a plurality of sets of the wirings can be formed on the upper surface of the driver 1C, and the wirings can be formed at the central portion in the longitudinal direction of the driver 1C or It can be placed at both ends.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of an essential part showing an example of an optical print head 20 to which the present invention is applied, and FIG. 2 is a circuit block diagram thereof. In this optical print head 20, a plurality of, for example, L = 20 light emitting elements 22 are arranged in a line on an insulating long substrate 21, and the driver IC 1 is arranged adjacent to one side of the light emitting elements 22. One-to-one with the light emitting element 22
Are arranged in a line corresponding to each other. In this example, the driver ICs 1 and the light emitting elements 22 are arranged in a one-to-one relationship, but they may be arranged in a one-to-many relationship. Further, in this example, the driver IC 1 is arranged on one side of the light emitting element 22, but when the driver IC 1 is arranged on both sides of the light emitting element 22, the light emitting element 22 and the driver IC 1 are arranged in a ratio of 1: 2.
It should be arranged according to the correspondence relationship of.

A wiring 23 for connecting the light emitting element 22 and the driver IC 1 is provided between the two. As the wiring 23, a direct connection structure by a wire bond wire such as a gold wire is adopted, but in addition to this, an indirect connection structure by a wire bond wire with a relay pattern interposed or a high-density flexible wiring is used. A structure in which an anisotropic conductive adhesive is used for connection can also be used.

Between the driver IC 1 and the light emitting element 22,
Since there are no wiring patterns IPO1 to IPO4 to be described later, wiring 2
When wire bonding wire 3 is used, its length can be shortened, and a short circuit between adjacent wires can be prevented.

A plurality of types of wiring patterns 24 for signals, power supply, etc. are formed on the substrate 21. Most of the wiring pattern is formed in an elongated shape extending along the arrangement direction of the light emitting elements 22. A wiring 25 similar to the wiring 23 is provided between the driver IC 1 and the wiring pattern 24.

The light emitting element 22 is composed of a monolithic type semiconductor light emitting element, and a plurality of light emitting elements (for example, m × n) are provided on the upper surface thereof.
= 384) light emitting portions 26 each including LEDs are arranged in a line along the longitudinal direction, for example, 1200 DPI (Dot / I).
nch) density (resolution). Each of the plurality of light emitting portions 26 is independently formed so as to be time-divisionally driven, and is divided into a plurality of groups so as to be time-divisionally driven for each group. In this example,
The first, fifth, and ninth light emitting units 26 are the first group, 2, 6, and 10.
As an example, the second group is referred to as a second group, and the number indicating the arrangement order of the light emitting units 26 is divided into four groups based on the number of remainders when divided by 4.

The light emitting element 22 is provided with a plurality (m = 4) of common electrodes 27 in which the light emitting portions 26 belonging to the first to fourth groups are connected in common along the longitudinal direction of the light emitting element 22. ing. The light emitting element 22 is provided with an individual electrode 28 for selecting a plurality of light emitting portions 26 belonging to one group. The individual electrodes 28 are used for the light emitting units 2 belonging to different groups.
6. In this example, 96 light emitting elements 22 are connected to four adjacent light emitting portions 26 (n = 96).
The individual electrodes 28 are arranged in the same direction as the light emitting parts 26. Each common electrode 27 is provided with external extraction terminals 27-1 to 27-4, and is arranged on the same side of the upper surface of the light emitting element 22 as the side on which the individual electrodes 28 are arranged. In this example, the terminals 27-1 to 27-4 are arranged along the row of the individual electrodes 28, but other arrangements may be used.

As shown in FIGS. 1 and 2, the driver IC 1 has a plurality of output terminals DO on the side facing the light emitting element 22.
And a plurality of output terminals CD are arranged. Output terminal CD
The terminal portion 31 including one set of 1 to CD4 is arranged at the center of the long side. The output terminals DO are arranged on both sides of the terminal portion 31 so as to be divided into half each. The terminal portion 31 is
The output terminals CD1 to CD4 are connected to the terminal 2 of the light emitting element 22.
7-1 to 27-4 are connected using wire bond wires. Terminals CDD1 to CDD4 are arranged on the long side opposite to the long side on which the output terminals CD1 to CD4 are provided, and are individually connected to the terminals CD1 to CD4 via the auxiliary wirings SL1 to SL4. The auxiliary wirings SL1 to SL4 having terminals for wire bonding at both ends are made of a metal film such as aluminum provided on the surface of the driver IC 1,
In this example, the driver IC is arranged so as to cross the driver IC in the same direction as the short side of the driver IC.

The circuit board 21 has terminals CDD1 to CDD.
A wiring pattern for giving a signal for selecting a common electrode is formed on each of the four electrodes. This pattern is a driver IC
The island-shaped patterns IPO1 to IPO4 arranged at positions corresponding to one terminal CDD1 to CDD4 and the corresponding island-shaped patterns IPO1 to IPO4 are connected to each other via through holes formed in the island-shaped pattern. It is configured by a pattern (arranged on the edge or the back side of the substrate 21) and the like. A driver (circuit) DR for selecting a common electrode arranged on the periphery or the back surface of the circuit board 21 is connected to these patterns, and the driver DR causes one of the common electrodes 27 to have a predetermined potential, that is, a ground potential in this example. Can be selectively switched to.

The driver DR is composed of a circuit or an IC in which a plurality of transistors or a plurality of FETs are combined, and the signal terminal CS of the driver IC1.
The operation is controlled by control signals output from 1 to CS4 via the wiring patterns IPI1 to 4. Signal terminals CS1 to C for giving control signals to the driver DR
S4 is arranged on the same side as the terminals CDD1 to CDD4 are arranged. The wiring patterns IPI1 to 4 are connected to the driver DR through through holes formed in each of them. In addition, it is desirable that the driver DR is arranged at a location where the substrate 21 excels in heat dissipation.

FIG. 3 shows a circuit block diagram of the driver IC 1.

As shown in FIG. 3, the driver IC 1 is connected to each of the output terminals DO and an individual terminal portion composed of a plurality (n) of output terminals DO for driving the light emitting element (for the individual electrode 28). , A drive unit 2 for giving a predetermined current output as a drive signal to these, and a plurality of (m) auxiliary wirings forming a part (relay pattern) of a circuit for selecting a plurality of groups (m) The common terminal unit COM including SL is provided.

The drive unit 2 includes a data signal storage circuit 4 for temporarily storing serial input data signals sequentially applied via a plurality (r) of data input terminals SI1 to SI4,
A drive circuit 5 that outputs a drive signal to each of the output terminals DO1 to DO96 based on the data signal output from the data signal storage circuit 4, a current supply circuit 6 that supplies a constant current to the drive circuit 5, and a drive unit. 2 and the timing control circuit 7 which supplies a predetermined timing signal to terminals CS1 to 4 described later.

The data signal storage circuit 4 takes in data signals serially input from the data input terminals SI1 to SI4 in synchronization with the clock signal CLK1 and outputs serially from the data output terminals SO1 to SO4 n × m (38).
4) A multi-input shift register 8 having a bit configuration, and an n × m (384) bit configuration in which a data signal captured in the shift register 8 is captured in parallel in n × m (384) bit units based on the load signal LOAD1. Latch circuit 9 of FIG. The n × m (384) data signals output in parallel from the shift register 8 can be supplied to the memory circuit 10 without passing through the latch circuit 9.

When the data signal is composed of a plurality of bits, the configuration of the shift register 8 and the latch circuit 9 can be changed accordingly. For example, the shift register 8 can be an addressing type memory. It can also be configured.

The drive circuit 5 outputs n output from the latch circuit 9.
A first selection circuit 11A for sequentially selecting and outputting data signals in units of n from xm (384) data signals;
A constant current is output through the output terminals DO1 to DO96 based on the output of the first selection circuit 11A.
The first drive circuit 12A having a (96) bit configuration is provided as a basic configuration. In addition to this basic configuration, the drive circuit 5 includes a correction data storage circuit 10 for storing n × m (384) pieces of correction data for accommodating output current correction, and the correction data storage, if necessary. Circuit 10
A second selection circuit 11B for correction data for sequentially selecting and outputting correction data signals in units of n from the n × m (384) correction data signals output from the correction data signal, and a selection circuit for this correction data. A second drive circuit 12B for correction having an n (96) -bit configuration for outputting an output of a current value increased or decreased based on the output of 11B as a drive signal via the output terminals DO1 to DO96 can be provided.

The storage circuit 10 stores, for example, n × m (384) pieces of correction data composed of a plurality of (S) bits (for example, 3 bits) in correspondence with the data signal. A latch circuit having a × n × m bit configuration can be used. Then, the writing of the correction data into each of the correction data storage circuits 10 is performed based on the n × m unit signals supplied in parallel from the shift register 8.

Writing to the correction data storage circuit 10 can be performed in advance. That is, it is possible to perform the operation of storing each bit of the correction data via the shift register 8 a plurality of times (S = 3) with only the storage circuit 10 in the write state.

The drive circuit 12 has one output terminal DO.
On the other hand, a plurality of current amplifiers having different current outputs are set as one set, and the same number as the output terminals DO is provided. The current amplifiers, to which the current is supplied from the current supply circuit 6, individually control the operating states thereof so that the total output current in the lighting state is 3 mA based on 4 mA.
It can be changed within the range of about 5 mA.

The selection circuit 11 selects n × m pieces of data and correction data stored in the latch circuit 9 and the correction data storage circuit 10 for time-division driving in units of n and selects m times. This is a circuit for taking out and is composed of a plurality of logic gate circuits. Opening and closing of the gate of the selection circuit 11 is controlled by a division timing signal generation circuit 14 which constitutes a part of the timing control circuit 7.

The division timing signal generation circuit 14 is
Time division timing (selection timing of the selection circuit)
A circuit for generating division timing signals (DIV1 to 4) based on external signals DIVSEL1 and DIVSEL2 which are one of control signals supplied from the outside so as to define
It can be configured by combining logic gate circuits.
In this way, the division timing generation circuit 14 generates four division timing signals (DIV1 to 4) based on the small number of external signals DIVSEL1 and DIVSEL2, so that the number of control signal terminals connected to the outside can be reduced. The size of the IC can be reduced, and the number of external wires such as wire bond wires can be reduced.

The data for one IC1 (384 pieces of ON / OFF data) stored in the latch circuit 9 are divided into the divided timing signals DIV1 to DIV4 by dividing the divided timing signals DIV1 to DIV4 sequentially switched to the H level. As a result of opening only the connected AND gate circuit, it is selectively output during that time. Similarly, the correction data of the 3-bit structure stored in the correction data storage circuit 10 is also selected as a result of the AND gate circuits being opened in groups of three by switching the division timing signals DIV1 to DIV to H level in sequence. Will be output. The output of the correction data storage circuit 10 is supplied to the drive circuit 12 to selectively operate the current amplifier.

Since there are L (20) light emitting elements 22, the number of light emitting portions 26 of the entire head 20 is L × m × n.
= 20 × 4 × 96 = 7680.

Next, the operation of the optical print head 20 including the operation of the driver IC 1 will be briefly described below. The correction data to be stored in the memory circuit 10 is the light amount correction data obtained in advance for each light emitting unit 26 in order to make the light amount of each light emitting unit 26 of the light emitting element 22 uniform. It is assumed that the data has already been stored in the storage circuit 10.

Data signals (7680) are sequentially applied to the data input terminals SI1 to SI4 of the twentieth driver IC1 in units of r, which are sequentially supplied to the multi-input shift register 8 of each driver IC1 in synchronization with the clock signal CLK1. It is captured. Here, each data input terminal SI1 to SI
The data signal applied to the input terminal 4 is
The 5th and 9th data and the 2nd, 6th and 10th data are input to the input terminal SI2 in advance in a form corresponding to the four groups of light emitting elements. When the input of one driver IC1 to the shift register 8 is completed, the driver I located next to the driver I is output via the output terminals SO1 to SO4.
A data signal is given to the shift register 8 of C1. As described above, since a large number of data signals are input, the data input time can be significantly shortened as compared with the case of one input.

When the data input for one line is completed, the load signal LOAD1 is held at the H level for a predetermined time,
The n × m data signals held in the shift register 8 of each IC 1 are fetched. At this time, load signal L
Since the latch circuit 9 is selected (latched) at the falling edge of OAD1, n × fetched in the shift register 8
The m data signals are simultaneously input to and stored in the latch circuit 9.

Immediately after the load signal LOAD1 is switched from the H level to the L level, the external signal DIVSEL1,
2 are both held at the L level, and only the division timing signal DIV1 output from the division timing generation circuit 14 is at the L level.
Switch from level to H level. Immediately after that, the external strobe signal (inversion STB) indicating the timing of light emission is H level.
The level is maintained at the L level for a predetermined period, and the light emitting element selectively emits light in relation to the level.

By changing the combination of the external signals DIVSEL1 and DIVSEL2, the division timing signal DIV2 can be changed.
Only H can be switched to H level, and likewise D
Only IV3 and DIV4 can be switched to H level.

By switching the division timings DIV1 to DIV4, the position of the data signal selected and output by the selection circuit 11 from the latch circuit 9 or the storage circuit 10 is sequentially switched. For example, the division timing DIV1 selects the first, fifth, ..., 7677th data, and the division timing DIV2 selects the second, sixth ,.
The 78th data is selected.

These data (3 bits of correction data are added if necessary) are given to the drive circuit 12. The drive circuit 12 selectively operates a plurality of current amplifiers based on the data signal and the correction data added thereto to supply the output current to each individual electrode 28 of the light emitting element 22 via the output terminal DO. .

A current corresponding to a data signal or correction data can be supplied to the individual electrodes 28 of all the light emitting elements 22, but only a quarter of the light emitting portions 26 are connected to the ground potential level via the common electrode 27. In this example, only four light emitting units 26 are connected to the strobe signal (inversion S
Light is selectively emitted during the L level period of TB).

When the signals DIV1 to 4 output from the timing control circuit 7 are applied to the terminals CS1 to 4, the driver DR shown in FIG. 2 operates and the terminal CDD1.
To 4 are selectively held at the level of the ground potential. Although the terminals CS1 to CS4 are provided in each driver IC1, only the terminals CS1 to CS4 of one driver IC may be connected to the driver DR. The terminals CDD1 to 4 selectively hold any one of the common electrodes 27 at the ground potential level via the auxiliary wiring SL, the terminals CD1 to CD4, and the like.

An optical printer using the optical print head 20 as a light source for exposure has the above-mentioned quarter.
It is possible to perform one screen of exposure by selectively emitting light for one line by time-division driving by switching each of them, and sequentially repeating this.

In the above embodiment, the terminals CDD1 to CDD4 are arranged so as to be located at the center of the long side of the driver IC1.
Although the auxiliary wiring SL and the terminal CD on the opposite side are also arranged in the center in the same manner, the position and the number of the auxiliary wiring SL can be changed, for example, by forming a plurality of auxiliary wirings SL as schematically shown in FIGS. .

In FIG. 4, there are two sets of auxiliary wirings SL, one end of the auxiliary wiring SL is arranged at both ends of one long side of the driver IC 1, and the other end of the auxiliary wiring SL is arranged on the other long side. An example is shown in which it is arranged at a position slightly inward of both end portions. Here, the length slightly inward in the longitudinal direction can be set to a length necessary to avoid the terminal portions SI and SO provided at both ends for transmitting and receiving signals between the adjacent driver ICs 1.

In FIG. 5, there are two sets of auxiliary wirings SL, one end of the auxiliary wiring SL is arranged at both ends of one long side of the driver IC 1, and the other end of the auxiliary wiring SL is arranged on the other long side. An example is shown in which the driver IC 1 is arranged at both ends and at a position slightly inward of both ends in the short side direction of the driver IC 1. Here, the length slightly inward of both ends in the short side direction should be a length necessary to avoid the terminal portions SI and SO provided at both ends for exchanging signals between the adjacent driver ICs 1. Can be done.

In FIG. 6, two sets of auxiliary wirings SL are provided, one end of the auxiliary wiring SL is arranged at both ends of one long side of the driver IC 1, and the other end of the auxiliary wiring SL is arranged on the other long side. An example of arranging at both ends is shown. Here, the terminal portions SI and SO at both ends, which are provided for exchanging signals between the adjacent driver ICs 1, are arranged inside the terminals so as to avoid the terminals CDD1 to CDD4.

The patterns IPO1 to 4 connected to the terminals CDD1 to CDD4 are, as shown in FIGS.
It is also possible to form a plurality of strip-shaped patterns that extend along the driver IC 1 by being located on the front side of 1.

Further, in the above embodiment, the driver DR for selecting the common electrode 27 is arranged outside the IC1, the control signal given to the driver DR is generated inside the driver IC1, and the signal is used. Terminals CS1-4
However, as shown in FIG. 7, a control signal to be given to the driver DR may be generated by an external circuit such as a counter circuit CT provided outside the driver IC1 and the signal may be used. Here, the external circuit for generating the control signal given to the driver DR is the driver I
In order to ensure the synchronization with C1, the same control signal as the control signal given to the driver IC1 is commonly given. This commonly given signal is
For example, it is preferable to use the number of control signals smaller than the number of time divisions (m) in the light emitting element 22 in order to reduce the number of signal patterns.

As described above, each driver IC1 is provided outside the IC, and the driver DR for selecting and driving the common electrode is provided.
Since it is used together with this, it is possible to solve the heat problem when the driver DR is built in each IC 1.

Further, the optical print head 20 is capable of inputting a data signal for one line in one processing operation, although it is configured to perform time-division driving, so that the division performed as in the conventional circuit is performed. The process of repeatedly inputting the data signal for the same number of times is unnecessary. In particular,
Since the number of groups (m) and the number of data input terminals (r) are set to be the same, the data can be distributed in advance for each group and data can be input, and the data input process and the like can be easily executed. I can.

Even if the number of time divisions is increased, the timing (division timing signal) for time division is generated by using the supply lines of control signals smaller than the number of time divisions. It is possible to reduce the number of terminals and the number of assembly work.

Further, the terminals 27-1 to 27-4 provided on the common electrode 27 of the light emitting element 22 are connected to the row of the light emitting sections 26 with respect to
Since it is arranged on the same side as the individual electrode 28, the terminals 27-1 to 27-
It is possible to reduce the width of the light emitting element 22 by the amount corresponding to the arrangement space of 4 and the width of the optical print head 20.

The present invention is not limited to the above-mentioned embodiments, and the species can be changed without departing from the spirit of the present invention, and can be applied to forms other than the above-mentioned embodiments.

[0056]

According to the present invention, it is possible to provide an optical print head in which wiring between a driver and a light emitting element is favorably performed. Further, since the distance between the light emitting element and the driver can be shortened, the wire bond characteristic can be improved. Further, since the wiring for the individual electrodes and the wiring for the wire bonding of the common electrode can be performed in the same manner, the wire bonding can be performed uniformly. As a result, it is possible to reduce the adverse effect of the light reflected by the wire on the print quality and improve the print quality of the printer. Further, it is possible to improve the heat problem due to the heat generation of the driver. as a result,
The mechanism for heat dissipation can be simplified, and the size can be reduced.

[Brief description of drawings]

FIG. 1 is a plan view of essential parts of an optical print head showing an embodiment of the present invention.

FIG. 2 is a main circuit block of the optical print head.

FIG. 3 is a block diagram of a driver IC showing an embodiment of the present invention.

FIG. 4 is a plan view of an essential part of an optical print head showing another embodiment of the present invention.

FIG. 5 is a plan view of a main part of an optical print head showing another embodiment of the present invention.

FIG. 6 is a plan view of an essential part of an optical print head showing another embodiment of the present invention.

FIG. 7 is a circuit block diagram of an essential part of an optical print head showing another embodiment of the present invention.

[Explanation of symbols]

1 driver IC 20 optical print head 22 Light emitting element SL auxiliary wiring

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Mitsuhiro Ozen             3-201 Minamiyoshikata, Tottori City, Tottori Prefecture Tottori             Sanyo Electric Co., Ltd. F-term (reference) 2C162 AE28 AE47 AH04 AH27 AH54                       AH83 FA04 FA17 FA23

Claims (10)

[Claims] 1. A light emitting element having a terminal of a common electrode commonly connected to a plurality of light emitting portions on an upper surface thereof, a driver IC for driving the light emitting element, and a side opposite to the driver IC facing the light emitting element. Driver IC so that it crosses
And an interconnection pattern formed on the upper surface of the optical print head. 2. A time-division drive type light emitting element having a plurality of common electrodes and a plurality of individual electrodes corresponding to the number of time divisions, a driver for a common electrode connected to the plurality of common electrodes, and the plurality of individual electrodes. A driver for an individual electrode connected to an electrode, and a wiring for connecting the driver for the common electrode and the plurality of common electrodes is formed on an upper surface of the driver for the individual electrode. An optical print head featuring. 3. A time division drive type light emitting element having a plurality of common electrodes and a plurality of individual electrodes corresponding to the number of time divisions, a driver for a common electrode connected to the plurality of common electrodes, and the plurality of individual electrodes. A driver for an individual electrode connected to an electrode is provided on a circuit board, and the driver for the individual electrode has a wiring formed on its upper surface for connecting between the driver for the common electrode and the plurality of common electrodes. And a wiring pattern for connecting between the driver for the common electrode and the plurality of common electrodes is formed on the upper surface of the circuit board, and the wiring pattern is based on the driver for the individual electrode. An optical print head, which is arranged on the side opposite to the light emitting element. 4. The optical print head according to claim 2, wherein the driver for the individual electrode includes an output terminal for a control signal supplied to the driver for the common electrode. 5. The light according to claim 2, wherein the driver for the common electrode is controlled by a circuit to which a signal common to the signal for the driver for the individual electrode is applied. Print head. 6. The optical print head according to claim 5, wherein the circuit that controls the driver for the common electrode is configured by a counter. 7. The optical print head according to claim 6, wherein the number of signals given to the counter is smaller than the number of common electrodes of the light emitting element. 8. A driver IC connected to the individual electrodes of a time-division drive type light-emitting element having a plurality of common electrodes and a plurality of individual electrodes corresponding to the number of time divisions, and terminals for wire bonding at both ends. A driver IC characterized in that a wiring having the above is formed on the upper surface. 9. The driver I according to claim 8, wherein a plurality of sets of the wiring are formed on the upper surface of the driver 1C.
C. 10. The driver IC according to claim 8, wherein the wiring is arranged at a central portion or both end portions in the longitudinal direction of the driver 1C.