JPH03104739U - - Google Patents
Info
- Publication number
- JPH03104739U JPH03104739U JP1286790U JP1286790U JPH03104739U JP H03104739 U JPH03104739 U JP H03104739U JP 1286790 U JP1286790 U JP 1286790U JP 1286790 U JP1286790 U JP 1286790U JP H03104739 U JPH03104739 U JP H03104739U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- circuit board
- flexible circuit
- mounting structure
- annular substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 5
- 239000000945 filler Substances 0.000 claims 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
Description
第1図は、実施例の実装構造を示す斜視図、第
2図は、実施例の実装構造を示す断面図、第3図
は、多層の実装構造を示す断面図、第4図は、耐
湿性の実装構造を示す断面図、第5図は、従来の
実装構造を示す断面図、第6図は従来の実装構造
におおける接続不良を示す断面図である。 11……フレキシブル回路基板、12,12a
,12b……(フレキシブル回路基板の)配線回
路、13……半導体素子実装部、18……環状基
板、18a……内側空間、20……(環状基板の
)配線回路、25……充填材、30……半導体素
子。
2図は、実施例の実装構造を示す断面図、第3図
は、多層の実装構造を示す断面図、第4図は、耐
湿性の実装構造を示す断面図、第5図は、従来の
実装構造を示す断面図、第6図は従来の実装構造
におおける接続不良を示す断面図である。 11……フレキシブル回路基板、12,12a
,12b……(フレキシブル回路基板の)配線回
路、13……半導体素子実装部、18……環状基
板、18a……内側空間、20……(環状基板の
)配線回路、25……充填材、30……半導体素
子。
Claims (1)
- 【実用新案登録請求の範囲】 (1) フレキシブル回路基板に半導体素子を実装
する構造であつて、 前記フレキシブル回路基板上でかつ半導体素子
実装部の周囲に、前記フレキシブル回路基板より
可撓性の小さい環状基板を用けたことを特徴とす
る半導体素子の実装構造。 (2) 前記半導体素子の実装構造であつて、 配線回路を形成した前記環状基板を前記フレキ
シブル回路基板上に設けるとともに前記環状基板
の配線回路と前記フレキシブル回路基板の配線回
路とを電気的に接続したことを特徴とする請求項
1記載の半導体素子の実装構造。 (3) 前記半導体素子実装部に実装した半導体素
子の周囲に充填材を形成したことを特徴とする請
求項1又は請求項2記載の半導体素子の実装構造
。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1286790U JPH03104739U (ja) | 1990-02-13 | 1990-02-13 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1286790U JPH03104739U (ja) | 1990-02-13 | 1990-02-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03104739U true JPH03104739U (ja) | 1991-10-30 |
Family
ID=31516314
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1286790U Pending JPH03104739U (ja) | 1990-02-13 | 1990-02-13 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03104739U (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006028155A1 (ja) * | 2004-09-08 | 2006-03-16 | Nec Corporation | モジュール型電子部品及び電子機器 |
JP2007081108A (ja) * | 2005-09-14 | 2007-03-29 | Yaskawa Electric Corp | 半導体チップの積層構造とそれを用いた半導体装置 |
-
1990
- 1990-02-13 JP JP1286790U patent/JPH03104739U/ja active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006028155A1 (ja) * | 2004-09-08 | 2006-03-16 | Nec Corporation | モジュール型電子部品及び電子機器 |
JP2007081108A (ja) * | 2005-09-14 | 2007-03-29 | Yaskawa Electric Corp | 半導体チップの積層構造とそれを用いた半導体装置 |