JPH0294660A - Variable capacity type semiconductor device - Google Patents

Abstract

PURPOSE:To absorb an irregularity in capacity during a manufacturing process by a method wherein a structure where a dielectric film on a semiconductor substrate is sandwiched between electrode films and a P-N junction structure are connected in series to form a capacitor, and a reverse bias voltage for capacity control use is applied to the P-N junction. CONSTITUTION:A capacity formation part is formed of a structure where a first capacitor of a MIS(Metal Insulator Semiconductor) structure in which a nitride film 4 has been sandwiched between a P-type semiconductor region 3 and polysilicon 5 as electrode materials is connected in series with a second capacitor composed of a junction capacitor by a P-N junction structure of an N-well region 2 and the P-type semiconductor region 3. A composite capacity of a whole double structure of this semiconductor device, i.e., a capacity between the polysilicon 5 and the N-well region 2, is controlled by applying a voltage for capacity control use to an aluminum wiring part 6 and an aluminum wiring part 7 and by changing a junction capacity in such a way that a P-N junction between the N-well region 2 and the P-type semiconductor region 3 is reverse- biased. Thereby, it is possible to adjust a capacity value even after a manufacturing process.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a variable capacitance type semiconductor device that is effective in absorbing variations in element capacitance during semiconductor manufacturing, and is particularly applicable as a capacitor for phase compensation of an operational amplifier. Start using the
The present invention relates to a variable capacitance type semiconductor device suitable for adjusting the time constant of an integrating circuit, the coefficients of an active filter, etc., and optimizing circuit characteristics.

[Prior Art] Conventionally, as shown in FIG. 6, as a technique for forming a capacitor element on a semiconductor substrate, each layer of a dielectric material 23 and an electrode 22 is formed on a semiconductor substrate 24,
Terminals 27 and 2 are provided on the electrode 22 and the semiconductor substrate 24, respectively.
8 to form a capacitor. Furthermore, as shown in FIG. 7, there is a method in which an N-type semiconductor 25 is formed on the surface of a P-type semiconductor 26 and a depletion layer region formed at the boundary between the two is used. Terminals 29 and 30 are respectively taken out from the back side of 26 to form a capacitor element.

[Problems to be Solved by the Invention] However, in any of the above techniques, the capacitance value cannot be controlled after the capacitor structure is formed.For example, in a capacitor element having the structure shown in FIG. Since the capacitance is determined by the area of the electrode 22 and the thickness of the dielectric 23, which are the manufacturing conditions, the capacitance cannot be varied during use.Furthermore, in the capacitor element having the structure shown in FIG. Since the width of the depletion layer changes depending on the change in the reverse bias voltage between the N-type semiconductor 25 and the P-type semiconductor 26, the capacitance has reverse bias voltage dependence. Since the area to which the voltage is applied is itself a region forming a capacitor element, it is not possible to control the capacitance from the outside.

The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide a variable capacitance type semiconductor device whose capacitance value can be adjusted to optimize the circuit characteristics even after the integrated circuit is manufactured.

[Means for Solving the Problems] A variable capacitance type semiconductor device according to the present invention includes a first semiconductor device having a dielectric film disposed on a semiconductor substrate and an electrode film formed over the dielectric film. a capacitor element, a first conductivity type layer formed on the surface of the semiconductor substrate, and a second conductivity type layer forming a PN junction with the first conductivity type layer, connected in series with the first capacitor element. It is characterized by comprising a second capacitor element and means for applying a reverse bias voltage to the PN junction.

[Operation] In the present invention, the first capacitor element has a structure in which a dielectric film formed on a semiconductor substrate is sandwiched between electrodes, and the second capacitor element formed on the surface of the semiconductor substrate has a PN junction. have Since the first and second capacitor elements are connected in series, the depletion layer width of the PN junction can be adjusted by changing the reverse bias voltage applied to the PN junction. The capacitance of the first and second capacitor elements as a whole can be optimally controlled.

[Example] Next, an example of the present invention will be described with reference to the accompanying drawings. 1 and 2 are diagrams showing the main parts of the first embodiment of the present invention, in which FIG. 1 is a plan view showing the pattern of each layer on the substrate surface, and FIG. This embodiment, which is a cross-sectional view taken along the line -■, is MOS FET (
Metal Oxide Semiconductor
Field Effect Transistor >
This is an example of forming a variable capacitance type capacitor in the manufacturing process of . The semiconductor device has an N-well region 2 of an N-type semiconductor on the surface of a P-type semiconductor substrate 1, and a P-type semiconductor region 3 inside the N-well region 2. The N-well region 2 and the P-type semiconductor region 3 are formed in an element formation region surrounded by a LOCO8 oxide film 8 formed on the surface of the semiconductor substrate 1.

Further, on the upper surface of the substrate l, a dielectric nitride film 4 and an electrode material polysilicon 5 are laminated and patterned. The entire surface is covered with a glass insulating film 9, and an aluminum interconnect 6 is bonded to the N-well region 2 through openings provided at appropriate locations, and an aluminum interconnect a7 is bonded to the P-type semiconductor region 3. There is.

Further, as shown in FIG. 2, the junction between the N-well region 2 and the aluminum wiring 6 and the junction between the P-type semiconductor region 3 and the aluminum wiring 7 are spaced apart in the width direction so as to sandwich the polysilicon 5. It is formed to extend along the longitudinal direction of polysilicon 5. On the other hand, polysilicon 5
is formed to extend to a position outside the area immediately above the P-type semiconductor region 3, and the polysilicon 5 and the aluminum interconnection R10 are bonded at this position.

In the semiconductor device constructed in this way, the nitride film 4 is separated from the P-type semiconductor region 3 and the polysilicon 5 which are the electrode materials.
M I S (MetalInsulato
r Sem1conductor) 111 structure first
A capacitor forming portion having a structure in which the capacitor 1 and a second capacitor constituted by a junction capacitance formed by a PN junction structure of an N well region 2 and a P type semiconductor region 3 are connected in series is obtained.

The combined capacitance of the entire double structure of this semiconductor device, that is, the capacitance between the polysilicon 5 and the N-well region 2, is such that the PN junction between the N-well region 2 and the P-type semiconductor region 3 is reverse biased. As such, the junction capacitance is controlled by applying a capacitance control voltage to the aluminum wiring 6 and the aluminum wiring 7 to change the junction capacitance. For example, when the donor concentration of the N-well region 2 is 10110l6' and the acceptor concentration of the P-type semiconductor region 3 is 10110l8', applying a reverse bias voltage of 0■ between the aluminum wiring 6 and the aluminum wiring 7 causes the depletion layer to The width becomes 0.17 μm, and the junction capacitance becomes approximately 6.2×10−′ F/m”. When a reverse bias voltage of 5 V is applied, the depletion layer width becomes 0.47 μm, and the junction capacitance becomes approximately 2. 3X 10
"-'F/m2.Here, the thickness of the nitride film is 20
Assuming that there are 0 people, the capacity of the MIS structure is approximately 1.2X10
-' F/♂, the total capacity of the semiconductor device is MI
It can be obtained as a series connection of the S structure capacitance and the above junction capacitance, and when the reverse bias voltage is 0■, it is 5.2X10
-' F/♂, 2 when the reverse bias voltage is 5V. lX
10-4 F/m2. In this way, the capacitance control voltage can cause a capacitance change of twice or more.

When analog elements are integrated using semiconductor manufacturing technology, variations in element characteristics during manufacturing can have a significant impact on the characteristics of the intended integrated circuit. In particular, if the variable capacitance type semiconductor device of this embodiment is used to determine the characteristics of differential/integral circuits, active filters, etc. constructed using operational amplifiers, as well as phase compensation of operational amplifiers, suitable capacitance control can be achieved. In addition to being able to absorb manufacturing variations by supplying voltage, it is also possible to actively change circuit characteristics.

Next, an example in which the variable capacitance type semiconductor device according to the embodiment of the present invention is applied to a phase compensation capacitor of an operational amplifier will be described with reference to FIG.

Figure 3 shows a case where an inverting amplifier circuit that is less prone to oscillation is constructed on a semiconductor integrated circuit by using the frequency of the input signal to control the capacitance of variable capacitors C, , c, which perform phase compensation of the operational amplifier 101. It is a schematic diagram.

The signal from the input terminal IN is input to an inverting amplifier with an amplification factor R2/R1 represented by the resistance values of resistors R, , R2, and F/V which converts the frequency into voltage via a capacitor co for cutting DC components. converter 100.

The F/V converter 100 includes a capacitor C for phase compensation.
The amount of phase compensation is optimized by applying a frequency-dependent voltage to the capacitor C1 of I and C2 that constitutes the junction capacitance.

The higher the input frequency of the operational amplifier 101 is, the larger the phase delay becomes and the more likely it is to oscillate. Therefore, it is better to have a larger capacitance for the phase compensation capacitors C, , C, but if the capacitance is too large, the amplification factor will decrease. Appropriate control is necessary to prevent this from occurring.

In this case, according to this embodiment, it is possible to configure an inverting amplifier circuit that has sufficient gain on the low frequency side and increases the phase compensation amount even if it sacrifices some gain on the high frequency side, making it difficult to oscillate. can.

Next, a second embodiment of the present invention will be described.

FIG. 4 is a diagram showing the main part of the second embodiment, and FIG. 4 is a plan view showing the pattern of each layer on the substrate surface, and FIG.
The figure is a sectional view taken along the line V--V in FIG. 4. This embodiment is also an example in which a variable capacitor is formed in the MOSFET manufacturing process. The semiconductor device includes an N-well region 1 of an N-type semiconductor formed on the surface of a P-type semiconductor substrate 11.
2, and further has a P-type semiconductor region 13 formed inside this N-well region 12, and on its upper surface, a polysilicon 14 as an electrode material, a nitride film 15 as a dielectric, and a polysilicon 16 as an electrode material. and are laminated together. Then, an opening is provided in the glass insulating film 19 covering the entire surface, and the N-well region 1 is
The aluminum wiring 17 is bonded to 2. In addition, LOCO
The 3 oxide film 18 is an element isolation region, and a semiconductor device is formed in the element formation region surrounded by this LOGO 8 oxide film.

FIG. 4 shows the positional relationship between the N-well region 12 and the aluminum wiring 17, the polysilicon 14 and the aluminum wiring 21, and the polysilicon 16 and the aluminum wiring 20.

The capacitor forming section includes a first capacitor having an MIS structure in which a nitride film 15 is sandwiched between polysilicon 14 and polysilicon 16, and a junction capacitor having a PN junction structure between an N well region 12 and a P type semiconductor region 13. It has a structure in which two capacitors are connected in series.

°The combined capacitance of the entire double structure of the semiconductor device, that is, the capacitance between the polysilicon 16 and the N-well region 12, is such that the PN junction between the N-well region 12 and the P-type semiconductor region 13 is reverse biased. The junction capacitance is controlled by applying a capacitance control voltage to the aluminum wiring 17 and the polysilicon 14 (aluminum wiring 21) to change the junction capacitance.

In this embodiment, after forming the N-well region 12, polysilicon 14 is formed on the entire surface, and boron ions for forming a P-type semiconductor are implanted into the polysilicon 14 in the subsequent process. By etching and buttering and forming the P-type semiconductor region 13 directly under the polysilicon 14 by thermal diffusion, self-alignment of the double structure becomes possible, so the area of the variable capacitance type semiconductor device can be reduced. Can be done.

[Effects of the Invention] As explained above, the present invention forms a capacitor by connecting in series a structure in which a dielectric film on a semiconductor substrate is sandwiched between electrode films and a PN junction. By applying a reverse bias voltage for capacitance control to , it is possible to control the capacitance of the entire double structure capacitor. Therefore, if analog elements are integrated using this variable capacitance type semiconductor device, it is possible to absorb capacitance variations during manufacturing by supplying an appropriate capacitance control voltage, and also to proactively This has the effect that circuits and characteristics can be optimized in a controlled manner.

[Brief explanation of drawings]

FIG. 1 is a plan view of essential parts of the first embodiment of the present invention, FIG. 2 is a sectional view taken along the first line ■-■, and FIG. 3 is a variable capacity type according to the first embodiment of the present invention. FIG. 4 is a circuit diagram showing an application example of a semiconductor device; FIG. 4 is a plan view of a main part of the second embodiment of the present invention;
The figure is a sectional view taken along the line ■--■ in FIG. 4, and FIGS. 6 and 7 are partial sectional views showing the prior art. 1.11. P-type semiconductor substrate, 2,12. N-well area,
3.13; P-type semiconductor region, 4, 15; Nitride film, 5, 1
4,16; Polysilicon, 6.7°17.20,21
; Aluminum wiring, 8, 18; LOCO8 oxide film,
9,19. Insulating film, 22; electrode, 23; dielectric, 24;
Semiconductor substrate, 25; N-type semiconductor, 26; P-type semiconductor

Claims (1)

[Claims] (1) A first capacitor element having a dielectric film disposed on a semiconductor substrate and an electrode film formed over the dielectric film, and a first conductivity type layer formed on the surface of the semiconductor substrate. and a second capacitor element having a second conductivity type layer forming a PN junction with the first conductivity type layer and connected in series with the first capacitor element, and means for applying a reverse bias voltage to the PN junction. A variable capacitance semiconductor device comprising: