JPH029325B2 - - Google Patents
Info
- Publication number
- JPH029325B2 JPH029325B2 JP56104839A JP10483981A JPH029325B2 JP H029325 B2 JPH029325 B2 JP H029325B2 JP 56104839 A JP56104839 A JP 56104839A JP 10483981 A JP10483981 A JP 10483981A JP H029325 B2 JPH029325 B2 JP H029325B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- liquid crystal
- resist
- tantalum
- mim
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004973 liquid crystal related substance Substances 0.000 claims description 43
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 239000011521 glass Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims 2
- 239000000470 constituent Substances 0.000 claims 1
- 229910052715 tantalum Inorganic materials 0.000 description 25
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 22
- 210000002858 crystal cell Anatomy 0.000 description 20
- 238000000034 method Methods 0.000 description 18
- 239000002184 metal Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000010409 thin film Substances 0.000 description 5
- 210000004027 cell Anatomy 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 3
- 150000003481 tantalum Chemical class 0.000 description 3
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1365—Active matrix addressed cells in which the switching element is a two-electrode device
Landscapes
- Physics & Mathematics (AREA)
- Liquid Crystal (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
【発明の詳細な説明】
本発明は液晶表示装置、特に金属−絶縁層−金
属（MIM）のごときスイツチング装置を用いた、
多数マトリツクス表示装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a liquid crystal display device, particularly a liquid crystal display device using a switching device such as a metal-insulator-metal (MIM).
The present invention relates to a method of manufacturing a multiple matrix display device.
液晶を用いた大容量表示装置については従来よ
り各種の検討がなされており、その最も簡単な例
が第１図に示すごとく構成したものである。一連
のデータ線１及びアドレス線２に、さらにそれぞ
れのデータ線とアドレス線の交差点に構成された
液晶セル３とにより成つており、所望の液晶セル
を点燈させる為には、その液晶セルに接続された
データ線とアドレス線との間に液晶を点燈させる
に十分な電圧を加えて行なつた。しかるにこの方
法では、電圧が印加されたデータ線及びアドレス
線に点燈すでき液晶セル以外の液晶セルが接続さ
れており、この液晶セルの一方の電極にも電圧が
印加される事となる。この為に第１図の構成によ
る表示装置では用いる事の出来るデータ線又はア
ドレス線の数は制御され、よく知られている様に
簡単には次の式によりその最大数が表わされる。 Various studies have been made on large-capacity display devices using liquid crystals, and the simplest example is constructed as shown in FIG. It consists of a series of data lines 1 and address lines 2, and a liquid crystal cell 3 formed at the intersection of each data line and address line.In order to turn on a desired liquid crystal cell, it is necessary to A voltage sufficient to turn on the liquid crystal was applied between the connected data line and address line. However, in this method, a liquid crystal cell other than the liquid crystal cell that can be turned on is connected to the data line and address line to which a voltage is applied, and a voltage is also applied to one electrode of this liquid crystal cell. For this reason, in the display device having the structure shown in FIG. 1, the number of data lines or address lines that can be used is controlled, and as is well known, the maximum number can be simply expressed by the following equation.
V2＝V1√８＋１ …(1)
ここでV1は液晶が点燈しない最大印加電圧、
V2は液晶が点燈する最少印加電圧であり、用い
た液晶の種類、セルの構成により変わるが、現在
得られているＮの最大数は20程度しかない。 V 2 = V 1 √8+1 …(1) Here, V 1 is the maximum applied voltage at which the liquid crystal does not turn on,
V2 is the minimum applied voltage at which the liquid crystal turns on, and varies depending on the type of liquid crystal used and the cell configuration, but the maximum number of N that can be obtained at present is only about 20.
この様な液晶表示装置を大容晶化する試みとし
て各液晶セルとデータ線との間にスイツチング素
子を直列に挿入し、実効的なＮの値を高める方法
がある。その１つがスイツチング素子としてトラ
ンジスターを用いたいわゆるアクテイブマトリツ
クス方式である。この方式によれば、スイツチン
グ素子としてトランジスターは完壁であるので前
記１式におけるＮの値はほとんど無限大まで許容
出来る反面、大面積上に多数のトランジスターを
欠陥なく製造しなければならないという極めて困
難な要求を必要とする欠点がある。第２の方法と
してスイツチング素子に金属−絶縁物−金属のサ
ンドイツチ製造（MIM素子）を用いたものがあ
り、前記１式のＮの値を数百程度にする事が可能
であり、この程度の値を有すれば実際上はトラン
ジスターを用いたものと比較してなんら遜色は無
い。このMIM素子の電圧−電流特性を示したも
のが第２回である。横軸ＶがMIM素子の金属−
金属間に印加する電圧であり縦軸が流れる電流で
ある。印加電圧の低い時は電流はほとんど流れず
素子は高抵抗状態であるが、印加電圧Vthを越え
ると低抗状態となり電流が流れる。このVthは用
いた金属及び絶縁層の種類により変わる。 As an attempt to increase the crystal capacity of such a liquid crystal display device, there is a method of inserting switching elements in series between each liquid crystal cell and a data line to increase the effective value of N. One of these is the so-called active matrix system that uses transistors as switching elements. According to this method, since the transistor is perfect as a switching element, the value of N in the above equation 1 can be allowed to be almost infinite, but on the other hand, it is extremely difficult to manufacture a large number of transistors on a large area without defects. It has the disadvantage of requiring extensive requirements. A second method is to use metal-insulator-metal sandwich fabrication (MIM device) for the switching element, and it is possible to reduce the value of N in the above equation 1 to about several hundred. If it has a certain value, it is actually no inferior to one using a transistor. The second part shows the voltage-current characteristics of this MIM element. The horizontal axis V is the metal of the MIM element.
It is the voltage applied between metals, and the vertical axis is the current flowing. When the applied voltage is low, almost no current flows and the element is in a high resistance state, but when the applied voltage exceeds Vth it becomes a low resistance state and current flows. This Vth varies depending on the type of metal and insulating layer used.
このMIM素子を用いて構成した液晶セル従来
における一例を示したものが第３図である。液晶
セルは１対のガラス板４，１２からなり、それら
の間に液晶１０が密封されている。板４，１２の
内表面は良く知られている方法により液晶配向処
理が施されている。液晶１０は電極９及び１１の
間に電圧を印加する事により再配向され光学的特
性に変化が生ずる。このうちの一方の電極９に、
MIM素子が結合されている。すなわち、MIM素
子の一方の電極はセル電極９に接続された８であ
り絶縁層は７、又他方の電極は６である。第３図
からわかる様に電極のパターニング工程は電極６
と、電極８，９の２回のみで良く、又両電極の位
置合わせの精度もそれ程きびしくない為、トラン
ジスターをスイツチング素子として用いた場合に
比べ製造上非常に簡単である。このMIM素子の
構成としては金属はタンタルを、絶縁層としてタ
ンタルを陽極酸化した厚さ約500オングスローム
の五酸化タンタルを用いるのがよく知られた一般
的な方法である。この様に形成されたMIM素子
を用い、液晶セルを構成する場合、液晶セルの一
方の電極９の面積と、絶縁層７を介して２つの金
属８と６が対向する面積との比に最適な値が存在
する。この最適値は液晶と比抵抗とセルの電気容
量及びMIM素子の電気容量とＶ−特性によつ
て決まり、通常電極９の面積はMIMの大きさの
１万信又はそれ以上必要である。つまり液晶セル
を１ミリメートル四角としれ場合のMIMの大き
さは10ミクロンメートル四角又はそれ以下の大き
さにしなければならない。この様に10ミクロンメ
ートルのパターンを例えば５ないし10センチメー
トル四角のごとくの大型表示パネル上に形成する
事は非常に困難な事であり、又、液晶セル電極９
の大きさが１ミリメートル四角というのは表示ド
ツトとしてはかなりきめが粗く、表示品質上この
ドツト面積を数分の１以下に小さくする場合
MIMの大きさも数分の１の大きさにしなければ
ならない。この場合必要とされるパターンサイズ
は５ミクロンメートル以下が必要となり、実現は
不可能である。 FIG. 3 shows an example of a conventional liquid crystal cell constructed using this MIM element. The liquid crystal cell consists of a pair of glass plates 4 and 12, with a liquid crystal 10 sealed between them. The inner surfaces of the plates 4 and 12 are subjected to liquid crystal alignment treatment by a well-known method. By applying a voltage between the electrodes 9 and 11, the liquid crystal 10 is reoriented and its optical properties change. On one of these electrodes 9,
MIM elements are combined. That is, one electrode of the MIM element is 8 connected to the cell electrode 9, the insulating layer is 7, and the other electrode is 6. As can be seen from Figure 3, the patterning process for the electrode is electrode 6.
Since the electrodes 8 and 9 only need to be connected twice, and the accuracy of positioning the two electrodes is not so strict, the manufacturing process is much simpler than when a transistor is used as a switching element. A well-known and common method for constructing this MIM element is to use tantalum as the metal and tantalum pentoxide with a thickness of about 500 angstroms, which is anodized tantalum, as the insulating layer. When constructing a liquid crystal cell using the MIM element formed in this way, the ratio between the area of one electrode 9 of the liquid crystal cell and the area where the two metals 8 and 6 face each other with the insulating layer 7 in between is optimal. values exist. This optimum value is determined by the liquid crystal, resistivity, capacitance of the cell, capacitance of the MIM element, and V-characteristics, and usually the area of the electrode 9 is required to be 10,000 times or more the size of the MIM. In other words, if the liquid crystal cell is 1 mm square, the size of the MIM must be 10 micrometer square or smaller. It is extremely difficult to form a 10 micrometer pattern on a large display panel, such as a 5 to 10 cm square, and also
The size of 1 mm square is quite rough for a display dot, and for display quality reasons, it is necessary to reduce the dot area to a fraction of the original size.
The size of the MIM must also be reduced to a fraction of the size. In this case, the pattern size required is 5 micrometers or less, which is impossible to realize.
本発明は以上の点を鑑みてなされたものであ
り、従来より知られている技術を用い簡単により
小さなMIM素子を製造する方法を提供するもの
である。以下図面により本発明を詳細に説明す
る。 The present invention has been made in view of the above points, and provides a method for easily manufacturing smaller MIM elements using conventionally known techniques. The present invention will be explained in detail below with reference to the drawings.
まず最初にガラス基板上に第１のタンタル層を
形成する。このタンタル層の厚さは従来よく行な
われている3000〜5000オングストローム程度で良
い。次にこのタンタルをIC製造方面で良く知ら
れているフオトエツチング技術を用いて、第４図
の１３のごとくタンタルのパターニングを行な
う。本実施例では第４図の１３の形状からわかる
様に液晶セルの電極とMIM素子の一方の金属電
極とを同じタンタルで同時に作り込む例について
示した。次に第４図の斜視部を除いたガラス基板
上にレジスト材料を形成する。この場合タンタル
薄膜１３の一部は図に示された通り必ずレジスト
が塗布されない様にする、レジストの透布厚さは
通常ICの工程で用いられている１mm程度で良い。
この第４図のＸ−X′で示した位置での基板断面
形状を示したものが第５図ａの断面図である。１
４はガラス板、１５はレジストである。次に第５
図ｂに示される様にレジスト１５をマスクとし
て、レジストにおおわれていないタンタルをエツ
チング除去し、さらにレジストを除去しないまま
タンタルの陽極酸化を行なう。この酸化によつて
五酸化タンタル１６はタンタル１３のエツチング
断面にしか成長しない。次にさらにレジストを残
したまま、第２のタンタル薄膜１７を基板全体に
形成する。この第２のタンタル薄膜１７の膜厚は
第１のタンタル薄膜１３のそれと同一であるのが
最も良く、又、レジスト１５より薄いので第５図
ｃの様にレジスト上に形成されるタンタル層とレ
ジストの無い所に形成されるタンタル層は容易に
分離して形成する事が可能である。さらに又レジ
ストの無い所に形成されたタンタル層１７は絶縁
層の五酸化タンタル１６を介して第１のタンタル
層１３とMIM素子を形成する。最後にレジスト
１５を除去すると同時にレジストの上に形成され
た第２のタンタル薄膜１７を除去すれば第６図に
示された様な構成で、液晶セル電極、MIM素子、
データ線が完成する。この様に第２のタンタル層
を形成パターニングする方法は、ICの製造上良
く知られているリフトオフ法であつて、これによ
り形成された第２のタンタル１７データ線とな
る。以降、液晶表示パネルは従来のものと全く同
一の方法により製造を行なえば良い。 First, a first tantalum layer is formed on a glass substrate. The thickness of this tantalum layer may be approximately 3,000 to 5,000 angstroms, which is conventionally commonly used. Next, this tantalum is patterned as shown at 13 in FIG. 4 using a photoetching technique well known in the field of IC manufacturing. In this embodiment, as can be seen from the shape 13 in FIG. 4, an example is shown in which the electrode of the liquid crystal cell and one metal electrode of the MIM element are made of the same tantalum at the same time. Next, a resist material is formed on the glass substrate excluding the oblique portion shown in FIG. In this case, a portion of the tantalum thin film 13 is made sure not to be coated with resist as shown in the figure, and the thickness of the resist may be about 1 mm, which is normally used in the IC process.
The sectional view of FIG. 5a shows the cross-sectional shape of the substrate at the position indicated by X-X' in FIG. 4. 1
4 is a glass plate, and 15 is a resist. Next, the fifth
As shown in FIG. b, using the resist 15 as a mask, the tantalum not covered by the resist is etched away, and then the tantalum is anodized without removing the resist. Due to this oxidation, tantalum pentoxide 16 grows only on the etched cross section of tantalum 13. Next, a second tantalum thin film 17 is formed over the entire substrate while leaving the resist. It is best that the thickness of this second tantalum thin film 17 is the same as that of the first tantalum thin film 13, and since it is thinner than the resist 15, it is different from the tantalum layer formed on the resist as shown in FIG. 5c. The tantalum layer formed where there is no resist can be easily separated and formed. Furthermore, the tantalum layer 17 formed in the area without resist forms an MIM element with the first tantalum layer 13 via the insulating layer of tantalum pentoxide 16. Finally, if the resist 15 is removed and at the same time the second tantalum thin film 17 formed on the resist is removed, the structure shown in FIG. 6 will be obtained, including the liquid crystal cell electrode, MIM element,
The data line is completed. The method of forming and patterning the second tantalum layer in this way is the lift-off method, which is well known in IC manufacturing, and the second tantalum 17 data line is formed by this method. Thereafter, the liquid crystal display panel may be manufactured using exactly the same method as the conventional one.
以上の様にして製造したMIM素子の大きさは
第４図において斜線を施した領域へ突出したタン
タル層１３の巾と、このタンタルの厚みで決ま
り、フオトエツチングでの最少パターン寸法が10
ミクロンメートルであるとすると、従来方法を用
いた時のMIMの最小方法は10ミクロンメートル
×10ミクロンメートルであり、本発明を実施した
場合、タンタルの厚さを5000オングストロームと
した場合は、10ミクロンメートル×0.5ミクロン
メートルとなり、従来の製造方法に比べ特に微細
パターン加工を必要とせずに20分の１の大きさに
する事が可能である。従つて液晶セルの大きさも
従来の20分の１の大きさ、つまり、約200ミクロ
ン四角のものが実現出来、表示パネルのきめもこ
まかくなつて表示品質上極めて良好なものが可能
になる。又さらに小さな液晶セルが必要である場
合には、タンタル層の厚さを上記の5000オングス
トロームより薄く形成する事により可能となる
等、極めて余裕の大きい製造条件を取る事が出来
る。さらに又、MIM素子の厚みは従来の２分の
１以下であつて凹凸が少なくなり、これは表示パ
ネルの液晶層の厚みがますます薄形化している現
状を考えた場合、非常に有利である等の本発明は
数々のすぐれた特徴を有するものである。 The size of the MIM element manufactured as described above is determined by the width of the tantalum layer 13 protruding into the shaded area in FIG. 4 and the thickness of this tantalum, and the minimum pattern size by photoetching is 10
If the thickness of the tantalum is 5000 angstroms, then the minimum MIM using the conventional method is 10 micron meters x 10 micron meters, and when the present invention is implemented and the tantalum thickness is 5000 angstroms, the minimum MIM is 10 micrometers x 10 micrometers. The size is 0.5 micrometers x 0.5 micrometers, making it possible to make it 1/20th the size of conventional manufacturing methods without requiring special pattern processing. Therefore, the size of the liquid crystal cell can be reduced to one-twentieth of the conventional size, that is, about 200 microns square, and the display panel can be finely textured, making it possible to achieve extremely high display quality. Furthermore, if an even smaller liquid crystal cell is required, this can be achieved by forming the tantalum layer thinner than the above 5000 angstroms, allowing extremely flexible manufacturing conditions. Furthermore, the thickness of the MIM element is less than half that of the conventional one, resulting in less unevenness, which is extremely advantageous considering the current situation where the liquid crystal layer of display panels is becoming thinner and thinner. The present invention has a number of excellent features.
以下本発明は、IC製造工程におけるリフトオ
フ技術を用いて非常に小形のMIM素子を製造す
る方法を提供するものであり、これによりMIM
素子を用いた従来の液晶表示パネルに比べ格段に
小さな液晶セルを可能ならしめ、表示パネルの表
示品質を大巾に向上させるものである。 The present invention provides a method for manufacturing extremely small MIM elements using lift-off technology in the IC manufacturing process, and thereby provides a method for manufacturing extremely small MIM elements.
This enables a much smaller liquid crystal cell compared to conventional liquid crystal display panels using such elements, and greatly improves the display quality of the display panel.
尚、本発明の実施例として液晶セル駆動電極及
びデータ線をMIM素子と同時に作り込むものに
ついて述べたが、MIM素子とは別工程で製造し
ても本発明の主旨をそこなうものでなく、又用い
た金属及び絶縁物も前記実施例に限るものでない
事はいうまでもない。又第５図において、第２の
金属層１７が、レジスト１５の上の部分とレジス
トの無い領域の部分とが接触していない場合は、
レジスト１５を除去せずに表示パネルを組む事も
可能であり、この場合のレジスト１５はIC製造
上用いられるフオトレジスト以外に金属酸化物等
絶縁性物質を用いる事も可能である。 Although the embodiment of the present invention has been described in which the liquid crystal cell drive electrodes and data lines are manufactured at the same time as the MIM element, the gist of the present invention is not impaired even if the liquid crystal cell drive electrodes and data lines are manufactured in a separate process from the MIM element. It goes without saying that the metals and insulators used are not limited to those in the above embodiments. In addition, in FIG. 5, if the second metal layer 17 does not contact the part above the resist 15 and the part in the area where there is no resist,
It is also possible to assemble a display panel without removing the resist 15, and in this case, the resist 15 can be made of an insulating material such as a metal oxide other than the photoresist used in IC manufacturing.
第１図は従来における液晶マトリツクス表示装
置の構成法の一例を示した略図であり、第２図は
MIM素子の電圧−電流特性の一例を示したグラ
フであつて、第３図は従来においてMIM素子を
用いて液晶表示装置の一例を示す部分断面図であ
る。第４図、第５図、第６図は本発明により特
に、MIM素子を製造する製造方法を工程を追つ
て示すそれぞれ、平面図、断面図、斜視図であ
る。
１……データ線、２……アドレス線、３……液
晶セル、４，１２……ガラス板、６……データ線
及びMIM素子の下部電極、７……絶縁層、８…
…MIM素子の上部電極、９……液晶セル駆動電
極、１０……液晶、１１……電極。
Figure 1 is a schematic diagram showing an example of a conventional method of configuring a liquid crystal matrix display device, and Figure 2 is a
FIG. 3 is a graph showing an example of voltage-current characteristics of an MIM element, and is a partial cross-sectional view showing an example of a liquid crystal display device using a conventional MIM element. FIG. 4, FIG. 5, and FIG. 6 are a plan view, a sectional view, and a perspective view, respectively, showing step by step a manufacturing method for manufacturing an MIM device according to the present invention. DESCRIPTION OF SYMBOLS 1... Data line, 2... Address line, 3... Liquid crystal cell, 4, 12... Glass plate, 6... Data line and lower electrode of MIM element, 7... Insulating layer, 8...
... Upper electrode of MIM element, 9 ... Liquid crystal cell drive electrode, 10 ... Liquid crystal, 11 ... Electrode.
Claims (1)
とも該電極をおおつて、該電極より耐酸化性及び
耐触刻性のレジスト部材を形成し、該電極の一部
を露出すべく前記レジスト部材を一部除去し、該
露出した前記電極をエツチング除去した後、該電
極のエツチング断面に陽極酸化等により該電極の
酸化物層を形成し、次に基板全体へ第２の電極部
材を形成した後、前記レジスト部材とともに、該
レジスト部材上に形成された前記第２の電極部材
を除去し、前記第１の電極（又は前記第２の電
極）を液晶駆動電極に、前記第２の電極（又は前
記第１の電極）を液晶駆動電源に接続して成る事
を特徴とする液晶表示装置の製造方法。 ２ 前記レジスト部材と、該レジスト部材上に形
成された前記第２の電極部材とを除去せず液晶表
示装置の構成部材とする事を特徴とする特許請求
の範囲第１項記載の液晶表示装置の製造方法。[Claims] 1. A first electrode is formed on a glass substrate, a resist member having oxidation resistance and etching resistance is formed over at least the electrode, and a part of the electrode is covered with the resist member. After removing a portion of the resist member to expose the exposed electrode and etching away the exposed electrode, an oxide layer of the electrode is formed on the etched cross section of the electrode by anodic oxidation or the like, and then a second layer is applied to the entire substrate. After forming the electrode member, the second electrode member formed on the resist member is removed together with the resist member, and the first electrode (or the second electrode) is used as a liquid crystal drive electrode. A method of manufacturing a liquid crystal display device, characterized in that the second electrode (or the first electrode) is connected to a liquid crystal driving power source. 2. The liquid crystal display device according to claim 1, wherein the resist member and the second electrode member formed on the resist member are used as constituent members of the liquid crystal display device without being removed. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56104839A JPS587125A (en) | 1981-07-03 | 1981-07-03 | Production for liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56104839A JPS587125A (en) | 1981-07-03 | 1981-07-03 | Production for liquid crystal display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS587125A JPS587125A (en) | 1983-01-14 |
| JPH029325B2 true JPH029325B2 (en) | 1990-03-01 |
Family
ID=14391512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56104839A Granted JPS587125A (en) | 1981-07-03 | 1981-07-03 | Production for liquid crystal display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS587125A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62166213A (en) * | 1986-01-17 | 1987-07-22 | Paloma Ind Ltd | Burner head |
-
1981
- 1981-07-03 JP JP56104839A patent/JPS587125A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS587125A (en) | 1983-01-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5234541A (en) | Methods of fabricating mim type device arrays and display devices incorporating such arrays | |
| JPS61185724A (en) | Production for thin film transistor | |
| US5258864A (en) | Method of fabricating MIM device arrays using a single exposure and lift-off process | |
| JPS6349914B2 (en) | ||
| JPH06194688A (en) | Thin-film transistor matrix device and its production | |
| JPH029325B2 (en) | ||
| JP3076483B2 (en) | Method for manufacturing metal wiring board and method for manufacturing thin film diode array | |
| JP3041092B2 (en) | MIM element and manufacturing method thereof | |
| US6157422A (en) | Two-terminal nonlinear element having insulating films of different thickness formed on the flat top surface of a lower electrode | |
| JPH0685255A (en) | Thin film transistor and manufacture thereof | |
| JP3254757B2 (en) | Active matrix type liquid crystal display | |
| JPH07244295A (en) | Liquid crystal display device and its production | |
| JPS58181023A (en) | Manufacture of electrooptic device | |
| JP2777394B2 (en) | Manufacturing method of nonlinear element | |
| JPH0326367B2 (en) | ||
| JPH08320495A (en) | Liquid crystal display device and its production | |
| JPH06308539A (en) | Production of matrix array substrate | |
| JP2845929B2 (en) | Manufacturing method of nonlinear element | |
| JPH0720501A (en) | Nonlinear resistive element and its production | |
| JPH0836194A (en) | Nonlinear resistance element and its production | |
| JPH05323340A (en) | Selective etching method for anodically oxidized film and production of liquid crystal display device by using this method | |
| JPH03189624A (en) | Production of liquid crystal display device | |
| JPH0352277A (en) | Manufacture of nonlinear element | |
| JPS61234076A (en) | Manufacture of thin film transistor array | |
| JPH0462050B2 (en) |