JPH03189624A - Production of liquid crystal display device - Google Patents
Production of liquid crystal display deviceInfo
- Publication number
- JPH03189624A JPH03189624A JP1330334A JP33033489A JPH03189624A JP H03189624 A JPH03189624 A JP H03189624A JP 1330334 A JP1330334 A JP 1330334A JP 33033489 A JP33033489 A JP 33033489A JP H03189624 A JPH03189624 A JP H03189624A
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- JP
- Japan
- Prior art keywords
- film
- insulating film
- electrode
- metal
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000003647 oxidation Effects 0.000 claims abstract description 9
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 9
- 239000003795 chemical substances by application Substances 0.000 claims description 8
- 239000010407 anodic oxide Substances 0.000 claims description 6
- 230000000873 masking effect Effects 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 abstract 2
- 239000010408 film Substances 0.000 description 62
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 238000000059 patterning Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 239000007864 aqueous solution Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000029305 taxis Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は金属−絶縁膜−金属構造を持つ非線形性抵抗特
性を有する素子（以下ＭＩＭ素子と呼ぶ）を用いた液晶
表示装置の製造方法に関する。Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a method for manufacturing a liquid crystal display device using an element having a metal-insulating film-metal structure and having nonlinear resistance characteristics (hereinafter referred to as an MIM element). Regarding.
（ロ）従来の技術
従来は、ＭＩＭ素子を用いた液晶表示装置に於て、非選
択点も点灯するという、いわゆるクロストークが生じ、
コントラスト差のない表示になってしまう欠点があった
。(B) Conventional technology Conventionally, in liquid crystal display devices using MIM elements, so-called crosstalk occurs in which non-selected points also light up.
This had the disadvantage that the display had no contrast difference.
そのため、この欠点を解決するために、ＭＩＭ素子の静
電容量を小さくすれば良いことが’Ａ ２５０Ｘ ２４
０ Ｅｌｅｍｅｎｔ Ｌｃｄ Ａｄｄｒｅｓｓｅ
ｄ ｂｙＬａｔｅｒａｌ ＭＩＭＪ Ｊａｐａｎ
Ｄｉｓｐｌａｙ ’８３．１９８３年１０月号Ｐ
Ｐ、 ４０４〜４０７等の論文に明らかにされている。Therefore, in order to solve this drawback, it is sufficient to reduce the capacitance of the MIM element.
0 Element Lcd Address
d by Lateral MIMJ Japan
Display '83. October 1983 issue P
This is clarified in papers such as P., 404-407.
この様な従来例のＭＩＭ素子の断面図を第３図に示し、
その製造方法を述べる。A cross-sectional view of such a conventional MIM element is shown in FIG.
The manufacturing method will be described below.
３０００人厚さのＴａ膜から成る下部電極（１２）を基
板（６）の上にスパッタリング法により形成した後、約
５０００人の厚さのポリイミド膜（８）を下部電極（１
２）の上にフォトリングラフイーにより形成する。（第
１のパターニング）。その後、ポリイミド膜（８）と下
部電極（１２）はドライエツチングされ、斜めの側面を
有する様に第２のバターニングがされる。そして、下部
電極（１２）の側面は陽極酸化されて、厚さ３００〜５
００人の絶縁膜下部（１３）となる。After forming a lower electrode (12) made of a Ta film with a thickness of 3,000 nm on the substrate (6) by sputtering, a polyimide film (8) with a thickness of approximately 5,000 nm is formed on the lower electrode (1).
2) is formed by photophosphorography. (First patterning). Thereafter, the polyimide film (8) and the lower electrode (12) are dry etched and subjected to a second patterning so as to have oblique side surfaces. Then, the side surface of the lower electrode (12) is anodized to a thickness of 300 to 50 mm.
This will be the lower part (13) of the insulating film for 00 people.
その後、画素電極（１）及び上部電極（１５）がフォト
ノソダラフィーにより、それぞれ独立工程に於て形成さ
れる。（第３、第４のパターニング）。従来例ではバタ
ーニングが４回である。Thereafter, the pixel electrode (1) and the upper electrode (15) are formed in independent steps by photonosodraphy. (Third and fourth patterning). In the conventional example, buttering is performed four times.
（ハ）発明が解決しようとする課題
バターニング工程では、ゴミが侵入し易く、ＭＩＭ素子
の特性を不安定にする原因となる。寸カーまた、従来例
のポリイミド膜は陽極酸イヒ膜と比べて、緻密性に於て
劣り、ピンホールが多い。また、ポリイミド膜と絶縁膜
下部は斜めの側面を有するので、製造が複雑となる欠点
を有する。(c) Problems to be Solved by the Invention In the patterning process, dust easily enters, causing the characteristics of the MIM element to become unstable. In addition, conventional polyimide films are less dense and have more pinholes than anodic oxide films. Furthermore, since the polyimide film and the lower part of the insulating film have oblique side surfaces, there is a drawback that manufacturing is complicated.
本発明は従来例と比べ、ＭＩＭ素子の小さい静電容量を
維持し、ＭＩＭ素子の電圧−電流特性におけるオン電流
とオフ電流の十分大きい比を維持し、バターニング回数
を減らし、絶縁膜をより緻密にし、ピンホールを少なく
し絶縁膜の製造を容易にする事を目的とする。Compared to conventional examples, the present invention maintains a small capacitance of the MIM element, maintains a sufficiently large ratio of on-current to off-current in the voltage-current characteristics of the MIM element, reduces the number of buttering times, and improves the insulation film. The purpose is to make the insulating film easier to manufacture by making it denser and reducing pinholes.
（ニ）課題を解決するための手段
本発明のＭＩＭ素子の電極は次のような製造工程を少な
くとも経て形成される。(d) Means for Solving the Problems The electrodes of the MIM element of the present invention are formed through at least the following manufacturing process.
（ａ）基板の上に金属膜を形成した後、マスク剤を塗り
、その後、所定の部分のマスク剤を除去して、該金属膜
を露出させる工程。（ｂ）陽極酸化を行い、前記金属膜
の露出部分の１部を陽極酸化膜から成る絶縁膜上部とし
て基板に垂直に形成し、残りの金属膜を維持して、マス
ク剤を除去する工程。（ｃ）該残りの金属膜以外の金属
膜を除去し、前記残りの金属膜を下部電極として、形成
する工程。（ｄ）再び陽極酸化を行い、前記下部電極の
側面を陽極酸化膜へ変化させ、絶縁膜下部を形成して、
該絶縁膜下部の膜厚を前記絶縁膜上部の膜厚よりも薄く
し、前記絶縁膜上部と前記絶縁膜下部から成る絶縁膜を
形成する工程。（ｅ）該絶縁膜の少なくとも２面に接す
るよう設けた金属膜から成る上部電極及び該上部電極と
接し、前記絶縁膜と離れて設けた画素電極を形成する工
程。(a) A step of forming a metal film on a substrate, applying a masking agent, and then removing the masking agent in a predetermined portion to expose the metal film. (b) A step of performing anodic oxidation, forming a part of the exposed portion of the metal film perpendicularly to the substrate as an upper part of an insulating film made of an anodic oxide film, maintaining the remaining metal film, and removing the masking agent. (c) A step of removing metal films other than the remaining metal film and forming the remaining metal film as a lower electrode. (d) performing anodic oxidation again to change the side surface of the lower electrode to an anodic oxide film to form a lower insulating film;
A step of making the thickness of the lower part of the insulating film thinner than the thickness of the upper part of the insulating film to form an insulating film consisting of the upper part of the insulating film and the lower part of the insulating film. (e) forming an upper electrode made of a metal film provided in contact with at least two surfaces of the insulating film, and a pixel electrode provided in contact with the upper electrode and separated from the insulating film;
（ホ）作用
本発明の前記製造方法により絶縁膜は、すべて陽極酸化
膜から成り、斜めの側面を有しないので緻密であり、ピ
ンホールが少なく製造が容易となる。また、ＭＩＭ素子
を流れる電流は主に絶縁膜下部を通って流れる。(E) Effects According to the manufacturing method of the present invention, the insulating film is entirely made of an anodic oxide film and does not have oblique side surfaces, so it is dense and has few pinholes, making it easy to manufacture. Further, the current flowing through the MIM element mainly flows through the lower part of the insulating film.
（へ）実施例
本発明の実施例を第１図ないし第２図に基づいて説明す
る。(F) Embodiment An embodiment of the present invention will be explained based on FIGS. 1 and 2.
第１図（Ａ）に示す如く、ガラス等の基板（６）の上に
、スパッタリング法で約５３００人のＴａ膜を形成した
後に、レジスト（７）を塗り、最終的にＭ１〜１素子が
形成される部分だけを露光・現像により取り除く。As shown in FIG. 1(A), after forming about 5,300 Ta films by sputtering on a substrate (6) such as glass, a resist (7) is applied, and finally M1-1 elements are formed. Only the formed portion is removed by exposure and development.
第１図（Ｂ）に示す如く、０．０１重量％クエン酸水溶
液中で陽極酸化を行い、レジスト（７）におおわれてい
ない部分だけが酸化されＴａｘｅｓから成る絶縁膜上部
（４）が基板に垂直に形成される。As shown in Figure 1 (B), anodic oxidation is performed in a 0.01% by weight citric acid aqueous solution, and only the portion not covered by the resist (7) is oxidized, and the upper part (4) of the insulating film made of Taxes is attached to the substrate. Formed vertically.
この時、膜厚約５３００人のＴａ膜は膜厚約５０００人
の絶縁膜上部（４）および膜厚約３００人のＴａ膜にな
る。At this time, the Ta film with a thickness of about 5,300 thick becomes the upper insulating film (4) with a thickness of about 5,000 thick and the Ta film with a thickness of about 300 thick.
その後、レジスト（７）の剥離を行う。After that, the resist (7) is removed.
第１図（Ｃ）に示す如く、ドライエツチング法により選
択的にＴａをエツチングし、除去して、所定の形状にＴ
ａをパターニングする。As shown in FIG. 1(C), Ta is selectively etched and removed using a dry etching method to form T into a predetermined shape.
Pattern a.
このとき、下部電極（２）は形成される。At this time, the lower electrode (2) is formed.
第１図（Ｄ）に示す如く、再び０．０１％重量％クエン
酸水溶液中で陽極酸化を行い、膜厚約３００人のＴａ５
ｋｓから成る絶縁膜下部（３）は形成される。As shown in FIG. 1(D), anodic oxidation was performed again in a 0.01% wt% citric acid aqueous solution, and the film thickness was approximately 300%.
A lower insulating film (3) consisting of ks is formed.
第１図（Ｅ）に示す如く、インジューム・錫・酸化物（
Ｉ Ｔｏ）の膜をスパッタリング法で形成した後、所定
の形状にパターニングして画素電極（１）が形成される
。As shown in Figure 1 (E), indium, tin, oxide (
After forming a film of I To) by sputtering, it is patterned into a predetermined shape to form a pixel electrode (1).
第１図（Ｆ）に示す如く、Ｃｒ膜をスパッタリング法で
形成した後、所定の形状にパターニングして、上部電極
（５）が形成され、ＭＩＭ素子が完成する。As shown in FIG. 1(F), a Cr film is formed by sputtering and then patterned into a predetermined shape to form an upper electrode (5), completing the MIM element.
次に第１図（Ｆ）に示す如く、本発明のＭＩＭ素子の構
成を以下にまとめて明らかにする。Next, as shown in FIG. 1(F), the structure of the MIM element of the present invention will be summarized and explained below.
膜厚約３００人のＴａ膜から成る下部電極（２）が基板
（６）の上に形成される。膜厚約５０００人のＴａｇＯ
６膜から成る絶縁膜上部（４）が下部電極（２）の上に
形成される。膜厚約３００人のＴａ＊Ｏｓ膜から成る絶
縁膜下部（３）が下部電極（２）の側面に形成される。A lower electrode (2) consisting of a Ta film with a thickness of approximately 300 nm is formed on the substrate (6). TagO film thickness approximately 5000 people
An upper insulating film (4) consisting of six films is formed on the lower electrode (2). A lower insulating film (3) made of a Ta*Os film with a thickness of approximately 300 nm is formed on the side surface of the lower electrode (2).
Ｃｒ膜から成る上部電極（５）が縁膜下部（３）と絶縁
膜上部（４）のそれぞれの側面に沿って画素ＴＬ極（１
）と電気的に結ばれて形成される。An upper electrode (5) made of a Cr film is connected to the pixel TL pole (1) along each side of the lower edge film (3) and the upper insulating film (4).
) and are electrically connected to each other.
次に第２図に、一画素分のＭＩＭ素子の静電容量の等価
回路を示す。Next, FIG. 2 shows an equivalent circuit of the capacitance of the MIM element for one pixel.
ここでＣ１とＣ１はそれぞれ絶縁膜上部（４）と絶縁膜
下部（３）の静電容量を示す。ＣＭＩＭを絶縁膜上部（
４）と絶縁膜下部（３）からなる絶縁膜の静電容量とす
ると、ＣＭＩＭ＝ Ｃ＋ ＋ Ｃ＊となる。Here, C1 and C1 represent the capacitances of the upper part (4) of the insulating film and the lower part (3) of the insulating film, respectively. Place the CMIM on the top of the insulating film (
4) and the capacitance of the insulating film consisting of the lower part of the insulating film (3), CMIM=C+ + C*.
一般に、Ｃ＝εＳ／ｄである。ここに、Ｃは静電容量、
εは誘電率、ｄは対向金属の距離、Ｓは対向金属の面積
である。Generally, C=εS/d. Here, C is capacitance,
ε is the dielectric constant, d is the distance between the opposing metals, and S is the area of the opposing metals.
Ｃ１とＣ２を比較すると、ＣＩの面積Ｓの方がＣ１のＳ
よりもはるかに大きいのでＣ，＞Ｃ，従ってＣＭＩＭ＝
Ｃ＋ ＋ ＣｓＬ：ｔＣ＋となる。Comparing C1 and C2, the area S of CI is larger than the area S of C1.
Since it is much larger than C, > C, therefore CMIM=
C+ + CsL: tC+.
そこで、本発明のＣ２と従来例の０１を比較すると、ｄ
は、両方共約５０００人で同じであり、Ｓも然んど同じ
であるが、εは本発明のＴａ５Ｏｉ膜の方が従来例のポ
リイミド膜よりも２倍程大きい。Therefore, when comparing C2 of the present invention and 01 of the conventional example, d
are both about 5,000 people and the same, and S is also the same, but ε is about twice as large in the Ta5Oi film of the present invention as in the conventional polyimide film.
従がって２倍程度の違いであるので本発明のＭＩＭ素子
の静電容量は従来例のそれと大差がないと言える。Therefore, since the difference is about twice, it can be said that the capacitance of the MIM element of the present invention is not much different from that of the conventional example.
次に、ＭＩＭ素子のＴａ＊Ｏｓ薄膜を流れる電流はＰｏ
ｏｌ−Ｆｒｅｎｋｅｌｉｉ流に従って次式で表わされる
。Next, the current flowing through the Ta*Os thin film of the MIM device is Po
It is expressed by the following formula according to the ol-Frenkelii style.
１＝ｅＶｅｘｐ（βＶ”’）、 β＝（ｑ”／ｒｔ、
ｔ＋ｄ）’°’ ／ｋＴここで、ｄは絶縁膜の厚さ、ε
ｉは絶縁膜の光学的比誘電率である。1=eVexp(βV"'), β=(q"/rt,
t+d)'°' /kT, where d is the thickness of the insulating film, ε
i is the optical dielectric constant of the insulating film.
ＭＩＭ素子を用いた液晶表示装置で高い画質を実現する
ためにはＭＩＭ素子の電圧−電流特性における、オン電
流とオフ電流の比が十分大きいことが必要である。っま
りβを十分大きくする必要がある。In order to achieve high image quality in a liquid crystal display device using an MIM element, it is necessary that the ratio of on current to off current in the voltage-current characteristics of the MIM element be sufficiently large. Therefore, it is necessary to make β sufficiently large.
本実施例で示した絶縁膜下部の膜厚が約５ｏｏｏ人であ
る場合、絶縁膜下部の膜厚ｄとβ値の関係を実験で求め
ると、以下の表の通りになる。When the thickness of the lower part of the insulating film shown in this embodiment is about 5 mm, the relationship between the film thickness d of the lower part of the insulating film and the β value is experimentally determined as shown in the table below.
一般に、高い画質を実現するには、βが４以上が良いの
でｄは３００Å以下が望ましい。Generally, in order to achieve high image quality, β is preferably 4 or more, so d is preferably 300 Å or less.
また、本実施例のｄと従来例のｄは同じであるのでβも
ほぼ同じである。従がって本実施例も従来例と同じ程度
のオン電流とオフ電流の高い比が得られる。Further, since d in this embodiment is the same as d in the conventional example, β is also almost the same. Therefore, this embodiment also provides a high ratio of on-current to off-current comparable to that of the conventional example.
次に、本発明の他の実施例を述べる。Next, other embodiments of the present invention will be described.
基板上に形成される金属膜としてＮｂ、 Ｔｉ。Nb and Ti are used as the metal film formed on the substrate.
Ｃｒ、Ｚ ｒ、Ｗ、Ｍｏ、Ｎ ｉ等をベースとした耐蝕
性金属から選ばれる。また、マスク剤はレジストやメタ
ルマスク剤等から選ばれ、エツチングの方法として露光
・現像やドライ・エツチング等から選ばれる。It is selected from corrosion-resistant metals based on Cr, Zr, W, Mo, Ni, etc. Further, the mask agent is selected from resist, metal mask agent, etc., and the etching method is selected from exposure/development, dry etching, etc.
（ト）発明の効果
以上述べた様に、本発明に依れば、従来例に比べて以下
の効果が有る。(G) Effects of the Invention As described above, the present invention has the following effects compared to the conventional example.
第一に、ＭＩＭ素子の静電容量は従来例の静電容量と大
差ない程度に維持するとともに、オン電流とオフ電流の
比を従来例と同程度の高い値に維持したままで、バクー
ニング回数を三回と、従来る。First, the capacitance of the MIM element is maintained to the same level as the capacitance of the conventional example, and the ratio of on-current to off-current is maintained at a high value similar to that of the conventional example. three times, as usual.
第二に、絶縁膜は上部及び下部共に陽極酸化により形成
されるので、緻密であり、ピンホールが少ない。従って
、所定静電容量のＭＩＭが安定して得られる。Second, since both the upper and lower parts of the insulating film are formed by anodic oxidation, they are dense and have few pinholes. Therefore, an MIM with a predetermined capacitance can be stably obtained.
第三に、絶縁膜は基板に垂直に形成されるので製造は従
来例より容易になる。Third, since the insulating film is formed perpendicularly to the substrate, manufacturing is easier than in the prior art.
第１図（Ａ）ないしくＦ）は本発明の実施例の製造工程
を明らかにするＭＩＭ素子周辺の断面図を示し、第２図
は１画素分のＭＩＭ素子の静電容量の等価回路を示し、
第３図は従来例のＭＩＭ素子の断面部を示す。
（１）・・・画素電極、（２）、 （１２）・・・下部
電極、（３）、 （１３）・・・絶縁膜下部、（４）・
・・絶縁膜上部、（５）、 （１５）・・・上部電極、
（６）・・・基板、（７）・・・レジスト、（８）・・
・ポリイミド膜。Figures 1 (A) to (F) show cross-sectional views around the MIM element that clarify the manufacturing process of the embodiments of the present invention, and Figure 2 shows an equivalent circuit of the capacitance of the MIM element for one pixel. show,
FIG. 3 shows a cross section of a conventional MIM element. (1)...pixel electrode, (2), (12)...bottom electrode, (3), (13)...insulating film bottom, (4)...
... upper part of the insulating film, (5), (15) ... upper electrode,
(6)...Substrate, (7)...Resist, (8)...
・Polyimide membrane.
Claims (1)
を塗り、その後、所定の部分のマスク剤を除去して、該
金属膜を露出させる工程。 （ｂ）陽極酸化を行い、前記金属膜の露出部分の１部を
陽極酸化膜から成る絶縁膜上部として基板に形成し、残
りの金属膜を維持し、マスク剤を除去する工程。 （ｃ）該残りの金属膜以外の金属膜を除去して、前記残
りの金属膜を下部電極として形成する工程。 （ｄ）再び陽極酸化を行い、前記下部電極の側面を陽極
酸化膜へ変化させ、絶縁膜下部を形成し、該絶縁膜下部
の膜厚を前記絶縁膜上部の膜厚よりも薄くし、前記絶縁
膜上部と前記絶縁膜下部から成る絶縁膜を形成する工程
。 （ｅ）該絶縁膜の少なくとも２面に接するよう設けた金
属膜から成る上部電極、及び、該上部電極と接し、前記
絶縁膜と離れて設けた画素電極を形成する工程。 を少なくとも含むことを特徴とする金属−絶縁膜−金属
構造を有する素子を用いた液晶表示装置の製造方法。(1) (a) A step of forming a metal film on a substrate, applying a masking agent, and then removing the masking agent in a predetermined portion to expose the metal film. (b) A step of performing anodic oxidation to form a portion of the exposed portion of the metal film on the substrate as an upper insulating film made of an anodic oxide film, maintaining the remaining metal film, and removing the masking agent. (c) A step of removing metal films other than the remaining metal film and forming the remaining metal film as a lower electrode. (d) perform anodic oxidation again to change the side surface of the lower electrode to an anodic oxide film, form a lower insulating film, make the lower part of the insulating film thinner than the upper part of the insulating film, and A step of forming an insulating film consisting of an upper part of the insulating film and a lower part of the insulating film. (e) forming an upper electrode made of a metal film provided in contact with at least two surfaces of the insulating film; and a pixel electrode provided in contact with the upper electrode and separated from the insulating film. 1. A method for manufacturing a liquid crystal display device using an element having a metal-insulating film-metal structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1330334A JPH03189624A (en) | 1989-12-19 | 1989-12-19 | Production of liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1330334A JPH03189624A (en) | 1989-12-19 | 1989-12-19 | Production of liquid crystal display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03189624A true JPH03189624A (en) | 1991-08-19 |
Family
ID=18231464
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1330334A Pending JPH03189624A (en) | 1989-12-19 | 1989-12-19 | Production of liquid crystal display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03189624A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6100951A (en) * | 1996-09-30 | 2000-08-08 | U.S. Philips Corporation | Thin-film switching elements for electronic devices and a method of manufacturing the same |
-
1989
- 1989-12-19 JP JP1330334A patent/JPH03189624A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6100951A (en) * | 1996-09-30 | 2000-08-08 | U.S. Philips Corporation | Thin-film switching elements for electronic devices and a method of manufacturing the same |
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