JPH0292934U - - Google Patents

Info

Publication number
JPH0292934U
JPH0292934U JP1989001052U JP105289U JPH0292934U JP H0292934 U JPH0292934 U JP H0292934U JP 1989001052 U JP1989001052 U JP 1989001052U JP 105289 U JP105289 U JP 105289U JP H0292934 U JPH0292934 U JP H0292934U
Authority
JP
Japan
Prior art keywords
package
chip
attached
solder bump
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989001052U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989001052U priority Critical patent/JPH0292934U/ja
Publication of JPH0292934U publication Critical patent/JPH0292934U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの考案による実施例の構成図、第２
図は第１図の実施例を採用したモジユールの構成
図、第３図と第４図はこの考案による他の実施例
の構成図、第５図〜第１５図は従来技術の説明図
、第１６図と第１７図はこの考案による他の実施
例の構成図である。 １……パツケージ、２……電極、３……ハンダ
バンプ、４……ＩＣチツプ、５……ワイヤ、６…
…カバー、７……板、８……突起部、９……ハン
ダペデスタル、１１……基板、１２……ピン、１
３……ＩＣチツプ、１４……ワイヤ、１５……電
極、１６……導体、１７……内部導体、１８……
電極、１９……パツケージ、２０……パツケージ
、２１……電極、２２……ハンダバンプ、２３…
…放熱器、２４……放熱器、３１……フリツプチ
ツプ。 Figure 1 is a configuration diagram of an embodiment according to this invention, Figure 2
1 is a block diagram of a module adopting the embodiment of FIG. 1, FIGS. 3 and 4 are block diagrams of other embodiments based on this invention, FIGS. 5 to 15 are explanatory diagrams of the prior art, and FIGS. FIGS. 16 and 17 are configuration diagrams of other embodiments of this invention. 1...Package, 2...Electrode, 3...Solder bump, 4...IC chip, 5...Wire, 6...
... Cover, 7 ... Plate, 8 ... Protrusion, 9 ... Solder pedestal, 11 ... Board, 12 ... Pin, 1
3...IC chip, 14...wire, 15...electrode, 16...conductor, 17...inner conductor, 18...
Electrode, 19...Package, 20...Package, 21...Electrode, 22...Solder bump, 23...
...Radiator, 24...Radiator, 31...Flip chip.

Claims (1)

【実用新案登録請求の範囲】 １ パツケージ１のＩＣチツプ４取付側の面Ａに
取付けられる熱伝導性のよい板７と、 パツケージ１のＩＣチツプ４取付側の面Ａと反
対側の面Ｂ上に格子状に配列された電極２と、 電極２に形成されるハンダバンプ３と、を備え
ることを特徴とするチツプキヤリア型パツケージ
。 ２ パツケージ１のＩＣチツプ４取付側の面Ａに
取付けられる熱伝導率のよい板３と、 パツケージ１のＩＣチツプ４取付側の面Ａと反
対側の面Ｂ上に格子状に配列された電極２と、 電極２に形成されるハンダバンプ３と、 ハンダバンプ３を形成した面上に設けられる突
起部８とを備えることを特徴とするチツプキヤリ
ア型パツケージ。 ３ パツケージ１のＩＣチツプ４取付側の面Ａに
取付けられる熱伝導率のよい板３と、 パツケージ１のＩＣチツプ４取付側の面Ａと反
対側の面Ｂ上に格子状に配列された電極２と、 電極２に形成されるハンダバンプ３とを備え、 ハンダバンプ３を基板１１側のハンダ９よりも
高融点にしたことを特徴とするチツプキヤリア型
パツケージ。[Claims for Utility Model Registration] 1. A plate 7 with good thermal conductivity attached to surface A of the package 1 on the side where the IC chip 4 is attached, and on a surface B of the package 1 opposite to surface A on the side where the IC chip 4 is attached. A chip carrier type package comprising: electrodes 2 arranged in a grid pattern; and solder bumps 3 formed on the electrodes 2. 2. A plate 3 with good thermal conductivity attached to the surface A of the package 1 on the IC chip 4 mounting side, and electrodes arranged in a grid on the surface B of the package 1 opposite to the surface A on the IC chip 4 mounting side. A chip carrier type package comprising: 2, a solder bump 3 formed on the electrode 2, and a protrusion 8 provided on the surface on which the solder bump 3 is formed. 3 A plate 3 with good thermal conductivity attached to the surface A of the package 1 on the IC chip 4 mounting side, and electrodes arranged in a grid on the surface B of the package 1 opposite to the surface A on the IC chip 4 mounting side. 2; and a solder bump 3 formed on the electrode 2. A chip carrier type package characterized in that the solder bump 3 has a higher melting point than the solder 9 on the substrate 11 side.
JP1989001052U 1989-01-09 1989-01-09 Pending JPH0292934U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989001052U JPH0292934U (en) 1989-01-09 1989-01-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989001052U JPH0292934U (en) 1989-01-09 1989-01-09

Publications (1)

Publication Number Publication Date
JPH0292934U true JPH0292934U (en) 1990-07-24

Family

ID=31200605

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989001052U Pending JPH0292934U (en) 1989-01-09 1989-01-09

Country Status (1)

Country Link
JP (1) JPH0292934U (en)

Similar Documents

Publication Publication Date Title
TW362264B (en) Semiconductor device
JPH0292934U (en)
US6674163B1 (en) Package structure for a semiconductor device
JPS602873U (en) Soldering structure of surface mount transistor
JPS61153374U (en)
JPH07106470A (en) Semiconductor device
JPS6422034U (en)
JPH0338633U (en)
JPH038449U (en)
JPH0559849U (en) Semiconductor element mounting structure
JPS6157536U (en)
JPH01121945U (en)
JPS59109150U (en) IC chip package
JPS6194359U (en)
JPH02114941U (en)
JPH0189752U (en)
JPS60176551U (en) semiconductor equipment
JPS62160540U (en)
JPS6157534U (en)
JPH03120052U (en)
JPS61125054A (en) Semiconductor device
JPH0288240U (en)
JPS5945929U (en) Semiconductor element mounting structure
JPS59146960U (en) hybrid integrated circuit
JPS6457643U (en)