JPH0559849U - Semiconductor element mounting structure - Google Patents
Semiconductor element mounting structureInfo
- Publication number
- JPH0559849U JPH0559849U JP001282U JP128292U JPH0559849U JP H0559849 U JPH0559849 U JP H0559849U JP 001282 U JP001282 U JP 001282U JP 128292 U JP128292 U JP 128292U JP H0559849 U JPH0559849 U JP H0559849U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- circuit board
- mounting structure
- metal fitting
- shape
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Abstract
(57)【要約】
【目的】 半導体素子を回路基板に実装する場合に、電
気的接続距離を最短にし且つ熱的に安定な実装構造を提
供する。
【構成】 半導体素子１の外部接続用電極に半田バンプ
２を形成してフェイスダウンにて回路基板３に実装し、
中央片５ａの中央部に複数の穴６をメッシュ状に形成し
且つ全体の形状を略コ字状に形成した金属金具５を半導
体素子１の上から回路基板３に固定し、半導体素子１と
金属金具５の中央片５ａとの間に良好な熱伝導性を有す
るペースト８を介在させる。これにより半導体素子１で
発生する熱を金属金具５に逃がし熱抵抗の低減をはか
る。
(57) [Summary] [Object] To provide a thermally stable mounting structure with the shortest electrical connection distance when mounting a semiconductor element on a circuit board. [Structure] A solder bump 2 is formed on an external connection electrode of a semiconductor element 1 and mounted on a circuit board 3 face down.
A metal fitting 5 having a plurality of holes 6 formed in a mesh shape in the central portion of the central piece 5a and the overall shape of which is formed in a substantially U shape is fixed to the circuit board 3 from above the semiconductor element 1. The paste 8 having good thermal conductivity is interposed between the metal piece 5 and the central piece 5a. Thereby, the heat generated in the semiconductor element 1 is released to the metal fitting 5 to reduce the thermal resistance.
Description
【０００１】[0001]
本考案は半導体素子の実装構造に関する。 The present invention relates to a semiconductor device mounting structure.
【０００２】[0002]
従来、半導体素子を裸の状態で回路基板に実装する構造としては、図３に示す ように半導体素子５１の回路面を上にして回路基板５２に取り付け、半導体素子 ５１の外部接続用電極５３と回路基板５２に設けられたパターン５４との間に金 ワイヤ５５により接続する方法等のワイヤボンディングにより行う構造（フェイ スアップ）と、図４に示すように、半導体素子５１の外部接続用電極５３に半田 バンプ５６を設け、半導体素子５１の回路面を下にして回路基板５２に取り付け ると同時にパターン５４と半田バンプ５６が接続される構造（フェイスダウン） が一般的に用いられている。 Conventionally, as a structure in which a semiconductor element is mounted on a circuit board in a bare state, as shown in FIG. 3, the semiconductor element 51 is attached to the circuit board 52 with the circuit surface of the semiconductor element 51 facing upward, A structure (phase-up) performed by wire bonding such as a method of connecting a gold wire 55 to the pattern 54 provided on the circuit board 52 and an external connection electrode 53 of the semiconductor element 51 as shown in FIG. A structure (face down) is generally used in which the solder bumps 56 are provided, and the circuit surface of the semiconductor element 51 is attached to the circuit board 52, and at the same time, the pattern 54 and the solder bumps 56 are connected.
【０００３】[0003]
図３に示すフェイスアップの実装構造では、半導体素子が回路基板に直に接続 されているため、回路基板の材質を熱伝導性の良好なものを選択することで、半 導体素子の発熱を回路基板に逃がすことができ熱的に安定である。しかし、半導 体素子の外部接続用電極と回路パターンとの接続距離が長くなるため、使用周波 数が高くなると特性劣化を招き好ましくない。 In the face-up mounting structure shown in Fig. 3, the semiconductor element is directly connected to the circuit board. Therefore, by selecting a material with good thermal conductivity for the circuit board, the semiconductor element heat generation It can be released to the substrate and is thermally stable. However, since the connection distance between the external connection electrode of the semiconductor element and the circuit pattern becomes long, the use of a higher frequency undesirably deteriorates the characteristics.
【０００４】 図４に示すフェイスダウンの実装構造では、半導体素子の外部接続用電極と回 路基板のパターンとの接続距離を最短にすることができるため、高周波帯域での 使用が可能である。しかし、半導体素子の発熱を逃がす経路が接続用半田バンプ のみであるため熱抵抗が高く、消費電力の制約があるという欠点があった。In the face-down mounting structure shown in FIG. 4, since the connection distance between the external connection electrode of the semiconductor element and the pattern of the circuit board can be minimized, it can be used in a high frequency band. However, there is a drawback that the thermal resistance is high and the power consumption is limited because the path through which the heat generated by the semiconductor element is released is only the solder bumps for connection.
【０００５】 本考案の目的は、電気的接続距離を最短にすると共に熱的に安定な半導体素子 の実装構造を提供することにある。An object of the present invention is to provide a thermally stable semiconductor element mounting structure while minimizing the electrical connection distance.
【０００６】[0006]
本考案の半導体素子の実装構造は、外部接続用電極に半田バンプを形成した半 導体素子をフェイスダウンにて回路基板に実装し、略コ字状に形成され且つ中央 部をメッシュ状に形成した金属金具を半導体素子の上部から取り付けて回路基板 に固定し、金属金具の中央部と半導体素子との間に良好な熱伝導性を有するペー ストを介在させている。 According to the semiconductor element mounting structure of the present invention, a semiconductor element having solder bumps formed on electrodes for external connection is mounted face down on a circuit board, and is formed into a substantially U shape and a central portion is formed into a mesh shape. The metal fitting is attached from above the semiconductor element and fixed to the circuit board, and a paste having good thermal conductivity is interposed between the central part of the metal fitting and the semiconductor element.
【０００７】[0007]
次に本考案の実装例について図面を参照して説明する。 Next, an implementation example of the present invention will be described with reference to the drawings.
【０００８】 図１は本考案の一実施例の半導体素子の実装構造の斜視図、図２は図１の縦断 面図である。FIG. 1 is a perspective view of a semiconductor element mounting structure according to an embodiment of the present invention, and FIG. 2 is a vertical cross-sectional view of FIG.
【０００９】 図において、半導体素子１の外部接続用電極には半田バンプ２が形成されてい る。この半導体素子１を回路面を下にしたフェイスダウンにて回路基板３上に搭 載し、加熱することで回路基板３に形成されたパターン４と電気的に且つ機械的 に接続されている。In the figure, solder bumps 2 are formed on the electrodes for external connection of the semiconductor element 1. The semiconductor element 1 is mounted on the circuit board 3 face down with the circuit surface facing down, and is electrically and mechanically connected to the pattern 4 formed on the circuit board 3 by heating.
【００１０】 金属金具５は略コ字状に形成され、中央片５ａの中央部には複数の穴６がメッ シュ状に形成されている。金属金具５の高さは半導体素子１の高さよりも僅かに 高く形成されており、中央片５ａが半導体素子１と接触することのないように形 成されている。The metal fitting 5 is formed in a substantially U shape, and a plurality of holes 6 are formed in a mesh shape at the center of the center piece 5a. The height of the metal fitting 5 is formed to be slightly higher than the height of the semiconductor element 1, and the central piece 5a is formed so as not to come into contact with the semiconductor element 1.
【００１１】 金属金具５の側片５ｂは回路基板１に設けたパターン７に半田付け等によって 固着されている。The side piece 5b of the metal fitting 5 is fixed to the pattern 7 provided on the circuit board 1 by soldering or the like.
【００１２】 回路基板３に実装された半導体素子１の上部に金属金具５を取り付けると共に この金属金具５を回路基板３に固定した後、金属金具５の中央片５ａの中央部に 形成したメッシュ状の穴６から、この中央片５ａと半導体素子１の裏面（図にお ける上面）との間隙に良好な熱伝導性を有するペースト８を押し込んで充填する 。After the metal fitting 5 is attached to the upper part of the semiconductor element 1 mounted on the circuit board 3 and the metal fitting 5 is fixed to the circuit board 3, a metal mesh 5 is formed on the central portion of the central piece 5 a of the metal fitting 5. A paste 8 having good thermal conductivity is pressed and filled into the gap between the central piece 5a and the back surface (top surface in the figure) of the semiconductor element 1 through the hole 6.
【００１３】 上記構造において、半導体素子１から発生する熱は半導体素子１の半田バンプ ２から回路基板３への経路と、半導体素子１の裏面からペースト８を介して金属 金具５への経路を経て放熱される。In the above structure, the heat generated from the semiconductor element 1 passes through the path from the solder bump 2 of the semiconductor element 1 to the circuit board 3 and the path from the back surface of the semiconductor element 1 to the metal fitting 5 via the paste 8. Heat is dissipated.
【００１４】[0014]
以上説明したように本考案の半導体素子の実装構造では、半導体素子と回路基 板との接続が最短距離で行え、且つ半導体素子の発熱を逃がす経路を設けたため 半導体素子からの熱抵抗が低く、消費電力の大きな半導体素子を実装することが でき、また高周波帯域での特性劣化を少なくすることができるという効果を有す る。 As described above, in the semiconductor element mounting structure of the present invention, the connection between the semiconductor element and the circuit board can be made in the shortest distance, and since the path for releasing the heat of the semiconductor element is provided, the thermal resistance from the semiconductor element is low, This has the effect that a semiconductor element with high power consumption can be mounted and the characteristic deterioration in the high frequency band can be reduced.
【図１】本考案の一実施例の半導体素子の実装構造の斜
視図である。FIG. 1 is a perspective view of a mounting structure of a semiconductor device according to an embodiment of the present invention.
【図２】図１の縦断面図である。FIG. 2 is a vertical sectional view of FIG.
【図３】従来の半導体素子の実装構造（フェイスアッ
プ）の斜視図である。FIG. 3 is a perspective view of a conventional semiconductor element mounting structure (face-up).
【図４】従来の半導体素子の実装構造（フェイスダウ
ン）の斜視図である。FIG. 4 is a perspective view of a conventional semiconductor element mounting structure (face down).
１ 半導体素子 ２ 半田バンプ ３ 回路基板 ４，７ パターン ５ 金属金具 ５ａ 中央片 ５ｂ 側片 ６ 穴 ８ ペースト 1 semiconductor element 2 solder bump 3 circuit board 4, 7 pattern 5 metal fitting 5a center piece 5b side piece 6 hole 8 paste
Claims (1)
導体素子をフェイスダウンにて回路基板に実装する半導
体素子の実装構造において、略コ字状に形成され且つ中
央部をメッシュ状に形成した金属金具を回路基板に実装
した半導体素子の上部から取り付けると共に回路基板上
に固定し、金属金具のメッシュ状部分と半導体素子との
間に良好な熱伝導性を有するペーストを介在させたこと
を特徴とする半導体素子の実装構造。1. A semiconductor element mounting structure in which a semiconductor element having a solder bump formed on an external connection electrode is mounted face down on a circuit board. The semiconductor element mounting structure is formed in a substantially U shape and a central portion is formed in a mesh shape. The metal fittings are attached from above the semiconductor element mounted on the circuit board and fixed on the circuit board, and a paste having good thermal conductivity is interposed between the mesh-shaped portion of the metal fittings and the semiconductor element. And the mounting structure of the semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP001282U JPH0559849U (en) | 1992-01-17 | 1992-01-17 | Semiconductor element mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP001282U JPH0559849U (en) | 1992-01-17 | 1992-01-17 | Semiconductor element mounting structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0559849U true JPH0559849U (en) | 1993-08-06 |
Family
ID=11497099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP001282U Pending JPH0559849U (en) | 1992-01-17 | 1992-01-17 | Semiconductor element mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0559849U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017112348A (en) * | 2015-12-17 | 2017-06-22 | ▲き▼邦科技股▲分▼有限公司 | Heat dissipation package device |
-
1992
- 1992-01-17 JP JP001282U patent/JPH0559849U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017112348A (en) * | 2015-12-17 | 2017-06-22 | ▲き▼邦科技股▲分▼有限公司 | Heat dissipation package device |
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