JPH0292210U - - Google Patents
Info
- Publication number
- JPH0292210U JPH0292210U JP65989U JP65989U JPH0292210U JP H0292210 U JPH0292210 U JP H0292210U JP 65989 U JP65989 U JP 65989U JP 65989 U JP65989 U JP 65989U JP H0292210 U JPH0292210 U JP H0292210U
- Authority
- JP
- Japan
- Prior art keywords
- dielectric
- layer
- delay line
- ground electrode
- conductors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 6
- 239000003989 dielectric material Substances 0.000 claims 1
- 239000003365 glass fiber Substances 0.000 claims 1
- 229920001721 polyimide Polymers 0.000 claims 1
- 239000009719 polyimide resin Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 1
Description
第1図は、この考案の一実施例に係る積層形デ
イレイライン素子を示す斜視図である。第2図は
、第1図―に沿う断面図である。第3図は、
第1図のような積層形デイレイライン素子のより
具体例を示す分解斜視図である。第4図は、この
考案の他の実施例に係る積層形デイレイライン素
子を示す斜視図である。第5図は、第4図の積層
形デイレイライン素子の側面図である。第6図は
、第4図のような積層形デイレイライン素子のよ
り具体例を示す分解斜視図である。第7図は、第
6図の積層形デイレイライン素子の製造途中段階
を示す分解斜視図である。第8図は、従来のデイ
レイライン素子の一例を示す概略斜視図である。
10,20…実施例に係る積層形デイレイライ
ン素子、12…伝送線路、13…誘電体、14…
グランド電極、15〜17…スルーホール、18
…導体、25〜27…細溝。
FIG. 1 is a perspective view showing a laminated delay line element according to an embodiment of the invention. FIG. 2 is a sectional view taken along FIG. 1. Figure 3 shows
FIG. 2 is an exploded perspective view showing a more specific example of the laminated delay line element as shown in FIG. 1; FIG. 4 is a perspective view showing a laminated delay line element according to another embodiment of the invention. 5 is a side view of the multilayer delay line element of FIG. 4. FIG. FIG. 6 is an exploded perspective view showing a more specific example of the laminated delay line element as shown in FIG. 4. FIG. 7 is an exploded perspective view showing an intermediate stage of manufacturing the laminated delay line element of FIG. 6. FIG. 8 is a schematic perspective view showing an example of a conventional delay line element. DESCRIPTION OF SYMBOLS 10, 20... Laminated delay line element according to an example, 12... Transmission line, 13... Dielectric, 14...
Ground electrode, 15-17...Through hole, 18
...Conductor, 25-27...Small groove.
Claims (1)
およびグランド電極がこの順でしかも伝送線路が
複数層存在しかつ上下両面がグランド電極になる
ように繰り返して積層されて成り、かつ各層の伝
送線路がスルーホール内の導体を介して互いに直
列に接続されると共にその少なくとも両端が表面
に引き出されており、更に各層および上下両面の
グランド電極が他のスルーホール内の導体を介し
て互いに並列に接続されていることを特徴とする
積層形デイレイライン素子。 (2) グランド電極、誘電体、伝送線路、誘電体
およびグランド電極がこの順でしかも伝送線路が
複数層存在しかつ上下両面がグランド電極になる
ように繰り返して積層されて成り、かつ各層の伝
送線路が端面に設けた溝内の導体を介して互いに
直列に接続されると共にその少なくとも両端が表
面に引き出されており、更に各層および上下両面
のグランド電極が端面に設けた他の溝内の導体を
介して互いに並列に接続されていることを特徴と
する積層形デイレイライン素子。 (3) 前記誘電体がガラス繊維強化ポリイミド樹
脂から成る請求項1または2記載の積層形デイレ
イライン素子。[Scope of Claim for Utility Model Registration] (1) A ground electrode, a dielectric, a transmission line, a dielectric, and a ground electrode are repeatedly laminated in this order, and there are multiple layers of transmission lines, and both the top and bottom surfaces are ground electrodes. The transmission lines of each layer are connected in series to each other via conductors in the through holes, and at least both ends thereof are drawn out to the surface, and the ground electrodes of each layer and both the upper and lower surfaces are connected to each other in series through conductors in the through holes. A multilayer delay line element characterized in that the elements are connected in parallel to each other via conductors. (2) A ground electrode, a dielectric, a transmission line, a dielectric, and a ground electrode are repeatedly stacked in this order, and there are multiple layers of transmission lines, and both the top and bottom are ground electrodes, and the transmission of each layer is The lines are connected in series to each other via conductors in grooves provided on the end face, and at least both ends thereof are drawn out to the surface, and furthermore, each layer and the ground electrodes on both upper and lower surfaces are connected to conductors in other grooves provided on the end face. A multilayer delay line element characterized in that the elements are connected in parallel to each other via. (3) The multilayer delay line element according to claim 1 or 2, wherein the dielectric material is made of glass fiber reinforced polyimide resin.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP65989U JPH0292210U (en) | 1989-01-07 | 1989-01-07 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP65989U JPH0292210U (en) | 1989-01-07 | 1989-01-07 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0292210U true JPH0292210U (en) | 1990-07-23 |
Family
ID=31199883
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP65989U Pending JPH0292210U (en) | 1989-01-07 | 1989-01-07 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0292210U (en) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5623002A (en) * | 1979-08-03 | 1981-03-04 | Nippon Telegr & Teleph Corp <Ntt> | Microwave strip line |
JPS58117701A (en) * | 1982-01-06 | 1983-07-13 | Nec Corp | High frequency strip line |
JPS60227494A (en) * | 1984-04-26 | 1985-11-12 | 富士通株式会社 | Ceramic multilayer circuit board |
JPH01143403A (en) * | 1987-11-30 | 1989-06-06 | Nec Corp | Delay line |
JPH0231503A (en) * | 1988-07-20 | 1990-02-01 | Tdk Corp | Delay line |
-
1989
- 1989-01-07 JP JP65989U patent/JPH0292210U/ja active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5623002A (en) * | 1979-08-03 | 1981-03-04 | Nippon Telegr & Teleph Corp <Ntt> | Microwave strip line |
JPS58117701A (en) * | 1982-01-06 | 1983-07-13 | Nec Corp | High frequency strip line |
JPS60227494A (en) * | 1984-04-26 | 1985-11-12 | 富士通株式会社 | Ceramic multilayer circuit board |
JPH01143403A (en) * | 1987-11-30 | 1989-06-06 | Nec Corp | Delay line |
JPH0231503A (en) * | 1988-07-20 | 1990-02-01 | Tdk Corp | Delay line |
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