JPS6355502U - - Google Patents

Info

Publication number
JPS6355502U
JPS6355502U JP15013386U JP15013386U JPS6355502U JP S6355502 U JPS6355502 U JP S6355502U JP 15013386 U JP15013386 U JP 15013386U JP 15013386 U JP15013386 U JP 15013386U JP S6355502 U JPS6355502 U JP S6355502U
Authority
JP
Japan
Prior art keywords
thick film
film resistors
insulating layer
stacked
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15013386U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15013386U priority Critical patent/JPS6355502U/ja
Publication of JPS6355502U publication Critical patent/JPS6355502U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Non-Adjustable Resistors (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図イは、本考案に係わるパターン設計によ
り2つの抵抗体を直列接続した状態の平面図、同
ロは、同イのX―X線断面図、第2図イは、本考
案に係わるパターン設計による2つの抵抗体を並
列接続した状態の平面図、同ロは、同イのY―Y
線断面図、第3図は、従来のパターン設計による
抵抗体の断面図である。 〔主要部分の符号の説明〕、1:基板、2:抵
抗体、3:導体層、4:絶縁層。
Figure 1A is a plan view of two resistors connected in series according to the pattern design according to the present invention, Figure 1B is a cross-sectional view taken along line X--X of the same Figure 2A is according to the present invention. A plan view of two resistors connected in parallel according to the pattern design.
The line cross-sectional view, FIG. 3, is a cross-sectional view of a resistor with a conventional pattern design. [Explanation of symbols of main parts] 1: substrate, 2: resistor, 3: conductor layer, 4: insulating layer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数の厚膜抵抗体を絶縁層を介して重ね合わせ
て多層に配置したことを特徴とするハイブリツド
集積回路に於ける厚膜抵抗体の配置構造。
1. An arrangement structure of thick film resistors in a hybrid integrated circuit, characterized in that a plurality of thick film resistors are stacked on top of each other with an insulating layer interposed in between and arranged in multiple layers.
JP15013386U 1986-09-30 1986-09-30 Pending JPS6355502U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15013386U JPS6355502U (en) 1986-09-30 1986-09-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15013386U JPS6355502U (en) 1986-09-30 1986-09-30

Publications (1)

Publication Number Publication Date
JPS6355502U true JPS6355502U (en) 1988-04-14

Family

ID=31065994

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15013386U Pending JPS6355502U (en) 1986-09-30 1986-09-30

Country Status (1)

Country Link
JP (1) JPS6355502U (en)

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