JPH0287701A - Package for high frequency integrated circuit - Google Patents
Package for high frequency integrated circuitInfo
- Publication number
- JPH0287701A JPH0287701A JP63239035A JP23903588A JPH0287701A JP H0287701 A JPH0287701 A JP H0287701A JP 63239035 A JP63239035 A JP 63239035A JP 23903588 A JP23903588 A JP 23903588A JP H0287701 A JPH0287701 A JP H0287701A
- Authority
- JP
- Japan
- Prior art keywords
- high frequency
- conductor layer
- frame
- base
- frequency input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims description 34
- 238000007789 sealing Methods 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 abstract description 37
- 230000000694 effects Effects 0.000 abstract description 8
- 229910000679 solder Inorganic materials 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 19
- 239000002184 metal Substances 0.000 description 19
- 239000004065 semiconductor Substances 0.000 description 18
- 239000003990 capacitor Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Waveguides (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、高周波集積回路等の半導体素子を収容する
ための高周波集積回路用パッケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package for a high frequency integrated circuit for accommodating a semiconductor element such as a high frequency integrated circuit.
従来、この種の高周波集積回路用パッケージにおいては
、枠体1は第8図および第9図に示すように、コプレー
ナ導波路構造の高周波入出力端子を構成するための中心
導体層6、接地層7を形成した第1のセラミック基板1
3と該第1のセラミック基板13上に形成した端子を絶
縁するための第2のセラミック基板14とを積層させた
構成をしており、半導体素子が搭載される領域2の周囲
を取り囲むような構造が取られていた。また、高周波入
出力端子としてのコプレーナ導波路構造における接地層
7とセラミック製基体表面の導体層あるいは金属製基体
3とは第1のセラミック基板13を貫通して導通させた
ピアホール12を介して接続される構成が取られていた
。なお、15はバイアス電圧供給端子である。Conventionally, in this type of high-frequency integrated circuit package, the frame 1 has a central conductor layer 6 and a ground layer for configuring high-frequency input/output terminals of a coplanar waveguide structure, as shown in FIGS. 8 and 9. 7 is formed on the first ceramic substrate 1
3 and a second ceramic substrate 14 for insulating the terminals formed on the first ceramic substrate 13 are laminated. structure was taken. In addition, the ground layer 7 in the coplanar waveguide structure as a high frequency input/output terminal and the conductor layer on the surface of the ceramic substrate or the metal substrate 3 are connected via a pier hole 12 that penetrates the first ceramic substrate 13 and is electrically conductive. A configuration was adopted in which Note that 15 is a bias voltage supply terminal.
また、この種の高周波集積回路用パッケージの場合、半
導体素子が搭載される領域2に半導体素子を搭載して半
導体素子の電極と前記高周波入出力端子を構成する中心
導体層6および接地層7間をそれぞれボンディング用ワ
イア等で接続した後、板状材料(図示せず)を付けて半
導体素子を封止することによって増幅器等の機能を有す
る高周波モジュールが得られる。In the case of this type of high-frequency integrated circuit package, the semiconductor element is mounted in the area 2 where the semiconductor element is mounted, and between the electrode of the semiconductor element and the center conductor layer 6 and the ground layer 7 that constitute the high-frequency input/output terminal. After connecting them with bonding wires or the like, a plate-like material (not shown) is attached to seal the semiconductor element, thereby obtaining a high-frequency module having functions such as an amplifier.
(発明が解決しようとする課題〕
しかし、高周波入出力端子間で前記第1.第2のセラミ
ック基板13.14を介してリング共振を生ずる、ある
いは第1.第2のセラミック基板13.14を介したマ
イクロ波の澗洩分が高周波入出力端子にフィードバック
される等によって、高周波モジュールの周波数特性が劣
化するという欠点があった。また、高周波入出力端子に
おける接地層7がピアホール12のみでセラミック製基
体表面に形成された導体層あるいは金属製基体3と接続
しているため、ピアホール12におけるインダクタンス
成分、抵抗成分等により、接地層7の電位が充分にセラ
ミック製基体表面に形成された導体層あるいは金属製基
体3の電位、すなわち、接地電位とならず高周波用端子
での不整合を生じ、高周波集積回路用パッケージにおけ
る高周波特性が制限されるという欠点があった。(Problems to be Solved by the Invention) However, ring resonance may occur between the high frequency input and output terminals via the first and second ceramic substrates 13.14, or the first and second ceramic substrates 13.14 may There is a drawback that the frequency characteristics of the high-frequency module deteriorates due to the leakage of microwaves through the high-frequency input/output terminals being fed back to the high-frequency input/output terminals.Also, the ground layer 7 at the high-frequency input/output terminals is made of ceramic with only the peer hole 12. Since it is connected to the conductor layer formed on the surface of the ceramic substrate or the metal substrate 3, the potential of the ground layer 7 is sufficiently increased due to the inductance component, resistance component, etc. in the pier hole 12. Alternatively, the potential of the metal substrate 3, that is, the potential of the metal substrate 3 does not reach the ground potential, causing a mismatch at the high frequency terminal, which has the disadvantage that the high frequency characteristics of the high frequency integrated circuit package are limited.
この発明は、前記欠点を改善あるいは除去するためにな
されたもので、枠体におけるリング共振の抑制、枠体を
介したマイクロ波の漏洩分の高周波入出力端子へのフィ
ードバックの抑制ならびにピアホールにおけるインダク
タンス成分、抵抗成分の低減化を図ることによって、半
導体素子を搭載した高周波モジュールが30GHz帯の
超高周波領域まで動作可能となる高周波集積回路用パッ
ケージを士是イ共することを目的とする。This invention was made to improve or eliminate the above-mentioned drawbacks, and includes suppressing ring resonance in the frame, suppressing feedback of microwave leakage through the frame to the high frequency input/output terminal, and reducing inductance in the peer hole. The purpose of the present invention is to provide a high-frequency integrated circuit package that enables a high-frequency module equipped with a semiconductor element to operate up to an ultra-high frequency region of 30 GHz band by reducing the component and resistance component.
この発明にかかる高周波集積回路用パッケージは、枠体
を、複数の薄い絶縁性シートの各表面にコプレーナ導波
路構造の周囲を取り囲むように導体層を形成し、さらに
各導体層間および各導体層とコプレーナ導波路構造の高
周波入出力端子の接地層と、導体層を形成した基体の導
体層あるいは導電性基体とを電気的に接続して構成した
ものである。In the package for a high frequency integrated circuit according to the present invention, the frame is formed by forming a conductor layer on each surface of a plurality of thin insulating sheets so as to surround a coplanar waveguide structure, and further between each conductor layer and between each conductor layer. It is constructed by electrically connecting the ground layer of a high frequency input/output terminal of a coplanar waveguide structure to a conductive layer or a conductive base of a base on which a conductive layer is formed.
また、この発明においては、枠体に形成された高周波入
出力端子を除く他の高周波入出力端子。Further, in the present invention, other high frequency input/output terminals other than the high frequency input/output terminal formed on the frame body.
低周波入出力端子、バイアス電圧供給用端子および接地
用端子を枠体あるいは基体のいずれか一方に形成するこ
とができる。A low frequency input/output terminal, a bias voltage supply terminal, and a grounding terminal can be formed on either the frame or the base.
この発明においては、コプレーナ導波路構造の全周囲が
導体で囲まれていると等価となり、リング共振の抑制、
マイクロ波の漏洩分の高周波入出力端子へのフィードバ
ックの制御、およびインダクタンス成分の低減がはかれ
る。In this invention, the entire periphery of the coplanar waveguide structure is equivalent to being surrounded by a conductor, suppressing ring resonance,
Feedback of microwave leakage to the high frequency input/output terminal is controlled and the inductance component is reduced.
また、枠体に形成された高周波入出力端子を除く他の端
子を基体に設けたものは、シールドがより完全に行われ
、高周波特性が向上する。Further, in the case where terminals other than the high frequency input/output terminal formed on the frame are provided on the base body, shielding is more complete and high frequency characteristics are improved.
(実施例1)
第1図〜第5図はこの発明の第1の実施例を説明する図
であって、第1図は斜視図、第2図は、第1図の高周波
入出力端子(Tの部分)を詳細に説明した斜視図、第3
図は、第2図のA−A ’の断面図、第4図は第2図を
B方向から見た図、第5図は半導体素子を実装した構成
例の上面図である。(Embodiment 1) FIGS. 1 to 5 are diagrams for explaining a first embodiment of the present invention, in which FIG. 1 is a perspective view, and FIG. 2 is a high-frequency input/output terminal ( A perspective view explaining the T part in detail, Part 3
The figure is a cross-sectional view taken along the line A-A' in FIG. 2, FIG. 4 is a view of FIG. 2 seen from direction B, and FIG. 5 is a top view of a configuration example in which semiconductor elements are mounted.
図において、1はこの発明の高周波集積回路用パッケー
ジの枠体、2は半導体素子を搭載する領域、3は導体層
で覆われたセラミック製基体あるいは金属製基体、6は
コプレーナ導波路を構成するための(高周波入出力端子
の)中心導体層、7はコプレーナ導波路を構成するため
の(高周波入出力端子の)接地層、8は薄いセラミック
基板、9は前記薄いセラミック基板8の表面の内、接地
層7に平行な面に形成された第1の導体層、1゜は前記
薄いセラミック基板8の表面の内、接地層7に直交する
面に形成された第2の導体層、11はコプレーナ導波路
を構成するための絶縁層、12はピアホール、15はバ
イアス電圧供給端子、16は半導体素子、17はバイパ
スコンデンサ、18はボンディング用ワイアである。In the figure, 1 is a frame of the high-frequency integrated circuit package of the present invention, 2 is a region for mounting a semiconductor element, 3 is a ceramic base or metal base covered with a conductor layer, and 6 is a coplanar waveguide. 7 is a ground layer (of the high frequency input/output terminal) for configuring the coplanar waveguide, 8 is a thin ceramic substrate, and 9 is the inner surface of the thin ceramic substrate 8. , a first conductor layer formed on a plane parallel to the ground layer 7, 1° a second conductor layer formed on a plane perpendicular to the ground layer 7 on the surface of the thin ceramic substrate 8, 11 12 is a peer hole, 15 is a bias voltage supply terminal, 16 is a semiconductor element, 17 is a bypass capacitor, and 18 is a bonding wire.
はじめに、第1の実施例における枠体1の製造工程例に
ついて説明する。まず、薄いセラミックのグリーンシー
トを6枚用意し、それぞれの表面と裏面の所定の個所に
導電性材料、例えばタングステンペーストを塗布し、第
1の導体層9の形成準備をした後積層する。その後、パ
ンチング等で所定の位置を開口し、ピアホール12用の
穴および半導体素子16を搭載する領域2を形成する。First, an example of the manufacturing process of the frame body 1 in the first embodiment will be described. First, six thin ceramic green sheets are prepared, and a conductive material such as tungsten paste is applied to predetermined locations on the front and back surfaces of each sheet to prepare for the formation of the first conductor layer 9 and then laminated. Thereafter, a predetermined position is opened by punching or the like to form a hole for the peer hole 12 and a region 2 in which the semiconductor element 16 is to be mounted.
さらに、ピアホール12用の穴に前記タングステンペー
ストを埋め込んでピアホール12を形成する。次に、積
層した薄いセラミック基板8の壁面の所定の箇所、すな
わちコプレーナ導波路構造の高周波入出力端子の高周波
特性を損なわない範囲および他の端子を絶縁させる範囲
に、前記タングステンペーストを塗布する。最後に、セ
ラミック製基体表面に形成された導体層あるいは金属製
基体3に前記積層したセラミック基板8を銀ろう等の板
を挟んで重ね合わせた後高温で焼成する。Furthermore, the tungsten paste is filled into the hole for the pier hole 12 to form the pier hole 12. Next, the tungsten paste is applied to a predetermined portion of the wall surface of the laminated thin ceramic substrate 8, that is, an area that does not impair the high frequency characteristics of the high frequency input/output terminal of the coplanar waveguide structure and an area that insulates other terminals. Finally, the laminated ceramic substrate 8 is stacked on the conductor layer formed on the surface of the ceramic substrate or on the metal substrate 3 with a plate of silver solder or the like interposed therebetween, and then fired at a high temperature.
この工程によって、枠体1は、第2図に示すように6枚
の薄いセラミック基板8が第1.第2の導体層9.10
で囲まれた構造となる。また、高周波入出力端子の部分
は第3図に示すようにコプレーナ導波路の両側に高周波
入出力端子を構成する中心導体層6、接地層7と平行に
第1の導体層9が配置される。さらに、第2図、第4図
に示すように中心導体層6、接地層7と直交する枠体1
表面に第2の導体層10が形成され、また、高周波入出
力端子の接地層7とセラミック製基体表面の導体層ある
いは金属製基体3と接続し接地層7と直交する面方向に
ピアホール12が配置される。Through this process, the frame 1 is made up of six thin ceramic substrates 8 as shown in FIG. Second conductor layer 9.10
It becomes a structure surrounded by. In addition, in the high frequency input/output terminal portion, as shown in FIG. 3, a first conductor layer 9 is arranged parallel to the central conductor layer 6 and ground layer 7 that constitute the high frequency input/output terminal on both sides of the coplanar waveguide. . Furthermore, as shown in FIGS. 2 and 4, the frame 1 is perpendicular to the center conductor layer 6 and the ground layer 7.
A second conductor layer 10 is formed on the surface, and a pier hole 12 is formed in a plane direction perpendicular to the ground layer 7 to connect the ground layer 7 of the high frequency input/output terminal and the conductor layer on the surface of the ceramic base or the metal base 3. Placed.
この結果得られたパッケージの枠体1は、接地層7であ
るセラミック製基体表面の導体層あるいは金属製基体3
に導通した第1の導体層9、第2の導体層1oによって
枠体1の内外が電気的にシールドされた構造となり、従
来のセラミック製枠体におけるマイクロ波の漏洩分の高
周波入出力端子へのフィードバックの低減を抑制でき、
さらに、ピアホール12では不十分だったコプレーナ導
波路構造の高周波入出力端子における接地層7の電位を
セラミック製基体表面の導体層あるいは金属製基体3の
電位に限りなく近くできる構造となり、ピアホール12
でのインダクタンス成分および抵抗成分の低減が図れる
。その結果、枠体1はコプレーナ導波路構造の高周波入
出力端子を除き、擬似的に金属製枠体と同等の効果が得
られ、この発明の枠体1を介したリング共振等を除去で
きるため、パッケージのキャビティ寸法はTE+o+
、TE+oモードのマイクロ波の伝播を考慮した設計を
行えばよいことになる。以上の結果をもとにパッケージ
のキャビティを設計した結果、パッケージの高周波入出
力端子間のアイソレーションが30GHz帯でも30d
B以上が得られるとともに、高周波用端子の挿入損失が
0.3dB以下と低損失化が達成できた。The frame 1 of the package obtained as a result has a conductor layer on the surface of the ceramic base, which is the ground layer 7, or a metal base 3.
The inside and outside of the frame 1 are electrically shielded by the first conductor layer 9 and the second conductor layer 1o, which are electrically connected to each other, and the microwave leakage in the conventional ceramic frame is connected to the high frequency input/output terminal. can suppress the reduction of feedback,
Furthermore, the potential of the ground layer 7 at the high frequency input/output terminal of the coplanar waveguide structure, which was insufficient with the pier hole 12, can be brought as close as possible to the potential of the conductor layer on the surface of the ceramic base or the metal base 3, and the pier hole 12
The inductance component and resistance component can be reduced. As a result, except for the high frequency input/output terminals of the coplanar waveguide structure, the frame 1 can obtain an effect virtually equivalent to that of a metal frame, and ring resonance etc. via the frame 1 of the present invention can be eliminated. , the package cavity dimensions are TE+o+
, TE+o mode microwave propagation should be considered in the design. As a result of designing the package cavity based on the above results, the isolation between the high frequency input and output terminals of the package was 30d even in the 30GHz band.
B or more was obtained, and the insertion loss of the high frequency terminal was 0.3 dB or less, which was a low loss.
次に、この構造のパッケージを用いた高周波モジュール
への通用例について説明する。Next, an example of application to a high frequency module using a package with this structure will be explained.
第5図に示すように、このパッケージに半導体素子16
、バイパスコンデンサ17をパッケージの領域2にAu
Sn等のはんだを用いて取りつけた後、半導体素子16
の電極と高周波入出力端子の中心導体層6、接地層7お
よびバイパスコンデンサ17、DC電圧供給用導体層間
をそれぞれボンディング用ワイア18で電気的に結線す
る。最後に、金属製の蓋(図示せず)で気密封止するこ
とによって高周波モジュールが完成する。この場合、パ
ッケージの高周波用端子および枠体1が前述のような構
造になっていることから、前記高周波モジュールに高周
波信号を入力し半導体素子16で増幅するなどの動作を
実行しても、高周波入出力端子での漏洩分が枠体1を介
してフィードバックされることがなく、半導体素子16
の機能を損なうことがない。また、コプレーナ導波路構
造の高周波入出力端子の接地層7が、セラミック製基体
表面の導体層あるいは金属製基体3の電位と限りなく近
い電位となるため、高周波人出力端子の高周波特性が特
に優れるといった利点がある。As shown in FIG. 5, a semiconductor element 16 is included in this package.
, the bypass capacitor 17 is placed in the area 2 of the package using Au.
After attaching using solder such as Sn, the semiconductor element 16
The electrodes, the center conductor layer 6 of the high-frequency input/output terminal, the ground layer 7, the bypass capacitor 17, and the DC voltage supply conductor layer are electrically connected by bonding wires 18, respectively. Finally, the high frequency module is completed by hermetically sealing with a metal lid (not shown). In this case, since the high-frequency terminals and frame body 1 of the package have the above-described structure, even if a high-frequency signal is input to the high-frequency module and amplified by the semiconductor element 16, the high-frequency Leakage at the input/output terminal is not fed back through the frame 1, and the semiconductor element 16
without impairing its functionality. In addition, since the ground layer 7 of the high frequency input/output terminal of the coplanar waveguide structure has a potential that is extremely close to the potential of the conductor layer on the surface of the ceramic base or the metal base 3, the high frequency characteristics of the high frequency output terminal are particularly excellent. There are advantages such as
この結果から明らかなように、従来の技術では困難であ
った30GHz帯の超高周波まで動作する半導体素子1
6を搭載したマイクロ波集積回路が実現できるようにな
った。As is clear from these results, it is clear that the semiconductor device 1 can operate up to ultra-high frequencies in the 30 GHz band, which was difficult to achieve with conventional technology.
Microwave integrated circuits equipped with 6 can now be realized.
(実施例2)
第6図は、この発明の第2の実施例の高周波用端子部の
側面図であり、第2図のBの方向から見た図であり、第
4図に対応するもので、第2の導体層10が接地層7の
内輪まで延びており、第4図よりもコプレーナ導波路構
造を密に取り囲んでいる。したがって、接地層7のうち
中心導体層6の近傍部分がセラミック製基体表面の導体
層あるいは金属製基体3の電位により近くなるため、高
周波集積回路用パッケージの高周波特性の改善を図るこ
とができる。この実施例での、枠体1.の製作工程、キ
ャビティの設計方法等は実施例とほぼ同等である。(Embodiment 2) FIG. 6 is a side view of the high frequency terminal section of the second embodiment of the present invention, which is a view seen from the direction B in FIG. 2, and corresponds to FIG. 4. 4, the second conductor layer 10 extends to the inner ring of the ground layer 7 and surrounds the coplanar waveguide structure more closely than in FIG. Therefore, the portion of the ground layer 7 near the center conductor layer 6 becomes closer to the potential of the conductor layer on the surface of the ceramic substrate or the metal substrate 3, so that the high frequency characteristics of the high frequency integrated circuit package can be improved. In this embodiment, frame 1. The manufacturing process, cavity design method, etc. are almost the same as in the example.
(実施例3)
第7図はこの発明の第3の実施例の斜視図であって、コ
プレーナ導波路構造の高周波入出力端子を除く端子をセ
ラミック製の基体あるいは金属製基体3にガラス端子(
セラミック端子等でもよい)により形成した例である。(Embodiment 3) FIG. 7 is a perspective view of a third embodiment of the present invention, in which terminals other than high-frequency input/output terminals of a coplanar waveguide structure are attached to a ceramic substrate or a metal substrate 3 with glass terminals (
In this example, a ceramic terminal or the like may be used.
この実施例での、枠体1の製作工程、キャビティの設計
方法等は第1の実施例とほぼ同等である。この第3の実
施例では、コプレーナ導波路構造の高周波入出力端子を
除く端子をセラミック製基体あるいは金属製基体3にガ
ラス端子19で形成しているため、パッケージのキャビ
ティは高周波用端子以外は全てシールドされる構造とな
りて高周波特性が特に優れるなどの特徴を有する。In this embodiment, the manufacturing process of the frame 1, the method of designing the cavity, etc. are almost the same as in the first embodiment. In this third embodiment, all terminals except the high-frequency input/output terminals of the coplanar waveguide structure are formed with glass terminals 19 on the ceramic or metal base 3, so that all the terminals except the high-frequency terminals are in the cavity of the package. It has a shielded structure and has particularly excellent high frequency characteristics.
なお、これまでの実施例では、薄いセラミック基板8が
6枚の場合について説明したが、3〜5枚の場合につい
ても効果が若干小さくなるものの従来技術に比べて効果
的であることは言うまでもない。また、6枚をこえる場
合は効果が大きくなる方向であり、必然的にこの発明の
範嗜にはいることは言うまでもない。また、この発明の
実施例では、搭載している高周波集積回路の個数を1個
の場合で説明しているが、個数が複数になった場合でも
、この発明の特徴を損なうものではないことは言うまで
もない。また、ピアホール12がない場合でもこの発明
の効果が有効であることは言うまでもない。In the examples so far, the case where there are six thin ceramic substrates 8 has been explained, but it goes without saying that the case with three to five thin ceramic substrates 8 is also more effective than the conventional technique, although the effect is slightly smaller. . Moreover, if the number exceeds 6, the effect tends to increase, and it goes without saying that this is necessarily within the scope of the present invention. Furthermore, in the embodiments of the present invention, the number of installed high-frequency integrated circuits is one. However, even if the number of high-frequency integrated circuits is multiple, the features of the present invention will not be impaired. Needless to say. Furthermore, it goes without saying that the effects of the present invention are effective even when there is no peer hole 12.
ざらに、この発明の実施例では、枠体1をセラミック材
料、基体を金属材料として説明したが、プラスチック等
の絶縁製材料を使用した場合でもこの発明の範喝に入る
ことは明らかである。Generally speaking, in the embodiments of the present invention, the frame 1 is made of a ceramic material and the base is made of a metal material, but it is clear that the use of an insulating material such as plastic also falls within the scope of the present invention.
(発明の効果〕
以上説明したように、この発明は、枠体を、複数の薄い
絶縁性シートの各表面にコプレーナ導波路構造の周囲を
取り囲むように導体層を形成し、さらに各導体層間およ
び各導体層とコプレーナ導波路構造の高周波入出力端子
の接地層と、導体層を形成した基体の導体層あるいは導
電性基体、とを電気的に接続して構成したので、従来の
セラミック製枠体におけるマイクロ波の漏洩分の高周波
入出力端子へのフィードバックの低減を抑制でき、さら
にピアホールでは不十分だったコプレーナ導波路構造の
高周波入出力端子における接地層の電位を、基体表面の
導体層あるいは金属製基体の電位に限りなく近くできる
構造となり、ビアホー゛ルでのインダクタンス成分およ
び抵抗成分の低減が図れる。また、枠体はコプレーナ導
波路構造の高周波入出力端子を除き、擬似的に金属性枠
体と同等の効果が得られ、この発明の枠体を介したリン
グ共振等を除去できるため、高周波特性の改善が図れる
。(Effects of the Invention) As explained above, the present invention provides a frame in which a conductor layer is formed on each surface of a plurality of thin insulating sheets so as to surround a coplanar waveguide structure, and further between each conductor layer. Since each conductor layer is electrically connected to the ground layer of the high frequency input/output terminal of the coplanar waveguide structure and the conductor layer or conductive substrate of the base on which the conductor layer is formed, it is possible to use a conventional ceramic frame. In addition, the potential of the ground layer at the high-frequency input/output terminal of the coplanar waveguide structure, which was insufficient with a peer hole, can be reduced by reducing the potential of the ground layer at the high-frequency input/output terminal of the coplanar waveguide structure by using the conductor layer or metal on the substrate surface. The structure has a structure that can be as close to the potential of the base made of metal as possible, reducing the inductance component and resistance component in the via hole.In addition, the frame body is a pseudo metal frame, except for the high frequency input/output terminal of the coplanar waveguide structure. It is possible to obtain the same effect as the frame body and eliminate ring resonance etc. via the frame body of the present invention, so that high frequency characteristics can be improved.
さらに、枠体に形成された高周波入出力端子を除く他の
端子を基体に形成したものは、シールドがより完全に行
われ高周波特性が向上する利点がある。Furthermore, a device in which all terminals other than the high frequency input/output terminals formed on the frame are formed on the base body has the advantage that shielding is more complete and high frequency characteristics are improved.
第1図はこの発明のパッケージ全体を示す斜視図、第2
図は、第1図の高周波用端子を詳細に示した斜視図、第
3図はこの発明の特徴をもつとも良く示している第2図
のA−A ’の断面図、第4図は、第2図をB方向から
見た図、第5図は半導体素子を実装した構成例の上面図
、第6図はこの発明の第2の実施例の高周波用端子部の
側面図、第7図はこの発明の第3の実施例を表すパッケ
ージの斜視図、第8図はコプレーナ導波路用導体層を備
えた従来パッケージの上面図、第9図は、第8図におけ
るC方向からみた図である。
図において、1は枠体、2は半導体素子を搭載する領域
、3は導体層で覆ったセラミック製基体あるいは金属製
基体、6は中心導体層、7は接地層、8は薄いセラミッ
ク基板、9,10は第1゜第2の導体層、11は絶縁層
、12はピアホール、13は第1のセラミック基板、1
4は第2のセラミック基板、15はバイアス電圧供給端
子、16は半導体素子、17はバイパスコンデンサ、1
8はボンディング用ワイア、19はガラス端子である。
第
図
第
図
15バイアス電圧供M3一端子
第
図
1日ガラス珊す
第
図
第
図
第2のセラミック基板Fig. 1 is a perspective view showing the entire package of this invention;
The figure is a detailed perspective view of the high-frequency terminal in Figure 1, Figure 3 is a cross-sectional view taken along line A-A' in Figure 2, which clearly shows the features of the present invention, and Figure 4 is 2 is a view seen from direction B, FIG. 5 is a top view of a configuration example in which a semiconductor element is mounted, FIG. 6 is a side view of the high frequency terminal section of the second embodiment of the present invention, and FIG. A perspective view of a package representing a third embodiment of the present invention, FIG. 8 is a top view of a conventional package equipped with a conductor layer for a coplanar waveguide, and FIG. 9 is a view seen from direction C in FIG. . In the figure, 1 is a frame, 2 is a region for mounting a semiconductor element, 3 is a ceramic base or metal base covered with a conductor layer, 6 is a center conductor layer, 7 is a ground layer, 8 is a thin ceramic substrate, 9 , 10 is a first degree second conductor layer, 11 is an insulating layer, 12 is a peer hole, 13 is a first ceramic substrate, 1
4 is a second ceramic substrate, 15 is a bias voltage supply terminal, 16 is a semiconductor element, 17 is a bypass capacitor, 1
8 is a bonding wire, and 19 is a glass terminal. Figure Figure 15 Bias voltage supply M3 terminal Figure 1 Glass substrate Figure Figure 2 Ceramic substrate
Claims (2)
を有する枠体と、導体層を形成した基体あるいは導電性
基体と、封止用蓋とから構成された高周波集積回路用パ
ッケージにおいて、前記枠体を、複数の薄い絶縁性シー
トの各表面に前記コプレーナ導波路構造の周囲を取り囲
むように導体層を形成し、さらに前記各導体層間および
各導体層と前記コプレーナ導波路構造の前記高周波入出
力端子の接地層と、前記導体層を形成した基体の導体層
あるいは導電性基体とを電気的に接続して構成したこと
を特徴とする高周波集積回路用パッケージ。(1) A high-frequency integrated circuit package comprising a frame body partially having a high-frequency input/output terminal having a coplanar waveguide structure, a base body or conductive base body on which a conductor layer is formed, and a sealing lid, in which the above-mentioned A frame body is formed by forming a conductor layer on each surface of a plurality of thin insulating sheets so as to surround the coplanar waveguide structure, and further forming a conductor layer between each conductor layer and between each conductor layer and the high frequency input of the coplanar waveguide structure. 1. A package for a high-frequency integrated circuit, characterized in that a ground layer of an output terminal is electrically connected to a conductive layer or a conductive substrate of a base on which the conductive layer is formed.
周波入出力端子、低周波入出力端子、バイアス電圧供給
用端子および接地用端子を枠体あるいは基体のいずれか
一方に形成したことを特徴とする請求の項(1)記載の
高周波集積回路用パッケージ。(2) Except for the high frequency input/output terminal formed on the frame, other high frequency input/output terminals, low frequency input/output terminals, bias voltage supply terminals, and grounding terminals are formed on either the frame or the base. A package for a high frequency integrated circuit according to claim (1), characterized in that:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63239035A JP2603310B2 (en) | 1988-09-26 | 1988-09-26 | High frequency integrated circuit package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63239035A JP2603310B2 (en) | 1988-09-26 | 1988-09-26 | High frequency integrated circuit package |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0287701A true JPH0287701A (en) | 1990-03-28 |
JP2603310B2 JP2603310B2 (en) | 1997-04-23 |
Family
ID=17038908
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63239035A Expired - Lifetime JP2603310B2 (en) | 1988-09-26 | 1988-09-26 | High frequency integrated circuit package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2603310B2 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0685155A (en) * | 1992-09-01 | 1994-03-25 | Nec Corp | Molded semiconductor device |
US5574314A (en) * | 1994-07-28 | 1996-11-12 | Mitsubishi Denki Kabushiki Kaisha | Packaged semiconductor device including shielded inner walls |
US6674347B1 (en) | 1999-03-23 | 2004-01-06 | Nec Corporation | Multi-layer substrate suppressing an unwanted transmission mode |
US6800929B1 (en) | 1998-07-14 | 2004-10-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
JP2008159862A (en) * | 2006-12-25 | 2008-07-10 | Hitachi Kokusai Electric Inc | Package structure of high-frequency electronic component |
JP2014011271A (en) * | 2012-06-28 | 2014-01-20 | Kyocera Corp | Element accommodation package and mounting structure |
JP2014127564A (en) * | 2012-12-26 | 2014-07-07 | Kyocera Corp | Electronic component storing package and electronic apparatus using the same |
-
1988
- 1988-09-26 JP JP63239035A patent/JP2603310B2/en not_active Expired - Lifetime
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0685155A (en) * | 1992-09-01 | 1994-03-25 | Nec Corp | Molded semiconductor device |
US5574314A (en) * | 1994-07-28 | 1996-11-12 | Mitsubishi Denki Kabushiki Kaisha | Packaged semiconductor device including shielded inner walls |
US6800929B1 (en) | 1998-07-14 | 2004-10-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
US6674347B1 (en) | 1999-03-23 | 2004-01-06 | Nec Corporation | Multi-layer substrate suppressing an unwanted transmission mode |
JP2008159862A (en) * | 2006-12-25 | 2008-07-10 | Hitachi Kokusai Electric Inc | Package structure of high-frequency electronic component |
JP2014011271A (en) * | 2012-06-28 | 2014-01-20 | Kyocera Corp | Element accommodation package and mounting structure |
JP2014127564A (en) * | 2012-12-26 | 2014-07-07 | Kyocera Corp | Electronic component storing package and electronic apparatus using the same |
Also Published As
Publication number | Publication date |
---|---|
JP2603310B2 (en) | 1997-04-23 |
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