JPH0287652A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPH0287652A
JPH0287652A JP63241412A JP24141288A JPH0287652A JP H0287652 A JPH0287652 A JP H0287652A JP 63241412 A JP63241412 A JP 63241412A JP 24141288 A JP24141288 A JP 24141288A JP H0287652 A JPH0287652 A JP H0287652A
Authority
JP
Japan
Prior art keywords
pellet
ceramic package
memory cell
cell array
package lower
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63241412A
Other languages
Japanese (ja)
Inventor
Kazutoshi Kamibayashi
和利 上林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63241412A priority Critical patent/JPH0287652A/en
Publication of JPH0287652A publication Critical patent/JPH0287652A/en
Pending legal-status Critical Current

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  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To effectively prevent a soft error action to be caused by a radiation of alpha-rays without causing fluctuation in characteristics and a deterioration in quality of a memory cell by a method wherein an alpha-ray-absorbing layer is formed at an inner face of a ceramic package member surrounding a memory cell array pellet. CONSTITUTION:The following are contained: a ceramic package lower-part member 2 where a memory cell array pellet 1 is mounted inside a cavity at the surface; metal thin wires 3 which connect electrodes of the memory cell array pellet 1 to electrodes on the ceramic package lower-part member 2 individually; a ceramic package lid member 5 which is connected to the ceramic package lower-part member 2 via an adhesive material 4 and which airtightly seal the memory cell array pellet 1 together with the metal thin wires 3; organic films, e.g., polyimide layers 6, which have been applied individually to a sidewall of the cavity in the ceramic package lower-part member 2 surrounding the memory cell array pellet 1 and to an inner wall of the lid member 5. In this case, the polyimide films 6 are composed of a material manufactured so as not to contain uranium as far as possible.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に大容量メモリを塔載す
るセラミック・パッケージ型半導体記憶装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a ceramic package type semiconductor memory device mounting a large capacity memory.

〔従来の技術〕[Conventional technology]

従来、大容量メモリを有するセラミック・パッケージ型
半導体記憶装置は、セラミック・パッケージに含まれる
ウラン等の放射性物質からのX線によるメモリ・セルの
ソフト・エラーを防止する為、ペレットの上に低ウラン
濃度のポリイミドあるいはシリコーンを50μ〜200
μ程度の厚さに塗布する対策がとられている。
Conventionally, ceramic packaged semiconductor storage devices with large-capacity memory have a low uranium content on top of the pellet to prevent soft errors in memory cells caused by X-rays from radioactive substances such as uranium contained in the ceramic package. Polyimide or silicone with a concentration of 50μ to 200μ
Measures have been taken to apply the coating to a thickness of about μ.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、上述した従来技術は、ICのペレット上
へポリイミドもしくはシリコーンを直接被覆する為に下
記の欠点を有している。
However, the above-mentioned prior art has the following drawbacks because polyimide or silicone is directly coated onto the IC pellet.

(1)ペレット上へ直接ポリイミドもしくはシリコーン
を被覆すると、ベレット表面に応力が加わるので、メモ
リ特性の変動が生ずる。
(1) If polyimide or silicone is directly coated onto the pellet, stress is applied to the pellet surface, resulting in variations in memory characteristics.

(2)ペレット上へ直接ポリイミドもしくはシリコーン
を被覆した後、溶剤の乾燥等を行う高温処理が必要とな
り、ペレットに熱的ストレスが加わるので、メモリ装置
の品質劣化を起こす。
(2) After coating polyimide or silicone directly onto the pellets, high-temperature treatment such as drying the solvent is required, and thermal stress is applied to the pellets, causing quality deterioration of the memory device.

本発明の目的は、上記の問題点に鑑み、α線吸収層のベ
レット直接被覆によるメモリ・セルの特性変動および品
質劣化を生じることなきソフト・エラ一対策を備えた半
導体記憶装置を提供することである。
SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a semiconductor memory device having a countermeasure against soft errors without causing characteristic fluctuations or quality deterioration of memory cells due to direct coating of an α-ray absorbing layer on a pellet. It is.

〔課題を解決するための手段〕[Means to solve the problem]

本発明によれば、半導体記憶装置は、メモリ・セル・ア
レイ・ペレットと、前記メモリ・セル・アレイ・ペレッ
トを上面のくぼみ内に載置するセラミック・パッケージ
下部部材と、前記メモリ・セル・アレイ・ペレットを気
密封止するセラミック・パッケージ蓋部材と、前記メモ
リ・セル・アレイ・ペレットを取囲む前記セラミック・
パッケージ下部部材のくぼみの側壁および蓋部材の内壁
面をそれぞれ被膜する有機樹脂から成るα線吸収層とを
含んで構成される。
According to the present invention, a semiconductor memory device includes a memory cell array pellet, a ceramic package lower member in which the memory cell array pellet is placed in a recess on an upper surface thereof, and a ceramic package lower member in which the memory cell array pellet is placed in a recess on the upper surface thereof. - a ceramic package lid member that hermetically seals the pellet; and a ceramic package lid member that surrounds the memory cell array pellet;
The package includes an α-ray absorbing layer made of an organic resin that coats the side wall of the recess of the package lower member and the inner wall surface of the lid member.

〔実施例〕〔Example〕

以下図面を参照して本発明の詳細な説明する。 The present invention will be described in detail below with reference to the drawings.

第1図は本発明の一実施例を示すセラミック・パッケー
ジ型半導体記憶装置の断面図である。本実施例によれば
、本発明の半導体記憶装置は、メモリ・セル・アレイ・
ペレット1と、このメモリ・セル・アレイ・ペレット1
を上面のくぼみ内に載置するセラミック・パッケージ下
部部材2と、メモリ・セル・アレイ・ペレット1の電極
とセラミック・パッケージ下部部材2上の電極とをそれ
ぞれ接続する金属細線3と、接着材4を介しセラミック
・パッケージ下部部材2と接着されメモリ・セル・アレ
イ・ペレット1を金属細線3と共に気密封止するセラミ
ック・パッケージ蓋部材5と、メモリ・セル・アレイ・
ペレット1を取囲むセラミック・パッケージ下部部材2
のくぼみの側壁および蓋部材5の内壁にそれぞれ被着さ
れた膜厚50〜200μmのポリイミド膜6とを含む。
FIG. 1 is a sectional view of a ceramic package type semiconductor memory device showing one embodiment of the present invention. According to this embodiment, the semiconductor memory device of the present invention includes a memory cell array,
pellet 1 and this memory cell array pellet 1
a ceramic package lower member 2 that is placed in a recess on the upper surface, a thin metal wire 3 that connects the electrodes of the memory cell array pellet 1 and the electrodes on the ceramic package lower member 2, and an adhesive 4. A ceramic package lid member 5 which is bonded to the ceramic package lower member 2 through the ceramic package lid member 5 to hermetically seal the memory cell array pellet 1 together with the thin metal wire 3;
Ceramic package lower member 2 surrounding pellet 1
A polyimide film 6 having a thickness of 50 to 200 μm is deposited on the side wall of the recess and the inner wall of the lid member 5, respectively.

ここで、ポリイミド膜6はウランを極力台まないように
造られた材質から成り、セラミック・パッケージ部材が
通常有する10〜500ppBのウラン濃度に対してそ
の数百分の一以下(例えば0.1〜0.5ppB)にま
で精製したものが使用される。
Here, the polyimide film 6 is made of a material made so as not to deplete uranium as much as possible, and is less than a few hundredths of the uranium concentration of 10 to 500 ppB (for example, 0.1 ~0.5ppB) is used.

かかるパッケージ構造の場合には、セラミック・パッケ
ージ部材1および2からペレット1に向かって放射され
るα線はポリイミド膜5内に高々50μmの深さまでし
か到達しないので、α線によるメモリ・セルのソフト・
エラーの発生は有効に抑止される。
In the case of such a package structure, since the α rays emitted from the ceramic package members 1 and 2 toward the pellet 1 reach a depth of at most 50 μm within the polyimide film 5, the softness of the memory cell due to the α rays is・
The occurrence of errors is effectively suppressed.

第2図は本発明の他の実施例を示すセラミック・パッケ
ージ型半導体記憶装置の断面図である。
FIG. 2 is a sectional view of a ceramic package type semiconductor memory device showing another embodiment of the present invention.

本実施例によれば、セラミック・パッケージ下部部材2
のくぼみの側壁に被着するポリイミド膜6がくぼみの深
さを越える高さをもつように形成される。これにより、
パッケージ下部部材2の側面からのα線をより一層有効
に吸収することができる。
According to this embodiment, the ceramic package lower member 2
A polyimide film 6 attached to the side walls of the recess is formed to have a height exceeding the depth of the recess. This results in
α rays from the side surface of the package lower member 2 can be absorbed even more effectively.

以上はα線の吸収材にポリイミドを使用した場合を説明
したが、この他シリコーンその他の有機樹脂を用いるこ
とも可能である。
Although the case where polyimide is used as the α-ray absorbing material has been described above, it is also possible to use silicone or other organic resins.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、本発明によれば、メモリ・
セル アレイ・ペレットを取巻くセラミック・パッケー
ジ部材の内面に9線の吸収層が設けられるので、従来の
如くベレット表面に機械的および熱的応力を加えずにす
む利点があり、これによってメモリ・セルの特性変動お
よび品質の劣化を生しることなく、セラミック・パッケ
ージ部材に含まれるウランからのα線放射に基づくメモ
リ・セルのソフト・エラー動作を有効に予防することが
できる。
As explained in detail above, according to the present invention, the memory
The 9-wire absorbing layer on the inner surface of the ceramic package surrounding the cell array pellet has the advantage of eliminating the conventional mechanical and thermal stresses on the pellet surface, thereby improving memory cell performance. Soft error operations of memory cells due to alpha radiation from uranium contained in ceramic package members can be effectively prevented without causing characteristic fluctuations or quality deterioration.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すセラミック・パッケー
ジ型半導体記憶装置の断面図、第2図は本発明の他の実
施例を示すセラミック・パッケージ型半導体記憶装置の
断面図である。 1・・・メモリ・セル・アレイ・ペレット、2・・・セ
ラミック・パッケージ下部部材、3・・・金属細線、4
・・・接着材、 5・・・セラミック パッケージ蓋部 材、 6・・・ポリイ ド膜。
FIG. 1 is a cross-sectional view of a ceramic package type semiconductor memory device showing one embodiment of the present invention, and FIG. 2 is a cross-sectional view of a ceramic package type semiconductor memory device showing another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Memory cell array pellet, 2...Ceramic package lower member, 3...Metal thin wire, 4
... Adhesive material, 5. Ceramic package lid member, 6. Polyide film.

Claims (1)

【特許請求の範囲】[Claims] メモリ・セル・アレイ・ペレットと、前記メモリ・セル
・アレイ・ペレットを上面のくぼみ内に載置するセラミ
ック・パッケージ下部部材と、前記メモリ・セル・アレ
イ・ペレットを気密封止するセラミック・パッケージ蓋
部材と、前記メモリ・セル・アレイ・ペレットを取囲む
前記セラミック・パッケージ下部部材のくぼみの側壁お
よび蓋部材の内壁面をそれぞれ被膜する有機樹脂から成
るα線吸収層とを含むことを特徴とする半導体記憶装置
A memory cell array pellet, a ceramic package lower member in which the memory cell array pellet is placed in a recess on a top surface, and a ceramic package lid that hermetically seals the memory cell array pellet. and an α-ray absorbing layer made of an organic resin that coats the side wall of the recess of the ceramic package lower member surrounding the memory cell array pellet and the inner wall surface of the lid member, respectively. Semiconductor storage device.
JP63241412A 1988-09-26 1988-09-26 Semiconductor storage device Pending JPH0287652A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63241412A JPH0287652A (en) 1988-09-26 1988-09-26 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63241412A JPH0287652A (en) 1988-09-26 1988-09-26 Semiconductor storage device

Publications (1)

Publication Number Publication Date
JPH0287652A true JPH0287652A (en) 1990-03-28

Family

ID=17073906

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63241412A Pending JPH0287652A (en) 1988-09-26 1988-09-26 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPH0287652A (en)

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