JPH0287258A - Memory access system - Google Patents

Abstract

PURPOSE:To simultaneously write same data to plural memories by providing an access destination instructing means in each memory of a CPU, which respectively has the memories to have a shared space, and executing memory access according to the contents of this instructing means. CONSTITUTION:A competition control part 3 refers flags 1A and 2A, and executes the decision and control of a memory access competition condition with a CPUB. When the access right of a CPUA to memories (a) and (b) is obtained, the instruction of the memory access is generated to a memory access part 4A. The memory access part 4A makes both a data effective signal 10A and a memory enable signal 11A effective and the writing data and address of a register 5A are respectively sent to the memories (a) and (b). Since both AND gates 8A and 9A output the memory enable signal at such a time, both the memories (a) and (b) are in an enable condition. Thus, the same data can be written from the CPUA to the same addresses of the memories (a) and (b).

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory access method, and in particular to a method for accessing information including a plurality of information processing devices and a plurality of memories each of which can be accessed 1 m from each of these information processing devices. Related to memory access methods in processing systems.

Previously, in this type of memory access method, there was a method to switch memory access control based on simultaneous write mode.
In normal memory access, an information processing device writes to one memory, but by setting the operation mode to simultaneous write mode, it is possible to write the same data to multiple memories at the same time. It is. When the information processing device is set to the simultaneous write mode, it attempts to obtain access rights to all of the plurality of memories, recognizes that the access rights have been successfully obtained, and executes writing of the same data to all memories.

In this simultaneous store opening mode, the information processing device that executes the write only sees one memory under it. Figure 3 shows an example of two information processing devices, each with one memory. This is the case when you have it under your control.

The information processing device CPUA is set to simultaneous write mode,
When writing the same data to memory a and memory b under the CPUB, the existence of memory b is not recognized by the CPUA, and hardware control is performed so that the same data is written to memory a at the same time.

In general, the failure rate of memory chips is higher than that of control circuits.
Ensuring the safety of important data has long been an issue, as any destruction of data stored in memory would be fatal to information processing equipment, leading to system breakdowns. .

The above-mentioned conventional technology is an example of ensuring the safety of this data; by storing the same data in multiple memories, even if data in one memory is destroyed, it can be processed with data stored in the normal memory. The idea is to carry out the following. However, this type of memory access method has the disadvantage that even though the system is composed of multiple memories, it can only use the space for one memory, and the software recognizes and accesses multiple memories. However, there are disadvantages in that data cannot be written separately, and areas other than the shared memory area for storing important data cannot be used individually for each information processing device.

An object of the present invention is to provide a memory access system 31 that allows important data to be written to multiple memories simultaneously and other data to be written individually to subordinate memories.

According to the present invention, there is provided a memory access method in an information processing system including a plurality of =+i information processing devices and a plurality of memories each of which can be accessed from each of these information processing devices. In each of the information processing devices,
Access target memory indicating means provided corresponding to the memory and displaying the memory to be accessed; and determining the memory to be accessed indicated by the access target memory indicating means of not only the own device but also other devices and accessing the memory. There is provided a memory access method characterized in that a contention control means for arbitrating rights is provided, and a memory for which access rights have been acquired is accessed by the contention control means.

Examples Please refer to the drawings for examples of the present invention below! 41 I will explain.

FIG. 1 is a circuit block diagram showing a system according to an embodiment of the present invention, which has two CPUs A and B and two memories a and b, and both CPUs can freely access both memories. Both CPUA 0 and I'3 have the same configuration, so only the configuration of CPUA is shown.

Flags IA and 2A are provided corresponding to memories a and b, respectively. For example, when writing access is made to memory a, the corresponding flag IA is set to "1",
When write access is made to both memories a and b, both flags IA and 2A are set to "1". Conflict control (CNFL) 3A refers to the contents of flags IA and 2A, learns the memory to be accessed for write access obtained from Mana et al.'s =+W information processing device 13, and arbitrates and controls memory access conflicts.

The memory access control unit (H[HCNT) 4A generates two control signals 10A and 11A when the access right is determined by arbitration by the contention control unit 3A.

The control signal 10A is a group of AND gates (consisting of the data of register 5 and the number of address pins)
6A and 7A are made by one person, and the control signal 11A is made by one person from 8A and 9A.

The data register 5A stores write data and addresses, and serves as one input to the gate groups 6A and 7A. This game)-Flag I for the power of others in groups 6A and 7A
A and 2A are applied, respectively, and the corresponding flags LA and 2A
Also gate group 8A.

Each member of 9A is a source of strength.

In the gate group 6A, the flag IA is ``1'' and the control signal is 1.
Turns on when 0 (data valid signal) indicates valid,
Write data and address of register 5A to switch 1
2A to memory a. Gate group 7A is turned on when flag 2A is 01' and data valid signal 10 is valid, and supplies the write data and address of register 5A to memory b via snatch 12[1.

The gate 1-8A enables the memory a via the OR gate 13 when the control signal 11A (memory enable signal) is valid and the flag IA is "1". Gate 9A has a valid memory enable signal and flag 2.
When A is 1', memory b is enabled via OR gate 13[3.

In this +1.1 configuration, the CPU uses both memories a and b.
The case where the same data is written simultaneously to both will be explained. C
The software that controls the PUA first sets the write data and address in register 5A, and at the same time sets the flag LA.
, 2A are both considered to be 1 Pa.

The contention control unit 3A refers to both flags IA and 2A, and determines the CP
After determining and controlling the memory access conflict state with tJB and acquiring access rights to memories a and b of the CPUA,
Memory access unit 4 Generates a memory access instruction to A.

In response, the memory access unit 4A makes both the data valid signal 10A and the memory enable signal 18 11A valid. Therefore, AND gate group 6A.

Both 7A turn on and switch the write data and address of register 5A! It is sent to both memories a and b via 2A and 12B, respectively.

At this time, since AND gates 8A and 9A#J are both outputting memory enable signals, both memories a and b are in an enabled state. Therefore, C in both memories a and b
This makes it possible to write the same data from PUA to the same address.

If data is to be allocated to either one of the memories, this is possible by setting the corresponding one of the flags IA and 2A to "1". Furthermore, it is clear that the same access control can be performed from CPU B as well.

FIG. 2 shows the address space of memory ab in the first IfA embodiment, and both can be considered to have a CPU-individual space and a shared space.

Effects of the Invention As described above, according to the present invention, an access destination instruction means is provided for each memory in the CPUs each having memories having mutually shared space, and memory access is performed according to the contents of the access destination instruction means. This allows the same data to be written to multiple memories at the same time to ensure the safety of important data, while other data can be written to individual memories, which has the effect of making effective use of memory. .

[Brief explanation of drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention, FIG. 2 is a diagram illustrating a memory address space in an embodiment of the present invention, and FIG. 3 is a diagram explaining a conventional memory access method. . Description of symbols of main parts A, B...CPLI a, b...Memory 1 person 1B, 2A 3A. 4A. A 2B...Flag 3B...Conflict control section 4B...Memory access section 5B...Data register

Claims (1)

[Claims] (1) A memory access method in an information processing system including a plurality of information processing devices and a plurality of memories each of which is accessible from each of the information processing devices, wherein each of the information processing devices includes: Access target memory indicating means provided corresponding to the memory and displaying the memory to be accessed; and determining the memory to be accessed indicated by the access target memory indicating means of not only the own device but also other devices and accessing the memory. 1. A memory access method, comprising: a contention control means for arbitrating rights, and access is made to a memory for which access rights have been acquired by the contention control means.