JPH0284770A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the cost of a semiconductor device using a complementary high-withstand voltage TET by reducing the number of photo processes in an impurity mixing process by a method wherein, after the gate electrodes of the TET are formed, a process for mixing an impurity having one of conductivity types in the whole surface of a substrate is provided. CONSTITUTION:In the case of manufacture of a semiconductor device; wherein semiconductor thin films 102 and 103, gate insulating films 104 and 105 and gate electrodes 106 and 107 are provided on a substrate 101 with a surface which is at least insulated and a thin film transistor consisting of channel regions 120 and 120, offset regions 116 to 119 and source and drain regions 112 to 115, which are provided in the films 102 and 103, is formed into a complementary transistor; a process for mixing an impurity having one of conductivity types in the whole surface of the substrate is provided after the formation of the electrodes 106 and 107. For example, after the electrodes 106 and 107 are formed, an ion-implantation is performed in the whole surface to form P<-> regions. In case the films 102 and 103 consist of silicon, B and the like are used as an impurity to mix and a dose is set in 10<12>cm<-2> or thereabouts.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device using complementary high voltage thin film transistors (hereinafter referred to as TF'T).

[Conventional technology] High voltage TFTs are S, 5EKI etc.

IEEE ELECTRON DEVICELET
TER8, VOL, EDL-8, No, 9°pp, 42
5-427, 1987. As shown in et al., unlike normal TPT, it has an offset area.

The impurity mixing step in the conventional manufacturing method of a semiconductor device using complementary high-voltage TPT is shown in FIGS. 2(a) to 2(e).
), the photo process was required four times. Same figure (
a) is a cross-sectional view of a semiconductor device in the step of forming a thin p-type region (p-) to form an offset region of a Pch TFT, in which 101 is an insulating substrate, 102 and 103 are semiconductor thin films, and 104 and 105 are Gate insulating films 106 and 107 are gate electrodes, and 201 is a mask for preventing the incorporation of impurities. In this state, impurities are mixed in by ion implantation or the like to form a p- region. Same figure (
b) is a cross-sectional view of the semiconductor device in the step of forming a warm p-type region (p'') to form the source and drain regions of a Pch TFT, and 202 is a mask for preventing the incorporation of impurities. In the same figure (C), Nch
This is a cross-sectional view of the semiconductor device in the step of forming a thin n-type region (n-) to form an offset region of a TFT, and 203 is a mask for preventing the incorporation of impurities.

Figure (d) is a cross-sectional view of the semiconductor device in the step of forming a dense n-type region (nl) to form the source and drain regions of the Nch TFT, and 204 is a mask for preventing the incorporation of impurities. . FIG. 3(e) is a cross-sectional view of the semiconductor device after the impurity mixing process is completed with the masks 203 and 204 removed.

[Problems to be Solved by the Invention] However, in the conventional manufacturing method of a semiconductor device using complementary high-voltage TPT, there are as many as four photo steps in the impurity mixing step, making the semiconductor device expensive. There was a problem. Therefore, an object of the present invention is to reduce the cost of a semiconductor device by reducing the number of photo steps in the impurity mixing step.

[Means for Solving the Problems] In order to solve the above problems, the method for manufacturing a semiconductor device of the present invention includes a step of mixing an impurity having one conductivity type into the entire surface of the substrate after forming the gate electrode of the TPT. It is characterized by:

[Example] FIG. 1 shows a complementary high voltage TPT in an example of the present invention.
1A and 1B are cross-sectional views in the order of manufacturing steps in an impurity mixing step of a semiconductor device using the method. In the same figure (a), Pch TFT
3 is a cross-sectional view during a step of mixing an impurity having p-type conductivity into the entire surface of the substrate in order to form an offset region. FIG.

In the figure, 101 is a substrate whose surface is insulated at least, 102 and 103 are semiconductor thin films, 104 and 105 are gate insulating films, and 106 and 107 are gate electrodes.

Forming semiconductor thin films 102 and 103 on a substrate 101,
Gate insulating films 104 and 105 and gate electrodes 106 and 107 are formed. Then, a p- region is formed by ion implantation or the like. When the semiconductor thin films 102 and 103 are made of Sl, B or the like is used as the impurity, and in the case of ion implantation,
The dose amount is about 1012 cm-2. Same figure (b)
1 is a cross-sectional view at the time of selectively mixing impurities having a p-type conductivity type in order to form source and drain regions of a PchTFT, and 108 and 109 are mask materials for preventing the mixing of impurities. When impurities are mixed by ion implantation, a photoresist or the like is used for 108 and 109, and a p'''' region is formed with an impurity concentration of about 10 cm.sup.-2. In the same figure (C), Nch
To form the offset region of the TFT, selective n
It is a cross-sectional view at the time of mixing an impurity having a conductivity type of the mold, and 110 is a mask material. When Si is used for the semiconductor thin films 102 and 103, P or the like is used as the impurity to be mixed. Impurities are mixed in at a concentration on the same order of magnitude as the offset region of the Pch TFT to form an n- region. Figure (d) shows the source of the Nch TFT;
This is a cross-sectional view at the time of selectively mixing an impurity having an n-type conductivity type in order to form a drain region, and 111 is a mask material. Impurities are mixed in at a concentration on the same order as that of the source and drain regions of the Pch TFT to form n' regions. Figure (e) is a cross-sectional view at the end of the mask material peeling process, and in the above process, Pch
TFT source and drain regions 112 and 113, offset regions 116 and 117, channel region 120, N
ch TFT source and drain regions 114 and 11
5. Offset regions 118 and 119, channel region 1
It can be seen that 21 is formed to constitute a complementary high voltage TPT. In the impurity mixing step of this embodiment, the number of photo steps for forming the mask material is three, which is one step shorter than in the conventional example.

FIG. 3 is a cross-sectional view of the manufacturing process order in the impurity mixing process of a semiconductor device using a complementary high voltage TPT in another embodiment of the present invention.

FIG. 1(a) is a cross-sectional view during the process of selectively mixing impurities with p-type conductivity to form the source and drain regions of a Pch TFT, and the same symbols as in FIG. Represents the same thing as Figure 1.

301 and 302 are mask materials. The figure (b) is
FIG. 4 is a cross-sectional view during a step of mixing an impurity having p-type conductivity into the entire surface of the substrate in order to form an offset region of a Pch TFT. After forming the p1 region, impurities are mixed into the entire surface to form a p- region. In the same figure (C), Nch
To form the offset region of the TFT, selective n
It is a cross-sectional view at the time of mixing an impurity having a conductivity type of the mold, and 303 is a mask material. In the same figure (d), Nc
This is a cross-sectional view during the step of selectively mixing impurities with n-type conductivity to form the source and drain regions of the hTFT, and 304 is a mask material. FIG. 3(e) is a cross-sectional view at the end of the mask material peeling process. Through the above steps, a complementary high voltage TPT is constructed. The photo process in this embodiment also requires three steps, which is one step shorter than in the conventional example.

As described above, in the impurity mixing process of a semiconductor device using a complementary high breakdown voltage TPT, the photo process can be shortened by providing the process of mixing impurities into the entire surface of the substrate. The above embodiment is an example in which an impurity having a p-type conductivity type is mixed into the entire surface of the substrate, but of course a step may be taken in which an impurity having an n-type conductivity type is mixed into the entire surface of the substrate.

Furthermore, although the above embodiments are examples in which a TPT having offset regions on both sides of the gate electrode is used, the present invention may also be applied to a case where a TPT having an offset region on only one side of the gate electrode is used.

Further, since a normal TPT without an offset region can be formed at the same time by using the semiconductor device manufacturing method of the present invention, a complementary semiconductor device including a normal TPT and a high breakdown voltage TPT can be formed. Complementary high-voltage TPTs can be used to form driving circuits for electroluminescence and piezoelectric elements, and the present invention has a wide range of applications.

[Effects of the Invention] As described above, according to the present invention, complementary high voltage TPT
By providing a step of mixing impurities into the entire surface of the substrate in a method of manufacturing a semiconductor device using the method, the number of manufacturing steps is reduced, and a low-cost, high-voltage semiconductor device can be realized. The present invention can also be applied to semiconductor devices including circuits that use general high voltage.

3A and 3B are cross-sectional views in the order of manufacturing steps in an impurity mixing step of a semiconductor device using a pressure TFT. FIG. 6(a) is a cross-sectional view during the step of mixing an impurity having p-type conductivity into the entire surface of the substrate. (b
) is a cross-sectional view during the step of selectively mixing impurities with p-type conductivity. (C) is a cross-sectional view during a step of selectively mixing an impurity having an n-type conductivity type. (d) is selectively n
FIG. 3 is a cross-sectional view of a step of mixing an impurity having a conductivity type.

(Cross-sectional views in the order of manufacturing steps in the impurity mixing step of a semiconductor device using a complementary high-voltage TPT in the impurity mixing step of a semiconductor device.

101... A substrate 102 whose surface is insulated at least.
103...Semiconductor Wim 104.105...Gate insulating film 106.107...Gate electrodes 108-111...Mask material 112-115...Source and drain regions 116-1
19...Offset area 120.121...Channel area and above Applicant Seiko Epson Co., Ltd. agent Patent attorney - Masayoshi Kamiyanagi (1 other person) ↓ ↓ ↓ ↓ ↓ No.↓I/1 (a) 01... Substrate 0 whose surface is insulated at least
2.103...Semiconductor thin film 04.105...Gate mystery number 06.107...Gate electrode 08-111...Mask material 12-115...Source train region 16-119
...Offset region 20.121 ...Channel region (a) ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓I/1 (b) ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓I/1 Figure 2 (d) (d) (e) Figure 2 (a) Figure 3 ↓I/1 ↓l/1 ↓I71

Claims (1)

[Claims] A semiconductor device in which a semiconductor thin film, a gate insulating film, and a gate electrode are provided on a substrate whose surface is insulated at least, and a thin film transistor is formed in a complementary manner by providing a channel region, an offset region, a source, and a drain region in the semiconductor thin film. A method for manufacturing a semiconductor device, comprising a step of mixing an impurity having one conductivity type into the entire surface of the substrate after forming the gate electrode.