JPH0282648A - Solid-state image sensing device - Google Patents

Abstract

PURPOSE:To dimensionally reduce protective circuit itself by protecting an internal circuit from an over-input by forward currents when a junction between semiconductor regions is forwardly biased and by using punch-through when the junction is reversely biased. CONSTITUTION:A p-type well region 2 as a second conductivity type semiconductor region is shaped to an n-type silicon substrate 1 as a first conductivity type semiconductor base body. An n<+> type semiconductor region 3, a first conductivity type semiconductor region, is formed in the well region 2, facing the main surface of the well region 2. When over-input voltage at low potential is applied to the P terminal 4 side between a P terminal 4 and an L terminal 6, a p-n junction between the region 3 and the region 2 is forwardly biased, and forward currents are made to flow by the junction and an internal circuit can be protected. When over-input voltage at a high potential is applied to the P terminal 4 side, the p-n junction between the region 3 and the region 2 is reversely biased. Accordingly, punch-through is generated between the substrate 1 and the semiconductor region 3, thus protecting the internal circuit from an over-input.

Description

[Detailed description of the invention] [Industrial use! l! F) The present invention relates to a solid-state L-layer image device having a protection circuit against excessive input.

[Summary of the invention]

The present invention provides a solid-state imaging device having a protection circuit against excessive input, and the protection circuit is provided in a semiconductor region of a second conductivity type formed in a semiconductor substrate of a first conductivity type and a semiconductor region of the second conductivity type. If there is an excessive input to each terminal connected to each semiconductor region, and the junction between each semiconductor region becomes forward biased, the semiconductor region When a current flows in the forward direction between the semiconductor regions and the junction between each semiconductor region is reverse biased, the current flows due to the punch-through between the first conductivity type semiconductor region and the semiconductor substrate, ensuring reliable internal circuitry. It provides protection, etc.

[Conventional technology]

Usually, in a solid-state (layer imaging device) such as a CCD, a protection circuit is provided between a band portion connected to an external pin and the internal circuit in order to protect the internal circuit.

7 and 10 respectively show protection circuits for conventional solid-state image devices, with FIG. 7 being an example for an NMOS transistor, and FIG. 10 being an example for a CMOS transistor.

Here, these protection circuits will be briefly explained. First, in an example for an nMOS transistor, a p-type well region 72 is formed on an n-type silicon substrate 71, and the p-type well region 72 is
A p° type channel stopper region 77 and n9 type source/drain regions 74 and 76 are formed in the type well region 72 . The source/drain region 74 is connected to the P terminal 73 and to the internal circuit. The source/drain region 76 is connected to the L terminal 75 and the channel stone bar region 77, and is further connected to the gate lj pole 78 via the resistive element 79.

The equivalent circuit diagram is shown in FIG. 8, where P terminal 73 and L terminal 7
An nMOS transistor 81 is provided between the terminals 5 and 5, and its gate electrode 78 is connected to the L terminal 75 via a resistive element 79. Furthermore, a bipolar transistor 82 is equivalently provided between the substrate 7I and the substrate 7I.

The protection circuit for this nMOS transistor is the P terminal 73
When a voltage lower than the L terminal 75 is applied to the L terminal 75, the bipolar transistor 82 is activated and current flows to the L terminal 75° and the substrate 71. Furthermore, when a positive pulse high voltage is applied to the P@ child 73, the potential of the gate electrode 78 increases due to the parasitic capacitance 183 between the gate electrode 78 and the source/drain region 74, and the nMOS transistor 81 is turned on. This protects the internal circuit from excessive input.

Further, as shown in FIG. 10, in a protection circuit for a CMOS transistor, a p-type well region 102 is formed in an n-type silicon substrate lO1;
, there is an n-type semiconductor region 1 connected to the P terminal 105.
03 and a p'' type semiconductor region 104 connected to the L terminal 106. On the surface of the silicon substrate 101,
Further, a P' type semiconductor region 107 is formed, and the P' type semiconductor region 107 is connected to the P terminal 105 together with the internal circuit. Figure 11 shows the equivalent circuit diagram.
A diode 11 is connected between the base FiI 01 and the P terminal 105.
1 is provided, and a bipolar transistor 112 having the L terminal 106 as a base p, the 53B+ terminal 105 as an emitter, and the substrate 101 as a collector is also provided.

In this protection circuit, if the potential 1 of the P terminal 105 is higher than the substrate potential Vsub, a forward current flows through the diode 111 between the p' type semiconductor region 107 and the substrate 101.
If the potential (2) of the P terminal 105 is lower than the potential (2) of the L terminal 106, a forward bias is applied between the n'-type semiconductor region 103 and the p-type well region 102, and a current flows through the bipolar transistor 112.

[Problem to be solved by the invention]

However, each of the above protection circuits has the following technical problems.

In the circuit for the nMOS transistor shown in Fig. 7, P
In order to operate the nMOS transistor 81 when a high voltage is input to the terminal 73, it is necessary to increase the capacitance 83. For this reason, it is necessary to route the gate electrode 7 to the source/drain region 74. For example, as shown in FIG. patterned and ultimately require a large area. Furthermore, in the operation of the MOS) transistor 81, since it is a MOS) transistor, Gm
It is not possible to obtain a large amount of This improvement also requires increasing the area. Furthermore, in response to steady excessive human power rather than pulsed human power, the MOS transistor 81 is turned off due to leakage from the gate electrode 7, and does not function as a protection circuit.

Furthermore, since both of the protection circuits shown in FIG. 10 use forward current, their current capacity becomes large. However, the diode 111 and bipolar transistor 112
limit the voltage supplied as a signal, so the signal V supplied to operate the solid-state imaging device
P (e.g. clock signal) to V, <V, <Vsub
The relationship between the parties must be satisfied. for example,
In a solid-state imaging device that performs three-value control, as shown in FIG. 12, when the substrate voltage Vsub is set to 9■, it is not possible to give a signal V of 15V as shown by the broken line, and the signal V
, is limited to 9V, making it difficult to supply sufficient voltage for transfer.

Therefore, in view of the above-mentioned technical problems, the present invention provides a solid-state imaging device that exhibits a sufficient protection function against excessive input with a small area and that also increases the degree of freedom of signals necessary for the operation of the device. purpose.

[Means to solve the problem]

In order to achieve the above object, the solid-state imaging device of the present invention has a protection circuit for protecting an internal circuit, and the protection circuit includes a semiconductor substrate of a first conductivity type and a semiconductor substrate of the first conductivity type. a second terminal formed therein and to which the second terminal is connected;
It has a conductive type semiconductor region and a first conductive type semiconductor region provided in the second conductive type semiconductor region and to which an internal circuit and a first terminal are connected. The semiconductor substrate may be, for example, a silicon substrate, and the semiconductor region of the second conductivity type may be a well region of a conductivity type opposite to that of the silicon substrate. The first conductivity type semiconductor region is formed in the second conductivity type semiconductor region and forms a PN junction with the second conductivity type semiconductor region.

In response to an excessive input in which the junctions between the semiconductor regions are forward biased, the protection circuit causes a forward current to flow between the semiconductor regions, and the junctions of the semiconductor regions are reverse biased. In response to an excessive input, current flows due to punch-through between the semiconductor region of the first conductivity type and the semiconductor substrate. Here, the voltage at which the current begins to flow due to the punch-through may be controlled by providing a semiconductor region of the second conductivity type with a controlled concentration in the semiconductor region of the second conductivity type.

Further, in addition to the configuration in which the solid-state imaging device of the present invention performs each operation in each bias described above, the parasitic capacitance between the semiconductor substrate and the semiconductor region of the second conductivity type and the semiconductor region of the second conductivity type It can also be set to a value larger than the parasitic capacitance between conductive type semiconductor regions.

Further, the solid-state imaging device of the present invention has a configuration in which the main surface of the substrate is faced through an insulating film, in addition to the configuration in which each operation is performed in each bias described above, or in addition to the configuration in which the capacitance between each semiconductor region is increased. Further, an electrode layer may be provided which is electrically connected to the semiconductor substrate, preferably a semiconductor region of the second conductivity type.

[Function] In the solid-state imaging device of the present invention, in response to an excessive input that reverse biases the junction between the respective semiconductor regions, current is caused to flow through punch-through between the substrate and the semiconductor region of the first conductivity type.
Protect internal circuits. Therefore, the nMO5 shown in FIG.
) Unlike a transistor, there is no need to increase the capacitance between the gate electrode 78 and the source/drain region 74, and since Gm is also increased, the size of the circuit can be reduced.

Furthermore, in the solid-state imaging device of the present invention, excessive inputs of two polarities do not both result in forward currents as in the protection circuit shown in FIG. 10, but punch-through occurs when excessive inputs result in reverse bias. Therefore, by controlling the voltage at which punch-through occurs, the degree of freedom in setting the signals necessary for operating the device increases.

Further, in the solid-state imaging device of the present invention, the parasitic capacitance between the semiconductor substrate and the semiconductor region of the second conductivity type is set to a larger value than the parasitic capacitance between the semiconductor region of the second conductivity type and the semiconductor region of the first conductivity type. At this time, the potential at the second terminal follows the potential at the semiconductor substrate side due to the capacitance division by these capacitances. As a result, even if no voltage is supplied to the second terminal, operation is ensured between the first terminal and the semiconductor substrate. That is, when the junction between the semiconductor regions is forward biased to the first terminal, a forward current flows, and when it is reverse biased, punch-through occurs.

Furthermore, in the solid-state imaging device of the present invention, by providing an electrode layer facing the main surface of the substrate through an insulating film and electrically connected to the semiconductor substrate or the semiconductor region of the second conductivity type,
The electrode layer becomes a part of the opposing electrode, and the parasitic capacitance between the semiconductor substrate and the second conductivity type semiconductor region increases. Further, it is also possible to electrically block the adverse effects of fixed charges in a passivation film or the like formed on the electrode layer by the electrode layer.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

First Embodiment The solid-state imaging device of this embodiment has a protection circuit as shown in FIG.
It is.

As shown in FIG. 1, the structure of the main part of the protection circuit is as follows.
is formed. In the n-type well region 2, an n-type semiconductor region 3, which is a first conductivity type semiconductor region, is formed facing the main surface thereof. Therefore, a PN junction is formed between the n-type silicon substrate 1 and the n-type well region 2 and between the n-type well region 2 and the n'-type semiconductor region 3, respectively. A P terminal 4, which is a first terminal, is connected to this n-type semiconductor region 3.

This P terminal 4 is supplied with a signal to be sent to an internal circuit in order to operate a required device, such as a transfer signal to a transfer electrode for three-value control. That is,
A signal is supplied to the internal circuit from a node 8 between the P terminal 4 and the n° type semiconductor region 3. The above n-type well region 2
A p-type semiconductor region 5 is formed on the main surface of the substrate. This P' type semiconductor region 5 has a second terminal and a terminal 6.
is connected to the well region 2, and functions as an extraction region for the well region 2. Further, on the main surface of the n-type silicon substrate 1, an n°
A type semiconductor region 7 is formed, and a required substrate voltage sub is supplied to this n-type semiconductor region 7. By providing the extraction area near the protection circuit in this way, the collector resistance can be reduced.

In the solid-state imaging device of this embodiment, the n-type well region 2
Inside, an n-type impurity doped region 9 is formed in a region between the n-type semiconductor region 3 and the silicon substrate 1. This n-type impurity doped region 9 is for controlling the potential of the n-type well region 2, and the voltage at which punch-through occurs is determined by controlling the potential. Therefore, in order to set the voltage at which punch-through occurs to a predetermined value, it is necessary to appropriately select the ion implantation conditions for forming the impurity-introduced region 9, such as the depth, a degree, etc.

FIG. 2 shows an equivalent circuit of the protection circuit shown in FIG. 1. The protection circuit having the above structure is substantially equivalent to one npn type bipolar transistor IO. That is,
The n-type semiconductor region 3 connected to the P terminal 4 is the emitter 5.
The p-type semiconductor region 5 and the n-type well region 2 connected to the L terminal 6 function as a base, and the silicon substrate 1 functions as a collector. In addition, between the emitter base,
A parasitic capacitance it Ct m is formed, and a parasitic capacitance ICgc is formed between the base and the collector. Further, the emitter-base breakdown voltage is determined by the distance between the n' type semiconductor region 3 and the p' type semiconductor region 5.

Here, the operation of the protection circuit will be explained.

First, when an excessive input voltage is applied between the P terminal 4 and the L terminal 6 such that the P terminal 4 side has a low potential, is the n-type semiconductor? ■The PN junction between region 3 and p-type well region 2 becomes forward biased, and a forward current flows through that junction, activating the bipolar transistor IO shown in Figure 2 and protecting the internal circuit from the excessive power. can. This operating state is
P when both the substrate voltage and the L terminal voltage are ground voltage GND
Referring to FIG. 4, which shows the relationship between the voltage (2) applied to the terminal and the current I, it can be expressed by a curve A in the 61 range where the applied voltage VP is a negative voltage. For example, L terminal 6 to 9
When (2) is being applied, a forward current due to forward bias will flow when the voltage V applied to the P terminal 4 is smaller than (19).

Next, when an excessive input voltage such as a high voltage is applied to the P terminal 4 side is applied, the PN junction between the n° type semiconductor region 3 and the p type well region 2 becomes reverse biased. Therefore, a depletion layer grows in the PN junction in response to the applied voltage V. To explain the potential at this time with reference to Figure 3, when there is no bias, p
The potential has a peak in the well region 2 of the mold.

However, as the voltage applied to the P terminal 4 increases, the potential of the n° type semiconductor region 3 changes to the curve C+.
, Ct, and C3, the peak of the p-type well region 2 gradually moves deeper toward the substrate, and at the same time, the peak becomes lower. As a result, punch-through occurs between the silicon substrate 1 and the n-type semiconductor region 3, and the internal circuit is protected against excessive input. In Fig. 4, the current value Ip is almost zero when the positive applied voltage (■) is in the range of O to ■1 (curve B0), and the curve B1 (curve B1) where the current significantly flows when the punch-through occurs above ■0. ing. Therefore, the input voltage ■ to P terminal 4 is O~
Within the range of Vat, the input can be sent to the internal circuit without being treated as an excessive input.In other words, the signal necessary for the operation of the internal circuit can be sent freely if it is below pt where punch-through occurs. This means that it can be set to .

The voltages vI and L at which punch-through occurs can be selected by selecting the ion implantation conditions for forming the impurity-introduced region 9 shown in FIG. 1, especially in the solid-state imaging device of this embodiment. For example, when the p-type impurity concentration is increased, the peak of the potential in FIG. 3 becomes higher, and the voltage ■2. can be made higher. Here, the voltage ■1 at which punch-through occurs is usually 5■ ~
It is about IOV, and when the substrate voltage is 9■, it is 14
At least punch-through does not occur up to ~19V.

Therefore, if the voltage VIIL is about IOV, then 15V
This means that a relatively high level signal can be sufficiently supplied to the transfer electrodes.

In this way, in the solid-state imaging device of this embodiment, when the junction between the p-type well region 2 and the n-type semiconductor region 3 is forward biased, the internal circuit can be protected from excessive input by the forward current. . Furthermore, when the junction is reverse biased, punch-through can protect the internal circuitry against excessive input.

Therefore, there is no need to route the n-type semiconductor region 3 and the like in order to increase the capacity, and the protection circuit itself can be made smaller. Furthermore, it operates satisfactorily even with input other than pulse input. Furthermore, in the case of reverse bias, current flows by punch-through, so by selecting the voltage V IIL at which punch-through occurs, it is possible to send sufficient signals necessary for the operation of the internal circuit. Moreover, the setting of the voltage (1) is based on the impurity introduced region 9
It is also possible to select according to the ion implantation conditions.

Note that in the above example, the first conductivity type is n-type and the second conductivity type is p-type, but they may be of opposite conductivity types.

Second Embodiment This embodiment is a modification of the first embodiment, and as shown in FIG. This is an example where .

As shown in FIG. 5, its structure consists of an n-type silicon substrate 21 as a semiconductor base, a p-type well region 22 which is a second conductivity type semiconductor region for forming a protection circuit, and an image of a CCD. p-type well M'29
is formed. The p-type well region 22 includes an n-type semiconductor region 23 connected to the P-terminal 24 and a p-type semiconductor region connected to the L-terminal 26 to form a protection circuit, as in the first embodiment. 25 are provided. that n
A PN junction is formed between the ゛-type semiconductor region 23 and the p-type well region 22. Further, a substrate voltage V sub is applied to the n-type silicon substrate 21 via the n-type semiconductor region 27 . The P terminal 24 is branched and connected to an internal circuit. Therefore, the internal circuit can be protected by the forward current against an excessive input that causes the junction between the p-type well region 22 and the n-type semiconductor region 23 to be forward-biased. Also,
The internal circuit can be protected by punch-through against excessive input where the junction is reverse biased.

In the p-type well region 29, although not shown, a part of the sensor and a charge transfer section are formed, and a channel stomper region 28 made of a p9-type semiconductor region is also formed on its main surface. This channel stopper region 28 is disposed around the p-type well region 29 and has a ground voltage GN
D is supplied to prevent channel formation.

The solid-state imaging device of this embodiment having such a structure includes a silicon substrate 21 or a p-type well region 22, which faces the main surface of the substrate through an insulating film (not shown).
Electrode layers 31, 32, 33 are provided which are electrically connected to 29. These electrode layers 31 to 33 extend from above the p-type well region 22.29 to above the main surface of the n-type silicon substrate 21. The electrode layer 31 is the p′ type semiconductor region 25
The electrode layer 32 is connected to the n-type semiconductor region 27, and the electrode layer 33 is connected to the channel stomper region 2.
Connect to 8. There are two main functions of each of the electrode layers 31, 32, 33.

One is to extend it over the main surface of the n-type silicon substrate 21 to prevent the formation of a parasitic pMO3) disk. That is, solid-state imaging devices use glabella insulating films, passivation films, and the like, and fixed charges exist in these insulating films. However, when a large number of fixed charges exist on the substrate surface, a problem arises because a channel is formed between the p-type well region 29 and the p-type well region 22. Therefore, by providing each of the electrode layers 31, 32, and 33, it becomes possible not only to prevent contamination but also to electrically shield from fixed charges. Another function is that the silicon substrate 21 and p
The objective is to make the parasitic capacitance Cl1c between the p-type well 8N region 22 and the n-type semiconductor region 23 larger than the parasitic field Vices between the p-type well 8N region 22 and the n-type semiconductor region 23. Fifth
Just by looking at the cross-sectional structure in the figure, you can see the 'parasitic field' from the comparison of the size of the depletion layer! kctm>parasitic capacitance CIC, but by providing the electrode layers 31 and 32 electrically connected to the silicon substrate 21 or the p-type well region 22, the parasitic field 1 cm cO value increases. Become. As the parasitic capacitance CSC increases in this way, the L terminal 2
6 is open and an excessive input is applied between the P terminal 24 and the silicon substrate 21, the potential of the L terminal 26 becomes the potential on the silicon substrate 21 side.

Therefore, when a negative voltage is applied to the P terminal 24, a forward current is obtained, and when a voltage higher than that at which punch-through occurs is applied to the P terminal 24, the internal circuit is protected by punch-through. That will happen.

In the above embodiment, all of the electrode layers 31 to 33 are provided, but a structure in which any one or two types of electrode layers are provided may be used.

Furthermore, although the description has been made assuming that the first conductivity type is n type and the second conductivity type is p type, they may be of the opposite four conductivity types.

Third Embodiment This embodiment is an example of a solid-state imaging device that is particularly characterized by its layout.

As shown in a schematic plan view in FIG. 6, the structure is such that protection circuits 43, 44, 45 are formed for pad portions 46, 47, 48 as P terminals, respectively. Each of the protection circuits 43 to 45 has the structure described in the first or second embodiment, for example. Those protection circuits 43 to 45
Although the wiring for the terminals is also performed, in particular, in this embodiment, the wiring is performed using a common wiring pattern 42, and the pad portion 41 for the L terminal and each protection circuit 43 to
45. The wiring pattern 42 has a long distance on the chip because it is commonly used! It is routed and wired. Therefore, the parasitic capacitance 1c associated with the wiring increases between the wiring pattern 4 and the substrate.
2 is connected to the protection circuit as the base of the bipolar transistor IO shown in FIG. Therefore, in the solid-state imaging device, even when no voltage is applied to the L terminal, a forward current is obtained when a negative voltage is applied to the P terminals 46 to 48, and the P terminals 46 to 48 are punched. When a voltage higher than that at which through occurs is applied, the internal circuit is protected by punch through.

Note that the wiring pattern 42 is not limited to a substantially linear pattern as shown in the drawing.

〔Effect of the invention〕

In the solid-state imaging device of the present invention, when the junction between the first and second conductivity type semiconductor regions is forward biased as described above, the internal circuit is protected by a forward current, and the junction is reverse biased. punch-through can protect the internal circuitry from excessive input. For this reason, the protection circuit itself can be made smaller and can operate satisfactorily even with inputs other than pulse inputs. Furthermore, since the voltage at which punch-through occurs can be set, the degree of freedom in signals necessary for operating internal circuits is also increased.

In addition, by increasing the parasitic capacitance between the semiconductor substrate and the second conductivity type semiconductor region, even if the second terminal is left open, the internal circuit can be reliably protected, and the electrode layer can be used. By doing so, it is possible not only to obtain the effect of increasing the capacitance, but also to prevent the formation of parasitic MO3) run disks.

[Brief explanation of the drawing]

The first is a schematic sectional view of the main part of an example of the solid-state imaging device of the present invention, FIG. 2 is an equivalent circuit diagram thereof, and FIG. 3 is a diagram showing changes in potential when voltage is applied to the main part. FIG. 4 is a diagram showing the relationship between the voltage applied to the P terminal and the current I when the ground voltage GND is applied to the L terminal and the substrate, and FIG. 5 is a diagram of another example of the solid-state imaging device of the present invention. FIG. 6 is a schematic sectional view of the main part of still another example of the solid-state imaging device of the present invention. Further, FIG. 7 is a schematic cross-sectional view of a main part of an example of a conventional solid-state imaging device, and FIG. 8 is an equivalent circuit diagram of a main part of an example of the conventional solid-state imaging device.
FIG. 9 shows a layout of the main parts of an example of the conventional technology. Furthermore, FIG. 10 is a schematic sectional view of the main parts of another example of the conventional solid-state 1M imaging device, FIG. 11 is an equivalent circuit diagram of the main parts of the conventional example, and FIG. 12 is the operating example of the conventional example. FIG. 3 is a waveform diagram of a signal when 3.23...n° type semiconductor region 4.24...P terminal 5.25...p' type semiconductor region 626...terminal 9...impurity introduced regions 31 to 33...・Electrode layer C,,,C,c,C,... Parasitic capacitance patent applicant Akira Koike, patent attorney representing Sony Corporation (and 2 others) 1.21... N-type silicon substrate 2.22. 29...p-type well region Δ-itagepu 1
Nii Itoro CCD calculation 1 Figure equivalent times? Valley Fig. 2 Fig. 3 Fig. 4/L Litho Fig. 7 Fig. 8 Fig. 9 Suitable rice example Fig. 10 Fig. n1 Fig. 11 Fig. 12

Claims (3)

[Claims] (1) In a solid-state imaging device having a protection circuit for protecting an internal circuit, the protection circuit includes a semiconductor substrate of a first conductivity type and a second conductivity type semiconductor substrate formed in the semiconductor substrate and connected to a second terminal. It has a semiconductor region of a conductivity type, and a semiconductor region of a first conductivity type provided in the semiconductor region of a second conductivity type to which an internal circuit and a first terminal are connected, and between each of the semiconductor regions. For an excessive input that causes the junction to be forward biased, a forward current flows between each semiconductor region, and for an excessive input that causes the junction of each semiconductor region to be reverse biased, a current flows between the semiconductor regions of the first conductivity type. A solid-state imaging device characterized in that current flows through punch-through between a region and a semiconductor substrate. (2) A claim characterized in that the parasitic capacitance between the semiconductor substrate and the semiconductor region of the second conductivity type is larger than the parasitic capacitance between the semiconductor region of the second conductivity type and the semiconductor region of the first conductivity type. The solid-state imaging device according to item (1). (3) An electrode layer facing the main surface of the substrate through an insulating film and electrically connected to the semiconductor substrate or the semiconductor region of the second conductivity type is provided. 2) The solid-state imaging device described in section 2).