JPH0282633A - Mounting structure of semiconductor element - Google Patents
Mounting structure of semiconductor elementInfo
- Publication number
- JPH0282633A JPH0282633A JP23563188A JP23563188A JPH0282633A JP H0282633 A JPH0282633 A JP H0282633A JP 23563188 A JP23563188 A JP 23563188A JP 23563188 A JP23563188 A JP 23563188A JP H0282633 A JPH0282633 A JP H0282633A
- Authority
- JP
- Japan
- Prior art keywords
- curing
- semiconductor element
- resin
- mounting
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 229920005989 resin Polymers 0.000 claims abstract description 45
- 239000011347 resin Substances 0.000 claims abstract description 45
- 239000002184 metal Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims description 10
- 230000000694 effects Effects 0.000 abstract description 5
- 230000003287 optical effect Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 230000007257 malfunction Effects 0.000 abstract 1
- 238000001723 curing Methods 0.000 description 30
- 229920001187 thermosetting polymer Polymers 0.000 description 7
- 230000002950 deficient Effects 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000000178 monomer Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 125000003178 carboxy group Chemical group [H]OC(*)=O 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000011342 resin composition Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83909—Post-treatment of the layer connector or bonding area
- H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野１
本発明は、半導体素子と基板との実装構造に関し、特に
フェースダウン実装に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a mounting structure for a semiconductor element and a substrate, and particularly to face-down mounting.
［従来の技術１
従来、フェースダウンによる半導体素子と基板との実装
は、例えば特開昭６０−２６２４３０号公報に記載され
、第２図に示すような構造が知られていた。第２図にお
いて、１は配線基板であり、この上に配線パターン２が
形成しである。配線基板１は、ガラス、セラミクス、樹
脂もしくは金属酸化物を表面に被覆した金属等の表面に
、少くとも半導体素子６の金属突起４と対応した位置に
配線パターン２が形成しである。配線パターンは、金属
であれば何でも良い、配線基板１上かもしくは、半導体
素子６の能動面上に、光又は熱硬化性樹脂９を塗布、載
置する９次に、半導体素子上の金属突起４と配線基板１
上の配線パターン２とを位置合わせし、両者を圧接する
。この圧接により・、光又は熱硬化性樹脂９は押し広げ
られ、金属突起４と配線パターン２とは電気的接続を得
、結構半導体素子６上に形成された電極パッド５と、配
線パターン２との電気的接続が得られる。[Prior Art 1] Conventionally, face-down mounting of a semiconductor element and a substrate is described in, for example, Japanese Patent Laid-Open No. 60-262430, and a structure as shown in FIG. 2 has been known. In FIG. 2, 1 is a wiring board, on which a wiring pattern 2 is formed. The wiring board 1 has a wiring pattern 2 formed on the surface of glass, ceramics, resin, metal coated with a metal oxide, etc., at least at a position corresponding to the metal protrusion 4 of the semiconductor element 6. The wiring pattern may be any metal as long as it is metal.A photo or thermosetting resin 9 is applied and placed on the wiring board 1 or the active surface of the semiconductor element 6.Next, metal protrusions on the semiconductor element are formed. 4 and wiring board 1
Align the upper wiring pattern 2 and press them together. Due to this pressure contact, the optical or thermosetting resin 9 is pushed out and the metal protrusion 4 and the wiring pattern 2 are electrically connected, and the electrode pad 5 formed on the semiconductor element 6 and the wiring pattern 2 are connected to each other. electrical connection is obtained.
この状態で、光又は熱硬化性樹脂８に、光もしくは熱を
加えれば、その樹脂は硬化するので、半導体素子６と配
線基板１とは、上記電気的導通が保持されたまま固定さ
れる。In this state, if light or heat is applied to the thermosetting resin 8, the resin will be cured, so that the semiconductor element 6 and the wiring board 1 are fixed while maintaining the electrical continuity.
［発明が解決しようとする課題］
しかし、従来の半導体素子の実装構造では、半導体素子
と配線基板との保持に、光硬化型樹脂又は熱硬化型樹脂
を用いたため、以下のような問題点を有していた。[Problems to be Solved by the Invention] However, in the conventional semiconductor element mounting structure, a photocurable resin or a thermosetting resin is used to hold the semiconductor element and the wiring board, which causes the following problems. had.
光硬化型樹脂を用いる場合、光硬化型樹脂は、熱硬化型
樹脂に比較して３次元硬化が完全てないため、半導体素
子の実装を失敗した場合の再実装、すなわち半導体素子
を一度はく離し５再び実装することは比較的容易な反面
、実装の信頼性特に通電耐湿性には劣るという問題点が
あった。When using a photocurable resin, the three-dimensional curing of the photocurable resin is not as complete as that of a thermosetting resin, so if a semiconductor element fails to be mounted, it must be remounted, that is, the semiconductor element must be peeled off once. 5. Although it is relatively easy to remount the device, there is a problem in that the reliability of the mounting, especially the resistance to current and moisture, is poor.
熱硬化型樹脂を用いる場合、前記とは逆に３次元硬化が
進んでいるため、実装の信頼性は高いものの、半導体素
子の再実装性には劣るという問題点を有していた。When a thermosetting resin is used, contrary to the above, three-dimensional curing progresses, so although the reliability of mounting is high, the remountability of semiconductor elements is poor.
このような相反する問題点を解決するため、本発明では
、半導体素子と配線基板の再実装性にすぐれ、かつ実装
後は、実装信頼性も高い半導体素子の実装構造を得るこ
とを目的としている。In order to solve these contradictory problems, the present invention aims to obtain a semiconductor element mounting structure that has excellent remountability of the semiconductor element and wiring board and also has high mounting reliability after mounting. .
［課題を解決するための手段］
上記問題点を解決するため、本発明の半導体素子の実装
構造では、電極上に金属突起を有する半導体素子と、前
記電極と相対する配線パターンを有↑る基板とから成り
、前記半導体素子と前記基板とはフェースダウンにて実
装されており、前記半導体素子と前記基板との間には樹
脂が存在する半導体素子の実装構造において、前記樹脂
は異なる硬化メカニズムによって、第一段階の硬化では
完全に３次元硬化せず、第二段階の硬化で完全に３次元
硬化することを特徴とする。[Means for Solving the Problems] In order to solve the above problems, the semiconductor element mounting structure of the present invention includes a semiconductor element having a metal protrusion on an electrode, and a substrate having a wiring pattern facing the electrode. In a mounting structure for a semiconductor element in which the semiconductor element and the substrate are mounted face-down, and a resin is present between the semiconductor element and the substrate, the resin is cured by a different curing mechanism. , it is characterized by not being completely three-dimensionally cured in the first stage of curing, but completely three-dimensionally curing in the second stage of curing.
〔作 用］
本発明では、半導体素子と配線基板との間に存在する樹
脂が、第一段階の硬化では完全に３次元硬化せず、第二
段階の硬化で完全に３次元硬化するために、第一段階の
硬化時に半導体素子と配線基板との電気的接続を確認し
、もし接続が完全ならば、第二段階の硬化へ進み、樹脂
を完全硬化させて、良好な接続信頼性を得る。もし、接
続が完全でなければ、その次点で半導体素子を配線基板
からはく離し、不良力所を修正・取りかえ再度半導体素
子を配線基板へ実装することができ、最終的に半導体素
子と配線基板との完全な電気的接続、接続信頼性を得る
ことができる。[Function] In the present invention, the resin present between the semiconductor element and the wiring board is not completely three-dimensionally cured in the first stage of curing, but is completely three-dimensionally cured in the second stage of curing. , Check the electrical connection between the semiconductor element and the wiring board during the first stage of curing, and if the connection is complete, proceed to the second stage of curing to completely cure the resin and obtain good connection reliability. . If the connection is not perfect, then the semiconductor element can be peeled off from the wiring board, the defective force points can be corrected and replaced, and the semiconductor element can be mounted on the wiring board again. You can get a complete electrical connection and connection reliability.
［実 施 例］
以下に１本発明の実施例を図面に基き、詳細に説明する
。[Example] An example of the present invention will be described below in detail with reference to the drawings.
第１図は、本発明の半導体素子の実装構造の断面図であ
る。半導体素子６の電極パッド５に、例えばＣｒ−Ｃｕ
、Ｔｉ−Ｐｄ等の金属を被着した後、金属突起４を形成
する。金属突起４はＡｕ、Ｃｕ、ハンダ等の金属であり
、電気メツキ、スパッタ、蒸着等で数ｕｍ〜数１０μｍ
の厚さに形成されることが多い、配線基板１は、ガラス
、セラミクス、樹脂等であり、少（とも表面が絶縁され
ており、半導体素子６の金属突起４と対応した位置に配
線パターン２が形成されている。FIG. 1 is a sectional view of a mounting structure for a semiconductor element of the present invention. For example, Cr-Cu is applied to the electrode pad 5 of the semiconductor element 6.
, Ti--Pd, etc., and then the metal protrusions 4 are formed. The metal protrusion 4 is made of metal such as Au, Cu, or solder, and is formed by electroplating, sputtering, vapor deposition, etc. to a thickness of several um to several tens of μm.
The wiring board 1, which is often formed to a thickness of is formed.
配線パターン２は、金属もしくは金属酸化物を用いるの
が一般的であり、Ｎｉ、Ｃｕ、Ａｕ、Ａｌ又はＩＴＯ等
で形成すれば良く、必要に応じてメツキ処理を施せば良
い、配線基板１面上かもしくは半導体素子６の金属突起
４を形成した面上（こ２段階硬化型樹脂３を塗布、ある
いは設置する。２段階硬化型樹脂３は、液状もしくはシ
ート状である。The wiring pattern 2 is generally made of metal or metal oxide, and may be formed of Ni, Cu, Au, Al, ITO, etc., and may be plated if necessary. The two-step curing resin 3 is applied or placed on the surface of the semiconductor element 6 on which the metal projections 4 are formed.The two-step curing resin 3 is in the form of a liquid or a sheet.
次に、半導体素子６上の金属突起４と、配線基板ｌ上の
配線パターン２とを位置合わせし、両者を圧接する。す
ると、金属突起４と配線パターン２によって２段階硬化
型樹脂３は押し広げられ、金属突起４と配線パターン２
とは電気的に接続する。この状態で、第１段階の硬化を
行う。この段階では、２段階硬化型樹脂３の３次元硬化
は完全ではない、この状態で、半導体素子６と配線パタ
ーン２との電気的接続の不良を確認する。このためには
、半導体素子６の入力電極パッドに相対する配線パター
ンに所定の入力信号、電源を印加し、半導体素子６の出
力電極パッドに相対する配線パターンに所定の出力信号
が得られるかどうか確認すれば良い。電気的接続が正常
に行われていることが確認できれば、第２段階の硬化へ
移行する。電気的接続に異常があれば、まだ第２段階硬
化型樹脂３は完全硬化していないので、半導体素子６は
配線基板ｌから容易にはく離することができる。２段階
硬化樹脂３を半導体素子６と、配線基板１から例えば溶
剤を用いて取り去り、前述した通りにもう一度、半導体
素子６を配線基板１へ実装する。電気的接続が正常にな
るまでの操作を続ける。前述の操作は、電気的接続が不
良の場合のみならず、半導体素子６の不良、配線パター
ン２の不良の場合も有効であり、この場合は不良部品を
交換し、もう−度実装の手順をくり返す。Next, the metal protrusions 4 on the semiconductor element 6 and the wiring pattern 2 on the wiring board l are aligned and pressed together. Then, the two-step curing resin 3 is pushed out by the metal protrusion 4 and the wiring pattern 2, and the metal protrusion 4 and the wiring pattern 2
electrically connected to. In this state, the first stage of curing is performed. At this stage, the three-dimensional curing of the two-step curing resin 3 is not complete. In this state, a defect in the electrical connection between the semiconductor element 6 and the wiring pattern 2 is checked. To do this, apply a predetermined input signal and power to the wiring pattern facing the input electrode pad of the semiconductor element 6, and check whether a predetermined output signal is obtained from the wiring pattern facing the output electrode pad of the semiconductor element 6. Just check. If it is confirmed that the electrical connection is properly made, the process moves to the second stage of curing. If there is an abnormality in the electrical connection, the semiconductor element 6 can be easily peeled off from the wiring board 1 since the second stage curing resin 3 has not yet been completely cured. The two-step cured resin 3 is removed from the semiconductor element 6 and the wiring board 1 using, for example, a solvent, and the semiconductor element 6 is mounted on the wiring board 1 again as described above. Continue operation until the electrical connection is normal. The above operation is effective not only when the electrical connection is defective, but also when the semiconductor element 6 is defective or the wiring pattern 2 is defective. In this case, replace the defective part and repeat the mounting procedure. Repeat.
正常な電気的接続が得られた時点で、第２段階の硬化を
行い、２段階硬化型樹脂３の３次元硬化を完結させ、半
導体素子６と配線基板ｌとの電気的接続が保持されたま
ま、固定され続ける。こうして、電気的接続信頼性は保
たれるが、さらに耐２♀性を向上させるために、２段階
硬化型樹脂３の周囲を絶縁樹脂１０を塗布しても良い。When a normal electrical connection was obtained, a second stage of curing was performed to complete the three-dimensional curing of the two-stage curing resin 3, and the electrical connection between the semiconductor element 6 and the wiring board l was maintained. It remains fixed. In this way, electrical connection reliability is maintained, but in order to further improve the 2♀ resistance, an insulating resin 10 may be applied around the two-step curing resin 3.
また、さらに接続信頼性を向上させるために、２段階硬
化型樹脂３の中に、Ａｕ、Ａｇ、Ｎｉ、Ｃｒ、ハンダ、
あるいはそれらのメツキ物等から成る導電粒子を混入し
ても良い。こうすれば、金属突起４と配線パターン２と
の間に導電粒子が存在することになり、圧着のマージン
はさらに拡大する。In addition, in order to further improve the connection reliability, the two-step curing resin 3 contains Au, Ag, Ni, Cr, solder, etc.
Alternatively, conductive particles made of plated materials thereof may be mixed. In this way, conductive particles are present between the metal protrusion 4 and the wiring pattern 2, and the crimp margin is further expanded.
さて、次に、２段階硬化樹脂３の実際の構成について述
べる。２段階硬化樹脂は、光／熱併用型硬化樹脂、ある
いは光／室温放置硬化型等を用いれば良い。具体例を光
／熱併用型樹脂を用いて説明する。Now, next, the actual structure of the two-stage cured resin 3 will be described. As the two-step curing resin, a combination light/heat curing resin, a light/room temperature curing type, or the like may be used. A specific example will be explained using a combined light/heat type resin.
具体的な樹脂の構成としては、
ＣＨ，＝ＣＨＣ−０−Ｒ−ＣＯＯＨ（１）で示されるＣ
０ＯＨ基含有光重合性モノマーと、で示されるエポキシ
化合物から成る。The specific resin composition is CH,=CHC-0-R-COOH (1).
It consists of an 0OH group-containing photopolymerizable monomer and an epoxy compound represented by.
すなわち、第一段階では前述の混合物に光、例えば紫外
線を照射する。すると、
で示されるような、Ｃ０ＯＨ基含有光重合性モノマーの
重合体が生成し、未完全３次元硬化樹脂となる。That is, in the first step, the aforementioned mixture is irradiated with light, for example ultraviolet light. Then, a polymer of the C0OH group-containing photopolymerizable monomer as shown in the following is generated, resulting in an incomplete three-dimensionally cured resin.
次に、第２段階では、さらに加熱を行う。すると
で示されるような三次元網目構造となり、完全硬化樹脂
が得られる。Next, in the second stage, further heating is performed. This results in a three-dimensional network structure as shown in , and a completely cured resin is obtained.
［発明の効果］
以上、説明したように本発明による半導体素子の実装構
造では、半導体素子と配線基板との間に２段階効果樹脂
を存在させ、それらを保持させる構造としたので、以下
の効果を持つ。[Effects of the Invention] As explained above, in the semiconductor element mounting structure according to the present invention, the two-stage effect resin is present between the semiconductor element and the wiring board to hold them, so that the following effects can be achieved. have.
（１）２段階効果樹脂の第１段硬化の時点では樹脂が完
全に３次元硬化していないため、実装ミスがあっても半
導体素子を配線基板からはずし、再実装することができ
、続いて、実装ミスが無いことがわかってから第２段硬
化を行い完全３次元硬化を行えるといった、従来の１段
階硬化型樹脂では非常に困難であった半導体素子の高リ
ペア性と、同時に高接続信頼性を賦与することができる
ようになった。(1) Two-stage effect: Because the resin is not completely three-dimensionally cured during the first stage of curing, even if a mounting error occurs, the semiconductor element can be removed from the wiring board, remounted, and then After confirming that there are no mounting errors, the second stage of curing can be performed to achieve complete three-dimensional curing, which is extremely difficult to achieve with conventional one-stage curing resins, and at the same time provides high connection reliability. It is now possible to give gender.
（２）上記の結果、実装不良が無くなるため、実装コス
トが大幅に低減することができる。(2) As a result of the above, since mounting defects are eliminated, mounting costs can be significantly reduced.
（３）第１段階での半導体素子の固定は完全でなくて良
いため、光硬化性樹脂で問題となる不透明基板を用いて
も半導体素子の周囲に存在する２段階硬化樹脂のみを第
１段階で固化させ、第２段階で半導体素子と不透明基板
の樹脂もすべて３次元硬化させることができるので高い
実装信頼性を得ることができる。(3) The semiconductor element does not need to be completely fixed in the first stage, so even if an opaque substrate, which is a problem with photocurable resin, is used, only the two-stage cured resin that exists around the semiconductor element can be used in the first stage. In the second step, the resin of the semiconductor element and the opaque substrate can all be three-dimensionally cured, so high mounting reliability can be obtained.
第１図は本発明による半導体素子の実装構造を示す断面
図であり、第２図は従来の半導体素子の実装構造を示す
断面図である。
配線基板
配線パターン
２段階硬化型樹脂
金属突起
電極パッド
半導体素子
光又は熱硬化型樹脂
絶縁樹脂FIG. 1 is a sectional view showing a semiconductor element mounting structure according to the present invention, and FIG. 2 is a sectional view showing a conventional semiconductor element mounting structure. Wiring board wiring pattern 2-step curing resin Metal protrusion electrode pad Semiconductor device Optical or thermosetting resin Insulating resin
Claims (1)
対する配線パターンを有する基板とから成り、前記半導
体素子と前記基板とはフェースダウンにて実装されてお
り、前記半導体素子と前記基板との間には樹脂が存在す
る半導体素子の実装構造において、前記樹脂は異なる硬
化メカニズムによって、第一段階の硬化では完全に３次
元硬化せず、第二段階の硬化で完全に３次元硬化するこ
とを特徴とする半導体素子の実装構造。It consists of a semiconductor element having a metal protrusion on an electrode, and a substrate having a wiring pattern facing the electrode, and the semiconductor element and the substrate are mounted face-down, and the semiconductor element and the substrate are mounted face-down. In a semiconductor device mounting structure in which a resin exists between the resins, the resin has a different curing mechanism, so that it is not completely three-dimensionally cured in the first stage of curing, but is completely three-dimensionally cured in the second stage of curing. Characteristic semiconductor element mounting structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23563188A JPH0282633A (en) | 1988-09-20 | 1988-09-20 | Mounting structure of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23563188A JPH0282633A (en) | 1988-09-20 | 1988-09-20 | Mounting structure of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0282633A true JPH0282633A (en) | 1990-03-23 |
Family
ID=16988879
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23563188A Pending JPH0282633A (en) | 1988-09-20 | 1988-09-20 | Mounting structure of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0282633A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0319251A (en) * | 1989-06-15 | 1991-01-28 | Matsushita Electric Ind Co Ltd | Inspection method for semiconductor device |
| JPH03195033A (en) * | 1989-12-25 | 1991-08-26 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
| JPH0714880A (en) * | 1991-03-22 | 1995-01-17 | Semiconductor Energy Lab Co Ltd | Mounting method for chip of semiconductor integrated circuit and electronic equipment mounted therewith |
| US6081038A (en) * | 1998-04-07 | 2000-06-27 | Shinko Electric Industries Co., Ltd. | Semiconductor chip package structure |
| JP2002538626A (en) * | 1999-03-03 | 2002-11-12 | インテル・コーポレーション | Controlled collapsed chip connection (C4) integrated circuit package with two different underfill materials |
| WO2007058142A1 (en) * | 2005-11-21 | 2007-05-24 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing circuit board having electronic part |
| JP2008027921A (en) * | 2007-09-03 | 2008-02-07 | Hitachi Chem Co Ltd | Connection member, and connection structure and connection method of electrode using same |
| JP2010010142A (en) * | 2009-10-07 | 2010-01-14 | Hitachi Chem Co Ltd | Thermosetting circuit connection member and connection structure of electrode using it and connecting method of electrode |
| CN102361005A (en) * | 2011-08-19 | 2012-02-22 | 清华大学 | Capping shutter control method in scanning laser processing of film board |
-
1988
- 1988-09-20 JP JP23563188A patent/JPH0282633A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0319251A (en) * | 1989-06-15 | 1991-01-28 | Matsushita Electric Ind Co Ltd | Inspection method for semiconductor device |
| JPH0666356B2 (en) * | 1989-06-15 | 1994-08-24 | 松下電器産業株式会社 | Semiconductor device mounting method |
| JPH03195033A (en) * | 1989-12-25 | 1991-08-26 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
| JPH0714880A (en) * | 1991-03-22 | 1995-01-17 | Semiconductor Energy Lab Co Ltd | Mounting method for chip of semiconductor integrated circuit and electronic equipment mounted therewith |
| US6081038A (en) * | 1998-04-07 | 2000-06-27 | Shinko Electric Industries Co., Ltd. | Semiconductor chip package structure |
| JP2002538626A (en) * | 1999-03-03 | 2002-11-12 | インテル・コーポレーション | Controlled collapsed chip connection (C4) integrated circuit package with two different underfill materials |
| WO2007058142A1 (en) * | 2005-11-21 | 2007-05-24 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing circuit board having electronic part |
| JPWO2007058142A1 (en) * | 2005-11-21 | 2009-04-30 | パナソニック株式会社 | Method for manufacturing a circuit board on which electronic components are mounted |
| US8205327B2 (en) | 2005-11-21 | 2012-06-26 | Panasonic Corporation | Method for manufacturing circuit board on which electronic component is mounted |
| JP2008027921A (en) * | 2007-09-03 | 2008-02-07 | Hitachi Chem Co Ltd | Connection member, and connection structure and connection method of electrode using same |
| JP4631889B2 (en) * | 2007-09-03 | 2011-02-16 | 日立化成工業株式会社 | Connection member, electrode connection structure and connection method using the connection member |
| JP2010010142A (en) * | 2009-10-07 | 2010-01-14 | Hitachi Chem Co Ltd | Thermosetting circuit connection member and connection structure of electrode using it and connecting method of electrode |
| CN102361005A (en) * | 2011-08-19 | 2012-02-22 | 清华大学 | Capping shutter control method in scanning laser processing of film board |
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