JPH0666356B2 - Semiconductor device mounting method - Google Patents
Semiconductor device mounting methodInfo
- Publication number
- JPH0666356B2 JPH0666356B2 JP1153384A JP15338489A JPH0666356B2 JP H0666356 B2 JPH0666356 B2 JP H0666356B2 JP 1153384 A JP1153384 A JP 1153384A JP 15338489 A JP15338489 A JP 15338489A JP H0666356 B2 JPH0666356 B2 JP H0666356B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- mounting
- conductive adhesive
- circuit board
- inspection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置の検査方法に係わり、特に、回路
基板の導体電極上に半導体装置を導電性接着剤を用いて
フェイスダウンボンディングにより実装する半導体装置
の実装法における半導体装置の検査方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inspecting a semiconductor device, and more particularly to a semiconductor in which a semiconductor device is mounted on a conductor electrode of a circuit board by face down bonding using a conductive adhesive. The present invention relates to a semiconductor device inspection method in a device mounting method.
従来の技術 従来、半導体装置の接続端子と回路基板の導体電極との
接続には半田付けがよく利用されてきたが、近年、フラ
ットパッケージ等の小型化と接続端子の増加により、接
続端子間いわゆるピッチ間隔が次第に狭くなり、従来の
半田付け技術で対処することが次第に困難になってき
た。2. Description of the Related Art Conventionally, soldering has been often used to connect a connection terminal of a semiconductor device and a conductor electrode of a circuit board. Pitch intervals have become smaller and narrower, making it more difficult to deal with with conventional soldering techniques.
そこで最近では、裸の半導体装置を回路基板の導体電極
に直付けして、実装面積の効率的使用を図ろうとする方
法が考案されてきた。Therefore, recently, a method has been devised in which a bare semiconductor device is directly attached to a conductor electrode of a circuit board to efficiently use a mounting area.
なかでも、半導体装置を回路基板上に直接ダイボンディ
ングして、導体電極とＡｕワイヤやＡｌワイヤでワイヤ
ボンディングにより接続をする方法が用いられてきてい
る。In particular, a method has been used in which a semiconductor device is directly die-bonded on a circuit board and the conductor electrode is connected to the Au wire or Al wire by wire bonding.
以下図面を参照しながら、従来のワイヤボンディングに
よる裸の半導体装置の実装法における半導体装置の検査
方法について説明する。A semiconductor device inspection method in a conventional bare semiconductor device mounting method by wire bonding will be described below with reference to the drawings.
第３図は従来のワイヤボンディングによる半導体装置の
実装法における検査方法の概略説明図である。第３図に
おいて、６は回路基板であり、７は導体電極である。８
は半導体装置であり、９はＡｕワイヤである。１０は半
導体装置８の検査用のプローブ針である。FIG. 3 is a schematic explanatory view of an inspection method in a conventional semiconductor device mounting method by wire bonding. In FIG. 3, 6 is a circuit board and 7 is a conductor electrode. 8
Is a semiconductor device, and 9 is an Au wire. Reference numeral 10 is a probe needle for inspecting the semiconductor device 8.
以上のように構成された従来のワイヤボンディングによ
る半導体装置の実装法における検査方法について、以下
その概略を説明する。The outline of the inspection method in the conventional method of mounting a semiconductor device by wire bonding configured as described above will be described below.
まず、回路基板６の所定の位置に導電性接着剤等により
半導体装置８をダイボンディングを行なった後、Ａｕワ
イヤ９によって半導体装置８の電極パッドと回路基板６
の導体電極７をワイヤボンディングを行なうことによっ
て、半導体装置８の回路基板６への実装が実現できる。First, after the semiconductor device 8 is die-bonded at a predetermined position on the circuit board 6 with a conductive adhesive or the like, the electrode pad of the semiconductor device 8 and the circuit board 6 are bonded by the Au wire 9.
By wire-bonding the conductor electrode 7 of the above, the semiconductor device 8 can be mounted on the circuit board 6.
その後、半導体装置８自体の不良や実装不良を検査する
ために、回路基板６の導体電極７上に検査用のプローブ
針１０によってプロービングを行ない、所定の電気的検
査を行なう。Then, in order to inspect the semiconductor device 8 itself for defects and mounting defects, probing is performed on the conductor electrodes 7 of the circuit board 6 with a probe needle 10 for inspection, and a predetermined electrical inspection is performed.
発明が解決しようとする課題 しかしながら上記のような実装法における半導体装置の
検査方法においては、半導体装置８の実装が完了した状
態で検査を行なうため、半導体装置８自体の不良や実装
の不良が検出できても、不良の半導体装置の交換が不可
能であるといった課題を有していた。このことは、近年
見られるようなＨＩＣ等へのマルチチップ実装におい
て、一層深刻な課題となりつつある。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the method of inspecting a semiconductor device in the above-described mounting method, since the inspection is performed in a state where the mounting of the semiconductor device 8 is completed, a defect of the semiconductor device 8 itself or a defect of the mounting is detected Even if it is possible, there is a problem that it is impossible to replace a defective semiconductor device. This is becoming a more serious problem in multi-chip mounting on HIC and the like which has been seen in recent years.
本発明は上記の課題に鑑みてなされたものであり、その
目的とする所は、半導体装置自身の不良や実装の不良の
検出が可能で、不良の半導体装置の交換が容易にできる
半導体装置の検査方法を提出するものである。The present invention has been made in view of the above problems, and an object of the present invention is to detect a defect of a semiconductor device itself or a mounting defect, and to replace a defective semiconductor device easily. The inspection method is submitted.
課題を解決するための手段 本発明は上記の課題を解決するため、回路基板の導体電
極上に半導体装置を導電性接着剤を用いてフェイスダウ
ンボンディングにより実装してなる半導体装置の実装法
において、前記導電性接着剤に溶剤型の導電性接着剤を
用いることにより、仮硬化の状態で半導体装置の電気的
な検査を行なうことを特徴とするものであり、半導体装
置自身の不良や実装の不良の検出が可能で、不良の半導
体装置の交換が容易にできる半導体装置の検査方法を提
供することができる。Means for Solving the Problems The present invention, in order to solve the above problems, in a method for mounting a semiconductor device in which a semiconductor device is mounted on a conductor electrode of a circuit board by face-down bonding using a conductive adhesive, By using a solvent-type conductive adhesive as the conductive adhesive, an electrical inspection of the semiconductor device is performed in a temporarily cured state, and the semiconductor device itself has a defect or a mounting defect. It is possible to provide a method for inspecting a semiconductor device, which can detect a defect and can easily replace a defective semiconductor device.
作用 本発明は上記した方法によって、溶剤型の導電性接着剤
を用いることにより、仮硬化の状態で半導体装置の電気
的な検査を行なうことができ、半導体装置自身の不良や
実装の不良の検出が可能で、不良の半導体装置の交換が
容易にできるため、回路基板に半導体装置を実装した場
合に、歩留り１００％が実現できる。Effect of the Invention According to the present invention, by using the solvent-type conductive adhesive by the method described above, the semiconductor device can be electrically inspected in a temporarily cured state, and the defect of the semiconductor device itself or the mounting defect can be detected. Since the defective semiconductor device can be easily replaced, a yield of 100% can be realized when the semiconductor device is mounted on the circuit board.
実施例 以下、本発明の一実施例の半導体装置の検査方法につい
て、図面を参照しながら説明する。Embodiment Hereinafter, a semiconductor device inspection method according to an embodiment of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の半導体装置の検査方法の概
略説明図であり、第２図は本発明の半導体装置の検査方
法を説明するための実装後の経過時間とその接続抵抗の
関係を示した図である。FIG. 1 is a schematic explanatory diagram of a method for inspecting a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a diagram showing an elapsed time after mounting and its connection resistance for explaining a method for inspecting a semiconductor device according to the present invention. It is the figure which showed the relationship.
第１図において、１は回路基板であり、２は導体電極で
ある。３は半導体装置であり、４は溶剤型の導電性接着
剤である。５は半導体装置３の検査用のプローブ針であ
る。In FIG. 1, 1 is a circuit board and 2 is a conductor electrode. Reference numeral 3 is a semiconductor device, and 4 is a solvent-type conductive adhesive. Reference numeral 5 is a probe needle for inspecting the semiconductor device 3.
以上のように構成された本発明の半導体装置の検査方法
について、以下その概略を説明する。The outline of the semiconductor device inspection method of the present invention configured as described above will be described below.
まず、回路基板１の所定の導体電極２上に半導体装置３
を溶剤型の導電性接着剤４を用いてフェイスダウンボン
ディングにより実装した後、加熱等によって沸点の異な
る２種類の溶剤からなる溶剤型の導電性接着剤４中の低
い沸点の溶剤分を蒸発させる。このとき、第２図に示す
ように時間経過とともに半導体装置３の接続抵抗は、導
電接着剤４中の溶剤分の蒸発度合に従って減少し、経過
時間Ｔ後には電気的な導通が安定する。この後、半導体
装置３自体の不良や実装不良を検査するために、回路基
板１の導体電極２上に検査用のプローブ針５によって、
所定の電気的検査を行ない、半導体装置３自身の不良や
実装の不良の検出が可能となる。First, the semiconductor device 3 is formed on the predetermined conductor electrode 2 of the circuit board 1.
Is mounted by face-down bonding using a solvent-type conductive adhesive 4, and then a low-boiling-point solvent component in the solvent-type conductive adhesive 4 composed of two kinds of solvents having different boiling points is evaporated by heating or the like. . At this time, as shown in FIG. 2, the connection resistance of the semiconductor device 3 decreases with the lapse of time in accordance with the degree of evaporation of the solvent component in the conductive adhesive 4, and after a lapse of the elapsed time T, the electrical conduction becomes stable. After that, in order to inspect the semiconductor device 3 itself for a defect or a mounting defect, a probe needle 5 for inspection is provided on the conductor electrode 2 of the circuit board 1.
Predetermined electrical inspection can be performed to detect defects in the semiconductor device 3 itself or mounting defects.
つまり、この溶剤型の導電性接着剤４が仮硬化の状態で
半導体装置３の電気的な検査を行なうため、半導体装置
３自身の不良や実装の不良が検出された場合には、容易
に不良の半導体装置３を取り外し、交換することができ
る。In other words, since the semiconductor device 3 is electrically inspected while the solvent-type conductive adhesive 4 is temporarily cured, if a defect in the semiconductor device 3 itself or a mounting defect is detected, the semiconductor device 3 is easily defective. The semiconductor device 3 can be removed and replaced.
このようにして、半導体装置３の検査結果が良好となっ
た場合にのみ、溶剤型の導電性接着剤４の本硬化を行な
い、沸点の異なる２種類の溶剤からなる溶剤型の導電性
接着剤４中の残りの高い沸点の溶剤分を蒸発させること
により、回路基板１への半導体装置３の実装がなされ
る。In this way, the solvent-type conductive adhesive 4 is fully cured only when the inspection result of the semiconductor device 3 is good, and the solvent-type conductive adhesive composed of two kinds of solvents having different boiling points is used. The semiconductor device 3 is mounted on the circuit board 1 by evaporating the remaining high boiling point solvent component in 4.
上記した検査方法による半導体装置３の回路基板１への
実装は、溶剤型の導電性接着剤４を用いることにより、
仮硬化の状態で半導体装置の電気的な検査を行なうこと
ができ、不良の半導体装置の交換が容易にできるため、
１００％の歩留りが実現できる。The mounting of the semiconductor device 3 on the circuit board 1 by the above-described inspection method is performed by using the solvent-type conductive adhesive 4.
Since the semiconductor device can be electrically inspected in the temporarily cured state and the defective semiconductor device can be easily replaced,
A yield of 100% can be realized.
なお、本実施例において溶剤型の導電性接着剤４には、
沸点の異なる２種類の溶剤からなるものを用いて、仮硬
化によって低い沸点の溶剤分を蒸発させて検査するとし
たが、１種類の溶剤からなるもので、仮硬化によって溶
剤分の数十％を蒸発させた状態で電気的な導通が得られ
て、半導体装置３の検査を行なうものを用いることも可
能である。In addition, in this embodiment, the solvent-type conductive adhesive 4 includes
I tried to evaporate the solvent with a low boiling point by temporary curing and inspect it by using two kinds of solvents with different boiling points. It is also possible to use a device that can obtain electrical conduction in the evaporated state and inspect the semiconductor device 3.
また、さらに３種類以上の溶剤からなる溶剤型の導電性
接着剤を用いることができるのは言うまでもない。Further, it goes without saying that a solvent-type conductive adhesive composed of three or more kinds of solvents can be used.
発明の効果 以上に説明したように、本発明の半導体装置の検査方法
によれば、回路基板の導体電極上に半導体装置を導電性
接着剤を用いてフェイスダウンボンディングにより実装
してなる半導体装置の実装法において、回路基板と半導
体装置を接続するのに溶剤型の導電性接着剤を用いるこ
とにより、導電性接着剤の仮硬化の状態で半導体装置の
電気的な検査を行なうことができ、半導体装置自身の不
良や実装の不良の検出が可能で、不良の半導体装置の交
換が容易にできるため、回路基板に半導体装置を実装し
た場合に、歩留りが高く、信頼性の高いものが実現で
き、極めて実用上価値の高いものである。Effects of the Invention As described above, according to the semiconductor device inspection method of the present invention, the semiconductor device is mounted on the conductor electrode of the circuit board by face-down bonding using a conductive adhesive. In the mounting method, by using the solvent-type conductive adhesive to connect the circuit board and the semiconductor device, the semiconductor device can be electrically inspected while the conductive adhesive is temporarily hardened. It is possible to detect defects in the device itself and mounting defects, and because it is easy to replace defective semiconductor devices, it is possible to achieve high yield and high reliability when semiconductor devices are mounted on a circuit board. It is of extremely high practical value.
第１図は本発明の一実施例の半導体装置の検査方法の概
略説明図、第２図は本発明の半導体装置の検査方法を説
明するための実装後の経過時間とその接続抵抗の関係
図、第３図は従来のワイヤボンディングによる半導体装
置の実装法における検査方法の概略説明図である。 １，６……回路基板、２，７……導体電極、３，８……
半導体装置、４……溶剤型の導電性接着剤、５，１０…
…プローブ針、９……Ａｕワイヤ。FIG. 1 is a schematic explanatory view of a semiconductor device inspection method according to an embodiment of the present invention, and FIG. 2 is a relational diagram of elapsed time after mounting and connection resistance thereof for explaining a semiconductor device inspection method of the present invention. FIG. 3 is a schematic explanatory view of an inspection method in a conventional semiconductor device mounting method by wire bonding. 1, 6 ... Circuit board, 2, 7 ... Conductor electrodes, 3, 8 ...
Semiconductor device, 4 ... Solvent-type conductive adhesive, 5, 10 ...
... probe needle, 9 ... Au wire.
Claims (2)
性接着剤を用いて実装する方法において、溶剤型の前記
導電性接着剤を用いて、前記半導体装置を前記回路基板
の前記導体電極上に仮硬化の状態で接続する工程と、前
記仮硬化状態で前記半導体装置の電気的な検査を行う工
程と、前記検査の結果が良好な場合は、前記導電性接着
剤を本硬化して、前記半導体装置の実装を完了する工程
と、前記検査の結果が不良の場合は、前記半導体装置を
取り外して交換し、同様の検査工程を経た後、良好なら
ば本硬化して実装を完了する工程とを含むことを特徴と
する半導体装置の実装方法。1. A method of mounting a semiconductor device on a conductor electrode of a circuit board using a conductive adhesive, wherein the semiconductor device is mounted on the conductor electrode of the circuit board using the solvent-type conductive adhesive. The step of connecting in the state of temporary curing above, the step of performing an electrical inspection of the semiconductor device in the state of temporary curing, if the result of the inspection is good, then main curing the conductive adhesive The step of completing the mounting of the semiconductor device, and if the result of the inspection is defective, the semiconductor device is removed and replaced, and after a similar inspection step, if it is good, the main curing is completed to complete the mounting. A method for mounting a semiconductor device, comprising:
沸点の異なる２種類以上の溶剤、導電フィラーおよび樹
脂バインダーからなるものを用いることを特徴とする請
求項１記載の半導体装置の実装方法。2. The method of mounting a semiconductor device according to claim 1, wherein the solvent-type conductive adhesive comprises at least two kinds of solvents having different boiling points, a conductive filler and a resin binder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1153384A JPH0666356B2 (en) | 1989-06-15 | 1989-06-15 | Semiconductor device mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1153384A JPH0666356B2 (en) | 1989-06-15 | 1989-06-15 | Semiconductor device mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0319251A JPH0319251A (en) | 1991-01-28 |
| JPH0666356B2 true JPH0666356B2 (en) | 1994-08-24 |
Family
ID=15561300
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1153384A Expired - Fee Related JPH0666356B2 (en) | 1989-06-15 | 1989-06-15 | Semiconductor device mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0666356B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2564728B2 (en) * | 1991-02-28 | 1996-12-18 | 株式会社半導体エネルギー研究所 | Semiconductor integrated circuit chip mounting method |
| JP3014020B2 (en) * | 1993-12-16 | 2000-02-28 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JP3260253B2 (en) * | 1995-01-06 | 2002-02-25 | 松下電器産業株式会社 | Inspection method for semiconductor device and conductive adhesive for inspection |
| DE69739125D1 (en) | 1996-10-01 | 2009-01-02 | Panasonic Corp | Capillary for wire bonding for the production of bump electrodes |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5961940A (en) * | 1982-09-30 | 1984-04-09 | Sharp Corp | Bonding method of semiconductor chip |
| JPS62231225A (en) * | 1986-03-31 | 1987-10-09 | Stanley Electric Co Ltd | Preparation of liquid crystal display element |
| JPS63289824A (en) * | 1987-05-21 | 1988-11-28 | Fuji Electric Co Ltd | Method of mounting integrated device |
| JPH0282633A (en) * | 1988-09-20 | 1990-03-23 | Seiko Epson Corp | Mounting structure of semiconductor element |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6445136A (en) * | 1987-08-13 | 1989-02-17 | Konishiroku Photo Ind | Method of mounting semiconductor element |
-
1989
- 1989-06-15 JP JP1153384A patent/JPH0666356B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5961940A (en) * | 1982-09-30 | 1984-04-09 | Sharp Corp | Bonding method of semiconductor chip |
| JPS62231225A (en) * | 1986-03-31 | 1987-10-09 | Stanley Electric Co Ltd | Preparation of liquid crystal display element |
| JPS63289824A (en) * | 1987-05-21 | 1988-11-28 | Fuji Electric Co Ltd | Method of mounting integrated device |
| JPH0282633A (en) * | 1988-09-20 | 1990-03-23 | Seiko Epson Corp | Mounting structure of semiconductor element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0319251A (en) | 1991-01-28 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |