JPS61156792A - Manufacture of circuit module - Google Patents
Manufacture of circuit moduleInfo
- Publication number
- JPS61156792A JPS61156792A JP59274647A JP27464784A JPS61156792A JP S61156792 A JPS61156792 A JP S61156792A JP 59274647 A JP59274647 A JP 59274647A JP 27464784 A JP27464784 A JP 27464784A JP S61156792 A JPS61156792 A JP S61156792A
- Authority
- JP
- Japan
- Prior art keywords
- circuit module
- support plate
- resin
- plate
- electronic component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（発明の技術分野〕
本発明は、電子部品を基板に実装した回路モジュールの
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a method for manufacturing a circuit module in which electronic components are mounted on a substrate.
ＩＣその他の電子部品の実装法として従来、銅箔張り樹
脂基板を選択的にエツチングして回路パター゛ンを形成
したプリント配線板、あるいはアルミナ等のセラミック
基板表面に厚膜印刷により回路パターンを形成した厚膜
印刷配線基板上に、半田付けまたは導電性接着剤により
該電子部品を接続する方法が多く用いられている。Conventional methods for mounting ICs and other electronic components include printed wiring boards in which circuit patterns are formed by selectively etching copper foil-covered resin substrates, or circuit patterns are formed by thick film printing on the surface of ceramic substrates such as alumina. A method is often used in which electronic components are connected to a thick film printed wiring board using soldering or a conductive adhesive.
しかしながら、この方法は原理的に、得られた回路モジ
ュールの厚みが基板と部品の厚みを加算した寸法以下に
はなり得す、最近ますます薄型化されつつある電子機器
における回路モジュールの実現法としては不十分となっ
ている。また、この方法では厚膜印刷配線基板の形成工
程と、該基板上への電子部品の実装工程とが全く独立し
た工程であるため、回路モジュール全体としての製造工
程が複雑で時間がかかり、製造コストの低減にも自ずと
限界があるという問題があった。However, in principle, the thickness of the obtained circuit module can be less than the sum of the thickness of the board and the components, so this method is not suitable for realizing circuit modules in electronic devices that are becoming thinner and thinner. is insufficient. In addition, in this method, the process of forming the thick-film printed circuit board and the process of mounting electronic components on the board are completely independent processes, so the manufacturing process for the entire circuit module is complex and time-consuming. There is a problem in that there is a limit to the reduction of costs.
本発明の目的は、電子部品の厚みと同等またはそれに近
い厚みまで薄型化が可能であり、また基板上の導体パタ
ーンの形成と電子部品の接続とを同時に行なうことがで
き、製造工程が簡単で製造に要する時間の短い回路モジ
ュールの製造方法を提供することにある。The purpose of the present invention is to make it possible to reduce the thickness to a thickness equal to or close to that of electronic components, to form a conductor pattern on a board and to connect electronic components at the same time, and to simplify the manufacturing process. It is an object of the present invention to provide a method for manufacturing a circuit module that requires a short manufacturing time.
本発明はこの目的を達成するため、まず電子部品を支持
板上の所定位置に該電子部品の端子形成面を支持板表面
に対向させて配置し、電子部品の周囲に紫外線硬化樹脂
を注型し、該紫外線硬化樹脂上に平板を設置した後、支
持板側から紫外線を照射して紫外線硬化樹脂を硬化させ
る。この時、支持板としては紫外線を透過させる必要か
らガラス板、あるいはポリエチレンテレフタレート樹脂
。In order to achieve this object, the present invention first places an electronic component at a predetermined position on a support plate with the terminal forming surface of the electronic component facing the surface of the support plate, and then casts an ultraviolet curing resin around the electronic component. After a flat plate is placed on the ultraviolet curable resin, ultraviolet rays are irradiated from the support plate side to cure the ultraviolet curable resin. At this time, the supporting plate is a glass plate or polyethylene terephthalate resin because it is necessary to transmit ultraviolet rays.
ポリカーボネート樹脂、塩化ビニール樹脂、ポリエチレ
ン樹脂、四フッ化エチレン・六フフ化プロピレン樹脂、
ポリスチレン樹脂またはポリエチレン樹脂等の透光性を
有する材質のものが使用される。また、支持板は電子部
品を固定するため、粘着性を有することが必要であり、
その目的で、好ましくは次の工程で支持板を剥離するた
めに離型性を兼ね備えた被膜が形成される。この被膜は
例えばシリコーン樹脂をスピンナーコーティングした後
、１２０℃で１５分間加熱硬化させることにより得られ
る。Polycarbonate resin, vinyl chloride resin, polyethylene resin, tetrafluoroethylene/hexafluoropropylene resin,
A light-transmitting material such as polystyrene resin or polyethylene resin is used. In addition, since the support plate fixes the electronic components, it needs to have adhesive properties.
For that purpose, preferably a film having releasability is formed so that the support plate can be peeled off in the next step. This film can be obtained, for example, by coating a silicone resin with a spinner and then heating and curing it at 120° C. for 15 minutes.
次に、支持板を剥離した後、硬化した紫外線硬化樹脂か
らなる基板の支持板に対向していた面上に導体パターン
を形成すると共に、該導体パターンと基板表面に露出し
た電子部品上の端子との接続を行なう。ここで、紫外線
硬化樹脂上に設置する平板としては、該平板を支持板と
共に硬化した樹脂から剥離する場合には、テフロンシー
トをはじめとするフッ素系樹脂シートやテフロン処理を
施して離型性を持たせた樹脂シート、あるいは支持板と
同一の材質上にシリコーン樹脂被膜を設けたものが使用
される。逆に平板を硬化した樹脂から剥離しない場合に
は、平板の材質としては１５０℃〜１８０℃程度の耐熱
性を有するものであればよく、例えばガラスエポキシ板
、８Ｔレジン板、ＰＥＳ樹脂、ＰＥＥＫ樹脂、ポリカー
ボネート樹脂、ポリサルフオン樹脂、ポリフェニレンサ
ルファイド樹脂、ポリフェニレンオキシド樹脂等が使用
される。また、必要によってはセラミック板、金属板等
を用いてもよい。なお、平板は支持板を剥離するとき同
時に剥離してもよいし、回路モジュールの補強の意味で
残してもよい。Next, after peeling off the support plate, a conductor pattern is formed on the surface of the substrate made of cured ultraviolet curable resin that was facing the support plate, and the conductor pattern and terminals on the electronic components exposed on the substrate surface are formed. Connect with. Here, as for the flat plate placed on the ultraviolet curing resin, if the flat plate is to be peeled off from the cured resin together with the support plate, a fluororesin sheet such as a Teflon sheet or Teflon treatment can be applied to improve the mold releasability. A resin sheet with a support plate or a silicone resin coating on the same material as the support plate is used. On the other hand, if the flat plate is not to be peeled off from the cured resin, the material for the flat plate may be any material that has a heat resistance of about 150°C to 180°C, such as glass epoxy board, 8T resin board, PES resin, PEEK resin, etc. , polycarbonate resin, polysulfone resin, polyphenylene sulfide resin, polyphenylene oxide resin, etc. are used. Further, a ceramic plate, a metal plate, etc. may be used as necessary. Note that the flat plate may be removed at the same time as the support plate is removed, or may be left in place for the purpose of reinforcing the circuit module.
導体パターンの形成法としては、電子部品の端子表面と
基板の表面とが同一平面となるために、スクリーン印刷
、オフセット印刷、ディスペンサにより描画する方式等
を使用することが可能である。また、金属薄１１層を形
成し、感光性樹脂を用いて選択エツチングする写真法に
よる導体パターン形成を行なうこともできる。導体パタ
ーンに使用される導体材料としては、エポキシ樹脂やフ
ェノール樹脂等の熱硬化性樹脂をバインダとし、それに
金、銀、銅、ニッケル、タングステン、モリブデン、白
金、アルミニウム、錫等の金属粉、およびこれらを主成
分とする合金または複合粉、あるいはカーボン粉、五酸
化バナジウム粉等の半導体粉を混練してペースト化した
もの等を使用することができる。As a method for forming the conductor pattern, since the terminal surface of the electronic component and the surface of the substrate are on the same plane, screen printing, offset printing, drawing with a dispenser, etc. can be used. It is also possible to form a conductor pattern by a photographic method in which 11 thin metal layers are formed and selectively etched using a photosensitive resin. The conductor material used for the conductor pattern is a thermosetting resin such as epoxy resin or phenol resin as a binder, and metal powder such as gold, silver, copper, nickel, tungsten, molybdenum, platinum, aluminum, tin, etc. An alloy or composite powder containing these as main components, or a paste obtained by kneading semiconductor powder such as carbon powder or vanadium pentoxide powder can be used.
本発明によれば、電子部品が紫外線硬化樹脂からなる基
板中に埋め込まれた形で実装されるため、この基板上に
印刷等により導体パターンを形成すると同時にチップ型
電子部品の端子との接続を行なうことができる。従って
、厚みがほぼ電子部品の厚みと同程度の極めて薄い回路
モジュールを１ｑることができる。また、製造工程も紫
外線硬化樹脂を硬化させて基板形成を行なっていること
と、上述のように導体パターンの形成と電子部品の端子
接続とが同時になされることによって、配線基板の形成
と電子部品の実装を別々に行なう従来法に比較して著し
く簡単となり、短時間で回路モジュールが得られ、それ
により製造コストも大幅に低減される。According to the present invention, since electronic components are embedded and mounted in a substrate made of ultraviolet curing resin, a conductor pattern is formed on this substrate by printing or the like, and at the same time, connections with terminals of chip-type electronic components are made. can be done. Therefore, an extremely thin circuit module whose thickness is approximately the same as the thickness of an electronic component can be made in 1q. In addition, in the manufacturing process, the substrate is formed by curing the ultraviolet curable resin, and as mentioned above, the formation of the conductor pattern and the terminal connection of the electronic components are done simultaneously, so the formation of the wiring board and the electronic component Compared to the conventional method in which mounting is performed separately, the circuit module can be obtained in a short time, and the manufacturing cost is also significantly reduced.
第１図に本発明の一実施例に係る回路モジュールの製造
工程を示す。まず、厚さ３＃ｌｌＩ程度のガラス板上に
シリコーン樹脂（東芝シリコン社製Ｔ Ｓ Ｅ ３０５
１）をスピンナーコーティングし、厚さ１０μｍの被膜
を得た後、これを１２０℃で１５分間加熱することによ
りゲル化させて表面に粘着性と離型性を付与し、支持板
１とする。そして、第１図（ａ）（ｂ）に示すように、
こうして得られた支持板１上の所定位置に電子部品とし
て例えばＩＣ２，チップダイオード３およびチップ抵抗
４を配置する。これらの部品の配置には、チップマウン
タを用いた。なお、第１−図（ａ）は平面図、（ｂは（
ａ）図のＡ−Ａ線に沿う断面図である。FIG. 1 shows the manufacturing process of a circuit module according to an embodiment of the present invention. First, silicone resin (TSE 305 manufactured by Toshiba Silicon Co., Ltd.
1) was coated with a spinner to obtain a film with a thickness of 10 μm, which was then heated at 120° C. for 15 minutes to gel, thereby imparting adhesiveness and releasability to the surface, thereby forming support plate 1. Then, as shown in FIGS. 1(a) and (b),
Electronic components such as an IC 2, a chip diode 3, and a chip resistor 4 are placed at predetermined positions on the support plate 1 thus obtained. A chip mounter was used to place these parts. Note that Figure 1 (a) is a plan view, (b is (
a) It is a sectional view taken along the line A-A in the figure.
次に、第１図（Ｃ）に示すように支持板１の周囲に厚さ
２ｐｍ程度のテフロンよりなるスペーサ５を配置し、そ
の状態で支持ｌ１ｉｉ１上の各チップ型電子部品２〜４
の周囲に紫外線硬化樹脂６を注型し、さらにその上を例
えば厚さ５ ｍｒｔｒ程度のテフロンからなる平板７で
覆う。そして、支持阪１側から紫外線を照射し、紫外線
硬化樹脂６を硬化させる。Next, as shown in FIG. 1(C), a spacer 5 made of Teflon with a thickness of about 2 pm is arranged around the support plate 1, and in this state, each chip type electronic component 2 to 4 on the support l1ii1 is
An ultraviolet curing resin 6 is cast around the wafer, and a flat plate 7 made of Teflon and having a thickness of about 5 mrtr is further covered thereon. Then, ultraviolet rays are irradiated from the support plate 1 side to cure the ultraviolet curing resin 6.
この硬化した紫外線硬化樹脂が回路モジュールの基板と
なる。This cured ultraviolet curable resin becomes the substrate of the circuit module.
次に、第１図（ｄ）に示すように支持板１と平板７およ
びスペーサ５を剥離することにより、硬化した紫外線硬
化樹脂からなる基板８中に電子部品２〜４が埋め込まれ
たものが得られる。この状態では、各電子部品２〜４の
端子２ａ〜４ａは基板８の表面からｎ出している。Next, as shown in FIG. 1(d), by peeling off the support plate 1, the flat plate 7, and the spacer 5, a substrate 8 made of a cured ultraviolet curable resin with the electronic components 2 to 4 embedded therein is obtained. can get. In this state, the terminals 2a to 4a of each of the electronic components 2 to 4 protrude from the surface of the substrate 8.
次に、第１図（ｅ）に示すように基板８上に例えば銀ペ
ーストをスクリーン印刷することにより所望の導体パタ
ーン９を形成すると共に、これら導体パターン９とチッ
プ型電子部品２〜４の端子２ａ〜４ａとの接続をとる。Next, as shown in FIG. 1(e), desired conductor patterns 9 are formed on the substrate 8 by screen printing, for example, silver paste, and the terminals of these conductor patterns 9 and the chip-type electronic components 2 to 4 are formed. Make connections with 2a to 4a.
この後、１５０℃で１時間加熱することにより銀ペース
トを硬化させ、回路モジュールを完成させた。Thereafter, the silver paste was cured by heating at 150° C. for 1 hour to complete a circuit module.
こうして得られた回路モジュールに対し動作試験を行な
ったところ、良好な動作が得られた。When the circuit module thus obtained was subjected to an operation test, good operation was obtained.
第２図は本発明の他の実施例に係る回路モジュールを示
すもので、紫外線硬化樹脂の上に設置する平板１０とし
て例えば厚さ２ｍのガラスエポキシ板を用い、これを前
記実施例のように剥離せずに基板８に密着させたまま残
し、回路モジュールの補強板としたものである。FIG. 2 shows a circuit module according to another embodiment of the present invention, in which a glass epoxy plate with a thickness of 2 m, for example, is used as the flat plate 10 installed on the ultraviolet curing resin, and this is used as in the previous embodiment. It is left in close contact with the substrate 8 without being peeled off, and is used as a reinforcing plate for the circuit module.
本発明はその他、要旨を逸脱しない範囲で種々変形実施
が可能である。The present invention can be modified in various other ways without departing from the scope of the invention.
第１図は本発明の一実施例に係る回路モジュールの製造
工程を説明するための図で、（ａ）は平面図、（ｂ）〜
（ｅ）は断面図、第２図は本発明の他の実施例に係る回
路モジュールの最終工程における断面図である。
１・・・支持板、２〜４・・・電子部品、２ａ〜４ａ・
・・端子、５・・・スペーサ、６・・・紫外線硬化樹脂
、７・・・平板、８・・・硬化した紫外線硬化樹脂から
なる基板、９・・・導体パターン、１０・・・補強板と
して残した平板。
出願人代理人 弁理士 鈴江武彦
１゛へ １ 図
第１図FIG. 1 is a diagram for explaining the manufacturing process of a circuit module according to an embodiment of the present invention, in which (a) is a plan view, and (b) -
(e) is a cross-sectional view, and FIG. 2 is a cross-sectional view in the final step of a circuit module according to another embodiment of the present invention. 1...Support plate, 2-4...Electronic component, 2a-4a・
...terminal, 5...spacer, 6...ultraviolet curable resin, 7...flat plate, 8...substrate made of cured ultraviolet curable resin, 9...conductor pattern, 10...reinforcement plate A flat plate left as a. To Applicant's Representative Patent Attorney Takehiko Suzue 1 Figure 1
Claims (3)
する方法において、チップ型電子部品を粘着性を有しか
つ透光性を有する支持板上の所定位置に該電子部品の端
子形成面を支持板表面に対向させて配置し、前記電子部
品の周囲に紫外線硬化樹脂を注型し、該紫外線硬化樹脂
上に平板を設置した後、前記支持板側から紫外線を照射
して前記紫外線硬化樹脂を硬化させ、次いで前記支持板
を剥離した後、硬化した前記紫外線硬化樹脂からなる基
板の前記支持板に対向していた面上に導体パターンを形
成すると共に、該導体パターンと前記電子部品上の端子
との接続を行なうことを特徴とする回路モジュールの製
造方法。(1) In a method for manufacturing a circuit module in which an electronic component is mounted on a substrate, a chip-type electronic component is supported with the terminal forming surface of the electronic component at a predetermined position on a support plate that has adhesiveness and translucency. Placed facing the surface of the plate, cast an ultraviolet curable resin around the electronic component, set a flat plate on the ultraviolet curable resin, and then irradiate ultraviolet rays from the supporting plate side to cure the ultraviolet curable resin. After curing and then peeling off the support plate, a conductor pattern is formed on the surface of the substrate made of the cured ultraviolet curable resin that was facing the support plate, and the conductor pattern and the terminals on the electronic component are formed. 1. A method of manufacturing a circuit module, the method comprising making a connection with a circuit module.
することを特徴とする特許請求の範囲第１項記載の回路
モジュールの製造方法。(2) The method for manufacturing a circuit module according to claim 1, wherein when the support plate is peeled off, the flat plate is also peeled off at the same time.
ールの補強板として残すことを特徴とする特許請求の範
囲第１項記載の回路モジュールの製造方法。(3) The method for manufacturing a circuit module according to claim 1, wherein when the support plate is peeled off, the flat plate is left as a reinforcing plate of the circuit module.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59274647A JPS61156792A (en) | 1984-12-28 | 1984-12-28 | Manufacture of circuit module |
| US06/765,800 US4635356A (en) | 1984-12-28 | 1985-08-15 | Method of manufacturing a circuit module |
| DE8585110511T DE3585604D1 (en) | 1984-12-28 | 1985-08-21 | METHOD FOR PRODUCING A MODULAR CIRCUIT. |
| EP85110511A EP0187195B1 (en) | 1984-12-28 | 1985-08-21 | Method of manufacturing a circuit module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59274647A JPS61156792A (en) | 1984-12-28 | 1984-12-28 | Manufacture of circuit module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61156792A true JPS61156792A (en) | 1986-07-16 |
Family
ID=17544614
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59274647A Pending JPS61156792A (en) | 1984-12-28 | 1984-12-28 | Manufacture of circuit module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61156792A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003078069A (en) * | 2001-09-05 | 2003-03-14 | Sony Corp | Pseudo wafer for multichip module production and production method therefor |
| JP2016058464A (en) * | 2014-09-08 | 2016-04-21 | 日本電気株式会社 | Module component and manufacturing method of the same |
| JP2018067687A (en) * | 2016-10-21 | 2018-04-26 | 株式会社村田製作所 | Composite type electronic component and method of manufacturing the same |
| WO2018092408A1 (en) * | 2016-11-21 | 2018-05-24 | オムロン株式会社 | Electronic device and method for producing same |
| WO2018168734A1 (en) * | 2017-03-13 | 2018-09-20 | 株式会社村田製作所 | Resin structure with built-in electronic component and method for producing same |
-
1984
- 1984-12-28 JP JP59274647A patent/JPS61156792A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003078069A (en) * | 2001-09-05 | 2003-03-14 | Sony Corp | Pseudo wafer for multichip module production and production method therefor |
| JP4724988B2 (en) * | 2001-09-05 | 2011-07-13 | ソニー株式会社 | Method of manufacturing a pseudo wafer for manufacturing a multichip module |
| JP2016058464A (en) * | 2014-09-08 | 2016-04-21 | 日本電気株式会社 | Module component and manufacturing method of the same |
| JP2018067687A (en) * | 2016-10-21 | 2018-04-26 | 株式会社村田製作所 | Composite type electronic component and method of manufacturing the same |
| WO2018092408A1 (en) * | 2016-11-21 | 2018-05-24 | オムロン株式会社 | Electronic device and method for producing same |
| JP2018085384A (en) * | 2016-11-21 | 2018-05-31 | オムロン株式会社 | Electronic device and manufacturing method thereof |
| WO2018168734A1 (en) * | 2017-03-13 | 2018-09-20 | 株式会社村田製作所 | Resin structure with built-in electronic component and method for producing same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0187195B1 (en) | Method of manufacturing a circuit module | |
| JP3094481B2 (en) | Electronic circuit device and manufacturing method thereof | |
| JPS6129195A (en) | Method of producing multilayer circuit board | |
| JPH03136290A (en) | Resin circuit board and manufacture thereof | |
| JPH07211995A (en) | Method and apparatus for forming impedance-controlled flexible circuit | |
| JPS61188957A (en) | Manufacture of circuit module | |
| JPS61156792A (en) | Manufacture of circuit module | |
| US3449828A (en) | Method for producing circuit module | |
| JPH0521522A (en) | Semiconductor chip mounting method | |
| JPH0423391A (en) | Manufacture of multilayer wiring circuit board | |
| JPS58134497A (en) | Method of producing printed circuit board and printed circuit board | |
| KR20210053596A (en) | Recessed stretchable electrode and manufacturing method | |
| JPH02280334A (en) | Semiconductor device and manufacture thereof | |
| JPH06152104A (en) | Manufacture of ceramic circuit board | |
| JPS622592A (en) | Manufacture of smoothing type circuit module | |
| US3808679A (en) | Terminal leads for integrated circuit package and method for producing a frame of said leads | |
| JPS62285432A (en) | Micro formation of electric contact material | |
| JP2532720B2 (en) | Circuit board and semiconductor device | |
| JPH04242939A (en) | Packaging structure of semiconductor device and its manufacture | |
| JPH02260592A (en) | Circuit board | |
| JPS62291086A (en) | Wiring circuit board | |
| JPH02154496A (en) | Manufacture of circuit board | |
| JPH0685434A (en) | Manufacturing method of ceramic circuit board | |
| JPH0212931A (en) | Manufacture of circuit device | |
| JPH0923054A (en) | Manufacture of printed wiring board |