JPH05275490A - Mounting method of flip chip - Google Patents

Mounting method of flip chip

Info

Publication number
JPH05275490A
JPH05275490A JP6831992A JP6831992A JPH05275490A JP H05275490 A JPH05275490 A JP H05275490A JP 6831992 A JP6831992 A JP 6831992A JP 6831992 A JP6831992 A JP 6831992A JP H05275490 A JPH05275490 A JP H05275490A
Authority
JP
Japan
Prior art keywords
printed wiring
wiring board
flip chip
curing
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6831992A
Other languages
Japanese (ja)
Other versions
JP2774409B2 (en
Inventor
Eiichi Tsunashima
瑛一 綱島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP6831992A priority Critical patent/JP2774409B2/en
Publication of JPH05275490A publication Critical patent/JPH05275490A/en
Application granted granted Critical
Publication of JP2774409B2 publication Critical patent/JP2774409B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve the arrangement precision of flip chips, increase bonding strength to a printed wiping board, enhance electric characteristics, and promote the use efficiency of a printed wiring board. CONSTITUTION:A prepreg sheet 3 wherein aramid short fiber paper is used as reinforcement, and aromatic amine is compounded as adduct harder in impregnated resin is heated at 105 deg.C for 10 minutes, and holes 4 are formed by an ordinary drill method to obtain a board 5 provided with holes. The board 5 is made to abut against the printed wiring board 6 and pressed and heated at 160 deg.C for 30 minutes to be bonded to the board 6. In this case, the surface of the printed wiring board 6 is subjected to inverse sputtering. Holes 6 is filled with silver powder-epoxy resin based conductive paint 9, bumps 2 are made to abut against conductive paint 9. The paint 9 is turned into a B-stage by primary curing at 75 deg.C for 10 minutes, and electric conducting resistance is decreased to inspect the function of a flip chip 1. Acceptable articles are subjected to secondary curing.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、電子機器用プリント
配線板にフリップチップを搭載するフリップチップの搭
載方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip chip mounting method for mounting a flip chip on a printed wiring board for electronic equipment.

【0002】[0002]

【従来の技術】フリップチップ型の部品を搭載するサブ
ストレイトとして、ガラス布/エポキシ板,アルミナ磁
気板,ポリイミドフィルム板などが代表的であったが、
フリップチップ本体とサブストレイトとの間に空間がで
き、熱伝導性,接着面積などの特性が通常のSOP,Q
FP等のパッケージより悪くなる。
2. Description of the Related Art A glass cloth / epoxy plate, an alumina magnetic plate, a polyimide film plate, etc. have been typical as a substrate for mounting flip chip type parts.
There is a space between the flip chip body and the substrate, and the characteristics such as thermal conductivity and adhesive area are normal SOP and Q.
It is worse than packages such as FP.

【0003】樹脂封じ内に空気がトラップされ、温度上
昇時に膨張し、接合バンプを浮き上がらせる問題があっ
た。その対策として、紫外線硬化性としたエポキシアク
リレイト,エポキシ/ポリイミド,ポリイミド等の樹脂
をプリント配線板に塗布し、選択的に現像し、フリップ
チップのバンプ配置用の孔あけを行う例があった。
There has been a problem that air is trapped in the resin seal and expands when the temperature rises, causing the bonding bump to float. As a countermeasure, there is an example in which a resin such as an epoxy acrylate, an epoxy / polyimide, or a polyimide, which is UV-curable, is applied to a printed wiring board, selectively developed, and holes for flip chip bump placement are drilled. ..

【0004】しかしながら、これらの紫外線硬化性の樹
脂をプリント配線板の外層に用いた場合、硬化時の収縮
率が大きく、かつ、方向性が無秩序であるため、孔の位
置についての制御が困難で、バンプの位置と一致しなく
なる欠点があった。この理由は、これらの紫外線硬化性
樹脂がガラスラインフォースメントを有しているプリン
ト配線板からの反射光を受けることにある。また、紫外
線の透過率に影響して硬化が一様でなく、特にプリント
配線板の外面における境界の接合性の低下に直結する欠
点があった。
However, when these UV-curable resins are used for the outer layer of the printed wiring board, the shrinkage factor at the time of curing is large and the directionality is disordered, so that it is difficult to control the position of the holes. However, there was a defect that the position of the bump did not match. The reason for this is that these ultraviolet curable resins receive the reflected light from the printed wiring board having the glass line force. Further, there is a defect that the curing is not uniform due to the influence of the transmittance of ultraviolet rays, and in particular, the bonding property of the boundary on the outer surface of the printed wiring board is directly deteriorated.

【0005】また、はんだ耐熱性も低く、リフローソル
ダリングの加熱により軟化したり、洗浄剤、例えばME
K(メチルエチルケトン),ジメチルホルムアルデヒド
等に溶解する欠点があった。また、温度や湿度による伸
縮率が大きく、厚さ方向の安定性は、表面方向と同様に
よくない欠点もあった。
Further, the solder heat resistance is low, and the solder is softened by the heating of the reflow soldering, or the cleaning agent such as ME is used.
It has a drawback that it is soluble in K (methyl ethyl ketone), dimethyl formaldehyde and the like. Further, there is a drawback that the expansion and contraction rate due to temperature and humidity is large and the stability in the thickness direction is not as good as in the surface direction.

【0006】電気特性的にも不安定で、特にマイグレー
ションについてその程度が大きい欠点があった。また、
価格的にも本体のプリント配線板と比べて10〜100
倍程度の高価なものであった。フリップチップ脚部の電
気的接続用に導電性接着剤を用いることもダイボンディ
ングの実績から考えられるが、従来のダイシアンダイア
ミド硬化剤を配合したエポキシ樹脂は、マイグレーショ
ンの加速性があり、さらにAステージからCステージへ
の硬化が速やかでBステージに保留することが困難であ
るため、フリップチップの取替,電気的検査に不便であ
った。
The electrical characteristics are unstable, and there is a drawback that the degree of migration is large. Also,
10-100 compared to the printed wiring board of the main body in terms of price
It was about twice as expensive. It is possible to use a conductive adhesive for electrical connection of the flip chip legs from the past of die bonding, but the epoxy resin containing the conventional Dicyan diamide curing agent has a migration accelerating property. Since the curing from the A stage to the C stage is rapid and it is difficult to hold it in the B stage, it is inconvenient for the flip chip replacement and the electrical inspection.

【0007】[0007]

【発明が解決しようとする課題】従来、フリップチップ
のバンプの当接位置固定のため、アクリルまたはアクリ
ルとポリイミド,ポリイミド樹脂モノマーにフォトイニ
シエータを添加して、光感光性樹脂としプリント配線面
に形成し選択感光により光未照射部分を溶解して、プリ
ント配線板のコンタクト導体部分を底とする孔を形成し
ていた。この方法には、下記に示す問題点がある。
Conventionally, in order to fix the contact position of the bumps of the flip chip, a photoinitiator is added to acrylic, acrylic and polyimide, or a polyimide resin monomer to form a photosensitive resin on the printed wiring surface. Then, the non-irradiated portion was melted by selective exposure to form a hole having the contact conductor portion of the printed wiring board as the bottom. This method has the following problems.

【0008】 光感光性樹脂で形成したパターン孔の
位置精度が不安定である。 導体との接触によるマイグレーションが起こり、し
かもフォトイニシエータ添加による加速性がある。 光感光性樹脂層の厚さを、通常のコーティングの厚
さの15μmを超えて、50〜200μmにする必要が
あるが、プリント配線板との境界部において、硬化度が
不足する傾向がある。
The positional accuracy of the pattern hole formed of the photosensitive resin is unstable. Migration occurs due to contact with the conductor, and there is acceleration due to the addition of a photoinitiator. The thickness of the photosensitive resin layer needs to exceed the usual coating thickness of 15 μm to 50 to 200 μm, but the degree of curing tends to be insufficient at the boundary with the printed wiring board.

【0009】 光感光性樹脂を溶解し穴を形成する際
に、底に位置するコンタクト部分の表面を非オーム性接
触化するのでフリップチップ部品の電気的接続を阻害す
る。 光感光性樹脂層の厚さ方向に対する温度および湿度
に対する伸縮性が、プリント配線板にくらべて高く、そ
のためバンプの接合部が浮き上がり接合部が離れ易い。
When the photosensitive resin is melted to form the hole, the surface of the contact portion located at the bottom is made into a non-ohmic contact, which hinders electrical connection of the flip chip component. The photo-sensitive resin layer has higher elasticity in the thickness direction with respect to temperature and humidity than that of a printed wiring board, so that the bump bonding portion rises and the bonding portion easily separates.

【0010】 バンプ接合部の接合補助手段として銀
ペイントを用いた公知例がU.S.P.5,014,1
11(May 7,1991)に見られるが、これは、
フリップチップ部品のバンプと、前記孔の底部導体との
接触の離脱をつなぐためであり、銀ペイントの永久硬化
後の湿度による伸縮値が大きすぎること、銀のマイグレ
ーションに対して、何等の対策が行われていない。
A known example using silver paint as a bonding assisting means for a bump bonding portion is described in US Pat. S. P. 5,014,1
11 (May 7, 1991), this is
This is to connect the contact between the bump of the flip-chip component and the bottom conductor of the hole, and to prevent excessive expansion and contraction due to humidity after permanent curing of the silver paint, and to prevent silver migration. Not done.

【0011】 フリップチップの実装検査と検査後の
取替が不能に近く、光硬化性樹脂層を形成したプリント
配線板をフリップチップとともに廃棄することになる。 この発明の目的は、フリップチップの配置精度を向上さ
せるとともにプリント配線板への接合強度を向上させ、
電気特性の向上をはかり、さらにプリント配線板の使用
効率を高めることのできるフリップチップの搭載方法を
提供することである。
Mounting inspection of the flip chip and replacement after the inspection are almost impossible, and the printed wiring board having the photocurable resin layer formed thereon is discarded together with the flip chip. An object of the present invention is to improve the placement accuracy of a flip chip and the bonding strength to a printed wiring board,
It is an object of the present invention to provide a flip chip mounting method capable of improving electric characteristics and further improving the use efficiency of a printed wiring board.

【0012】[0012]

【課題を解決するための手段】この発明のフリップチッ
プの搭載方法は、アーラミド短繊維紙をラインフォース
メントとし、アロマティックアミンをアダクト性硬化剤
として配合したエポキシ系樹脂を含浸樹脂とするプリプ
レグシートを加熱してリジッド性を付与した後、フリッ
プチップのバンプ搭載位置に孔を開けて孔あき基板を形
成する工程と、プリント配線板の表面に逆スパッタリン
グを行い、孔あき基板をプリント配線板に圧接しながら
BステージからCステージに加熱硬化して孔あき基板を
プリント配線板に接着する工程と、温度および湿度に対
して孔あき基板の厚さ方向の伸縮率と同程度の厚さ方向
の伸縮率を有し、樹脂バインダとしてアロマティックア
ミンをアダクトしたエポキシ系の樹脂からなるAステー
ジの導電性ペイントを、孔あき基板の孔に注入し、フリ
ップチップのバンプを孔に挿入する工程と、導電性ペイ
ントをBステージに加熱硬化して接触抵抗値をプリント
配線板の導体のレベルに下げる第1次硬化工程と、導電
性ペイントをCステージに加熱硬化する第2次硬化工程
とを含むことを特徴とする。
A flip chip mounting method of the present invention is a prepreg sheet in which an aramide short fiber paper is used as a line force and an epoxy resin mixed with an aromatic amine as an adduct curing agent is used as an impregnating resin. After applying the rigid property by heating, form a hole in the flip chip bump mounting position to form a perforated substrate, and perform reverse sputtering on the surface of the printed wiring board to turn the perforated substrate into a printed wiring board. The process of heat-curing from the B stage to the C stage while pressure bonding and adhering the perforated substrate to the printed wiring board, and the temperature direction and humidity in A-stage conductive pane made of epoxy resin that has an expansion / contraction ratio and has an aromatic amine adduct as the resin binder To the holes of the perforated substrate and inserting the bumps of the flip chip into the holes, and the conductive paint is heat-cured on the B stage to lower the contact resistance value to the level of the conductor of the printed wiring board. It is characterized by including a curing step and a secondary curing step of heating and curing the conductive paint on the C stage.

【0013】[0013]

【作用】この発明の構成によれば、アーラミド短繊維紙
をラインフォースメントとし、アロマティックアミンを
アダクト性硬化剤として配合したエポキシ系樹脂を含浸
樹脂とするプリプレグシートを加熱してリジッド性を付
与した後、孔を開けて形成した孔あき基板は、温度およ
び湿度による寸法変化が少なく、孔の位置精度が安定
し、フリップチップの配置精度の向上をはかることがで
きる。
According to the constitution of the present invention, a prepreg sheet containing aramide short fiber paper as a line force and an epoxy resin mixed with an aromatic amine as an adduct curing agent as an impregnating resin is heated to impart rigidity. After that, the perforated substrate formed by forming the holes has little dimensional change due to temperature and humidity, the positional accuracy of the holes is stable, and the accuracy of arranging the flip chips can be improved.

【0014】また、プリント配線板の表面に逆スパッタ
リングを行うことにより、孔あき基板とプリント配線板
との境界面の接合強度が向上し、フリップチップのバン
プとプリント配線板の導体との接合強度の向上がはかれ
る。また、温度および湿度に対して孔あき基板の厚さ方
向の伸縮率と同程度の厚さ方向の伸縮率を有し、樹脂バ
インダとしてアロマティックアミンをアダクトしたエポ
キシ系の樹脂からなる導電性ペイントを、フリップチッ
プのバンプとプリント配線板の導体との接合部に用いる
ことにより、接合強度が増大するとともに、マイグレー
ションなどの電気特性の向上をはかることができる。
Further, by performing reverse sputtering on the surface of the printed wiring board, the bonding strength at the interface between the perforated substrate and the printed wiring board is improved, and the bonding strength between the bumps of the flip chip and the conductors of the printed wiring board is improved. Can be improved. Further, a conductive paint made of an epoxy-based resin that has an expansion / contraction ratio in the thickness direction similar to the expansion / contraction ratio in the thickness direction of a perforated substrate with respect to temperature and humidity and that has an aromatic amine adduct as a resin binder. Is used for the joint between the bump of the flip chip and the conductor of the printed wiring board, the joint strength can be increased and the electrical characteristics such as migration can be improved.

【0015】さらに、上記導電性ペイントは第1次硬化
工程におけるBステージを維持することができ、この状
態でフリップチップの機能検査を行い、不良チップを良
品チップに取り替えたのち、第2次硬化工程を行うこと
により、プリント配線板の使用効率を高めることができ
る。
Furthermore, the conductive paint can maintain the B stage in the primary curing step, and in this state, the functional inspection of the flip chip is performed, and the defective chip is replaced with a good chip, and then the secondary curing is performed. By performing the process, the use efficiency of the printed wiring board can be improved.

【0016】[0016]

【実施例】この発明の一実施例を図面に基づいて説明す
る。図1はこの発明の一実施例のフリップチップの搭載
方法を示す工程断面図である。まず、図1(a) に示すよ
うに、15mm×15mmサイズの半導体フリップチッ
プ1のバンプ(脚)2の長さにしたがって厚さを選んだ
厚さ約0.2mmのプリプレグシート3を用意する。フ
リップチップ1のバンプ2のピッチは125μmであ
る。プリプレグシート3は、ラインフォースメント(骨
材,繊維)として、マイナスの温度膨張係数をもつアー
ラミド短繊維紙を用い、含浸樹脂として、アロマティッ
クアミンをアダクト性硬化剤として50重量パーセント
配合し、さらに外部から侵入するCl- (塩素イオン)
のトラップ剤として、酸化亜鉛の粉末を微量添加したエ
ポキシ樹脂(以下「アロマエポキシ」という)を用いて
いる。そして、アロマエポキシを55重量パーセントと
してアーラミド短繊維紙に含浸したBステージのプリプ
レグシート3とする。このプリプレグシート3は、10
5℃,10分の第1次加熱により、あとの孔加工に耐え
るリジッド性を具備する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a process sectional view showing a flip chip mounting method according to an embodiment of the present invention. First, as shown in FIG. 1A, a prepreg sheet 3 having a thickness of about 0.2 mm is prepared, the thickness of which is selected according to the length of the bump (leg) 2 of the semiconductor flip chip 1 of 15 mm × 15 mm size. .. The pitch of the bumps 2 of the flip chip 1 is 125 μm. The prepreg sheet 3 uses aramide short fiber paper having a negative temperature expansion coefficient as a line force (aggregate, fiber), and contains 50% by weight of an aromatic amine as an impregnating resin as an impregnating resin. Cl entering from the outside - (chlorine ions)
As a trapping agent, a small amount of zinc oxide powder added epoxy resin (hereinafter referred to as "aromatic epoxy") is used. Then, the B-stage prepreg sheet 3 is obtained by impregnating aramide short fiber paper with 55% by weight of aromatic epoxy. This prepreg sheet 3 has 10
By the first heating at 5 ° C. for 10 minutes, it has the rigid property to withstand the later hole processing.

【0017】つぎに、図1(b) に示すように、プリプレ
グシート3に通常のドリル法により直径約0.15mm
のバンプ受入れ用の孔4を形成し、孔あき基板5とす
る。ここでフリップチップの装着予定部分をチップ本体
1′,脚部2′として示す。なお、孔4は、パンチ,レ
ーザ等により形成してもよい。つぎに、図1(c) に示す
ように、例えば厚さ1.5mmのポリイミドガラスやエ
ポキシガラスなどの表面に銅箔または銅めっきにより導
体7を形成したプリント配線板6に、孔あき基板5を当
接して、加圧(10kg/cm2 )下、160℃,30
分の第2次加熱することにより、図1(d) に示すよう
に、孔あき基板5をプリント配線板6へ接着し、孔4は
有底の穴8となる。
Next, as shown in FIG. 1 (b), the prepreg sheet 3 is made to have a diameter of about 0.15 mm by an ordinary drilling method.
The holes 4 for receiving the bumps are formed as the perforated substrate 5. Here, the portion where the flip chip is to be mounted is shown as a chip body 1'and legs 2 '. The holes 4 may be formed by punching, laser, or the like. Next, as shown in FIG. 1 (c), a perforated substrate 5 is formed on a printed wiring board 6 having a conductor 7 formed by copper foil or copper plating on the surface of, for example, a polyimide glass or epoxy glass having a thickness of 1.5 mm. Under pressure (10 kg / cm 2 ) at 160 ° C. for 30
By second heating for a minute, the perforated substrate 5 is bonded to the printed wiring board 6 as shown in FIG. 1 (d), and the holes 4 become the bottomed holes 8.

【0018】なお、Bステージの樹脂硬化レベルにある
孔あき基板5をプリント配線板6に接着するに際して、
Cステージの樹脂硬化レベルにあるプリント配線板6の
表面の導体7および絶縁面に対して、逆スパッタリング
を行う。この逆スパッタリングにより、硬化工程中に、
エポキシ樹脂の硬化面が清浄化されミクロポーラスな表
面を得て、孔あき基板6の含浸樹脂をBステージからC
ステージの硬化レベルに加熱硬化する際の被接着を高め
る。逆スパッタリングは、25cm×25cmの大きさ
に対して、高周波パワー1kW,5分、窒素ガス導入前
の真空度6.0×10-7Torr、窒素ガス導入後の真
空度4.6×10-3Torrとして行う。接着温度は、
170℃,30分で、保持圧力は第2次加熱と同じ20
kg/mm2 である。
When adhering the perforated substrate 5 at the resin curing level of the B stage to the printed wiring board 6,
Reverse sputtering is performed on the conductor 7 and the insulating surface on the surface of the printed wiring board 6 at the resin curing level of the C stage. By this reverse sputtering, during the curing process,
The cured surface of the epoxy resin is cleaned to obtain a microporous surface, and the impregnated resin of the perforated substrate 6 is transferred from the B stage to the C stage.
Enhances adherence when heat curing to stage cure level. The reverse sputtering is performed with a high frequency power of 1 kW for 5 minutes, a vacuum degree before introducing nitrogen gas of 6.0 × 10 −7 Torr, and a vacuum degree after introducing nitrogen gas of 4.6 × 10 with respect to a size of 25 cm × 25 cm. Perform as 3 Torr. The bonding temperature is
At 170 ° C for 30 minutes, the holding pressure is the same as the second heating, 20
It is kg / mm 2 .

【0019】つぎに、図1(d) に示すように、導電性ペ
イント9を有底の穴8に満たし、フリップチップ1のバ
ンプ2を導電性ペイント9に当接する。このとき、物理
的には導電性ペイント液に浮いているような状態にあ
る。導電性ペイント9として、銀粉−エポキシ樹脂系の
ものを用い、さらにエポキシ樹脂系としてアロマエポキ
シ系を用いて、75℃,10分の第1次硬化により、導
電性ペイント9をBステージ(半溶融状態)とし、導通
抵抗を10〜100ミリオームに低下させる。この状態
で、フリップチップ1のプリント配線板6への実装状態
の機能動作特性の測定接続を可能にする。
Next, as shown in FIG. 1 (d), the conductive paint 9 is filled in the bottomed hole 8 and the bump 2 of the flip chip 1 is brought into contact with the conductive paint 9. At this time, it is physically floating in the conductive paint liquid. The conductive paint 9 is a silver powder-epoxy resin type, and the epoxy resin type is an aroma epoxy type, and the conductive paint 9 is B-staged (semi-melted) by primary curing at 75 ° C. for 10 minutes. State), and the conduction resistance is reduced to 10 to 100 milliohms. In this state, it is possible to measure and connect the functional operation characteristics of the flip chip 1 to the printed wiring board 6 in the mounted state.

【0020】良品と判定した場合には、プリント配線板
6への固定接続を計るため、125℃,10分の炉に、
フリップチップ1を搭載したプリント配線板6を入れ、
導電性ペイント9をCステージの第2次硬化し、導通抵
抗を10ミリオーム以下1ミリオームまでとする。一
方、不良品と判定した場合には、フリップチップ1を抜
去することは容易な状態にあり、新たなチップと取り替
える。この際、導電性ペイントを若干量追加して、第1
次硬化を行い、良品と判定されると、第2次硬化を行
う。
When it is judged as a non-defective product, a fixed connection to the printed wiring board 6 is measured, and the furnace is put at 125 ° C. for 10 minutes.
Insert the printed wiring board 6 with the flip chip 1 mounted,
The conductive paint 9 is secondarily cured at the C stage so that the conduction resistance is 10 milliohms or less and up to 1 milliohm. On the other hand, when it is determined that the product is defective, it is easy to remove the flip chip 1, and the flip chip 1 is replaced with a new chip. At this time, add a small amount of conductive paint to
Secondary curing is performed, and when it is determined that the product is non-defective, secondary curing is performed.

【0021】以上のようにこの実施例によれば、温度,
湿度による伸縮率の大きい光感光性樹脂層の代わりに、
BステージまたはCステージで孔加工する孔あき基板5
として、導体を選択エッチング法で加工するのに耐え
て、かつ、孔をドリル,パンチレーザ等によって形成す
るに耐え、温度,湿度による寸法変化の少ない基板材料
を用いているため、孔4(穴8)の位置精度を得ること
ができる。
As described above, according to this embodiment, the temperature,
Instead of a photosensitive resin layer that has a large expansion and contraction rate due to humidity,
Perforated substrate 5 for drilling at B stage or C stage
As a substrate material that can withstand processing of a conductor by a selective etching method and can be formed with a drill, a punch laser, or the like and has a small dimensional change due to temperature and humidity, The position accuracy of 8) can be obtained.

【0022】また、孔あき基板5は、骨材として、従来
のNa+ (ナトリウムイオン)の多く含まれるガラス繊
維の代わりに、Na+ を数ppm以下としたポリパラフ
ェニレンジフェニルエーテルテレフタラミドの繊維を用
い、含浸樹脂として、従来のエポキシ硬化剤として数重
量パーセント添加しているジシアンジアミドを少なく
し、アロマティックアミンをほぼ等量にアダクトしたも
のを用い、さらに外部から侵入するCl- (塩素イオ
ン)のトラップ剤として、酸化亜鉛の粉末を微量添加し
たものを新規な配合樹脂として用いる。この硬化温度
は、下部のプリント配線板6の種類にもよるが、150
〜180℃に設定して対応する。なお、ポリイミド樹脂
を用いたのでは、逆スパッタリングによる前処理をポリ
イミド樹脂に行ったが、硬化温度が220℃となり、下
部のプリント配線板の耐熱限界を超えることが多く、導
体が酸化し、境界の接着性もよくない。従来のダイシア
ンダイアミド硬化のエポキシ樹脂では、Tg(ガラス転
移温度)が最大125℃と低く、逆スパッタリングやプ
ラズマ処理により表層部が溶けたり焦げたりして、接着
性は改良をみない。新規な配合樹脂は、Tgが最大19
5℃と高く、接着に適した表面処理がなされる。そのた
め、イオン性マイグレーション耐久性を1〜2桁延長す
ることができる。
The perforated substrate 5 is a fiber of polyparaphenylenediphenyl ether terephthalamide containing Na + of several ppm or less as an aggregate instead of the conventional glass fiber containing a large amount of Na + (sodium ion). as a reference, impregnating resin, to reduce the dicyandiamide are added a few percent by weight as a conventional epoxy curing agent, used after adduct with aromatic amines in approximately equal amounts, entering further externally Cl - (chlorine ions) As a trapping agent for the above, a mixture of a small amount of zinc oxide powder is used as a new compounding resin. This curing temperature depends on the type of the lower printed wiring board 6, but is 150
Set it to ~ 180 ° C to handle it. In addition, when the polyimide resin was used, the pretreatment by reverse sputtering was performed on the polyimide resin, but the curing temperature was 220 ° C., which often exceeded the heat resistance limit of the lower printed wiring board, and the conductor was oxidized to cause the boundary. The adhesiveness of is not good. The conventional Dicyan diamide-cured epoxy resin has a low Tg (glass transition temperature) of 125 ° C. at the maximum, and the surface layer portion is melted or burnt by reverse sputtering or plasma treatment, and the adhesiveness is not improved. The new compounded resin has a maximum Tg of 19
As high as 5 ° C, a surface treatment suitable for adhesion is performed. Therefore, the ionic migration durability can be extended by 1 to 2 digits.

【0023】孔あき基板5とプリント配線板6の層間接
着は、孔あき基板5としてアーラミドエポキシプリント
配線板の場合、逆スパッタなしでは、0.5kg/cm
であったが、逆スパッタにより、5kg/cmが得られ
た。但し、孔あき基板としてダイシアンダイアミド硬化
のエポキシ含浸ガラス基材板では、いずれも1/5〜1
/10の強度しか得られず殆ど実用性がない。
The interlayer adhesion between the perforated substrate 5 and the printed wiring board 6 is 0.5 kg / cm without reverse sputtering when the perforated substrate 5 is an aramide epoxy printed wiring board.
However, reverse sputtering yielded 5 kg / cm. However, in the case of the epoxy-impregnated glass base plate cured with Dicyan diamide as the perforated substrate, all of them are 1/5 to 1
Only a strength of / 10 is obtained, which is hardly practical.

【0024】さらに、熱硬化法の適用により孔あき基板
5の均一硬化が実現される。硬化時間は、10〜120
分であり、新規な配合樹脂の硬化温度は、ポリイミド樹
脂の215〜350℃より低く、215℃のはんだ付け
を許容可能な程度にとどまり、孔あき基板5とプリント
配線板6の境界の硬化不十分を解消し、さらに接着力も
飛躍的に向上する。
Further, by applying the thermosetting method, uniform hardening of the perforated substrate 5 is realized. The curing time is 10 to 120
The curing temperature of the new compounded resin is lower than 215 to 350 ° C. of the polyimide resin, and the soldering at 215 ° C. is acceptable, and the curing of the boundary between the perforated substrate 5 and the printed wiring board 6 does not occur. Sufficiently solved, the adhesive strength is also dramatically improved.

【0025】また、フリップチップ1のバンプ1とプリ
ント配線板6の導体7とのコンタクト部分の電気的接続
も、孔あき基板5の新規な配合樹脂の導入により、ガス
放出が僅少なため、良好なものとなる。また、孔あき基
板5として、従来の光硬化型樹脂から熱硬化型エポキシ
樹脂の新規材料を用いる。そして、温度,湿度による伸
縮率と、プリント配線板に対する接着性を向上させる。
イオン性不純物に関して、エポキシ樹脂の硬化剤を、従
来のジシアンジアミドの数重量パーセントの添加量を減
少または廃し、アロマティックアミンの50重量パーセ
ント前後をアダクトの形で配合し、均質な熱硬化物と
し、Tgも、従来の110〜125℃から、150〜1
95℃に向上させる。この実施例に関しては190℃と
している。そして、厚さ方向の伸縮性は、従来の30〜
50ppm/℃,吸湿量0.4〜0.5重量パーセント
を、12〜23ppm/℃,吸湿量0.2〜0.3重量
パーセントに向上する。なお、接着性については、従来
の0.1〜0.3kg/cmから、0.4〜1.6kg
/cmに向上する。この実施例では、105℃,10分
の第1次加熱、160℃,30分の第2次加熱を通じ
て、寸法変化は0.1%以内であり、単一のフリップチ
ップの装着精度に充分対応できる。通常のダイシアンダ
イアミド硬化のエポキシ樹脂では、3%を超え、10%
に達する。硬化温度は、プリント配線板6の種類にもよ
るが、150〜180℃に設定して対応する。
Further, the electrical connection of the contact portion between the bump 1 of the flip chip 1 and the conductor 7 of the printed wiring board 6 is also good because the introduction of the new compound resin of the perforated substrate 5 causes a slight gas emission. It will be Further, as the perforated substrate 5, a novel material from a conventional photocurable resin to a thermosetting epoxy resin is used. Then, the expansion / contraction rate due to temperature and humidity and the adhesiveness to the printed wiring board are improved.
With respect to ionic impurities, a curing agent for epoxy resin is used, in which the addition amount of conventional dicyandiamide is reduced or eliminated, and about 50% by weight of aromatic amine is compounded in the form of an adduct to form a homogeneous thermosetting product. Tg is also 150-1 from the conventional 110-125 ℃
Increase to 95 ° C. In this example, the temperature is 190 ° C. And, the elasticity in the thickness direction is 30 to
50 ppm / ° C, moisture absorption of 0.4 to 0.5% by weight is improved to 12 to 23 ppm / ° C, moisture absorption of 0.2 to 0.3% by weight. In addition, about adhesiveness, it is 0.4-1.6kg from conventional 0.1-0.3kg / cm
/ Cm improves. In this embodiment, the dimensional change is within 0.1% through the primary heating at 105 ° C. for 10 minutes and the secondary heating at 160 ° C. for 30 minutes, which corresponds sufficiently to the mounting accuracy of a single flip chip. it can. Ordinary Dicyan diamide cured epoxy resin exceeds 3% and 10%
Reach The curing temperature depends on the type of the printed wiring board 6, but is set to 150 to 180 ° C. to correspond.

【0026】なお、バンプ接合部の接合補助手段として
銀ペイントを用いた公知例がU.S.P.5,014,
111(May 7,1991)に見られるが、これ
は、フリップチップ部品のバンプと、孔の底部導体との
接触の離脱をつなぐためであり、銀ペイントの永久硬化
後の湿度による伸縮値が大きすぎること、銀のマイグレ
ーションに対して、何等の対策が行われていなかった。
これに対し、この実施例によれば、バンプ接合部の新規
の熱硬化性の銀ペイントとして、その樹脂バインダとし
て用いるエポキシ樹脂の硬化剤を、従来のジシアンジア
ミドの数重量パーセントの添加量を減少または廃し、エ
ポキシ樹脂に対して、アロマティックアミンの50重量
パーセント前後をアダクトの形で配合し、従来より安定
したBステージおよびCステージの状態を維持し、とり
わけ機能抵抗値として1メグオームから100ミリオー
ムへのスイッチング的変化を、中間硬化の条件70〜8
5℃,5〜20分の条件で実現する。また、イオン性不
純物の量を、5ppm以内とし、マイグレーション傾向
を解消し、1重量パーセント以内のZn(亜鉛)添加を
導体粉側にておこない、マイグレーション抑制強化剤と
して作用させる。そして、PCT2気圧,直流電圧印加
で、従来の1時間以内を、100時間以上にできる。
A known example in which silver paint is used as a bonding assisting means for bump bonding is described in US Pat. S. P. 5,014,
111 (May 7, 1991), which is to connect the bump of the flip-chip component with the release of contact with the bottom conductor of the hole, and has a large expansion and contraction value due to humidity after permanent curing of the silver paint. Too much and no migration measures were taken against silver migration.
On the other hand, according to this example, as a novel thermosetting silver paint for the bump bonding portion, the curing agent of the epoxy resin used as the resin binder is reduced by adding several percent by weight of the conventional dicyandiamide. Abolished and compounded around 50% by weight of aromatic amine in the form of adduct with respect to epoxy resin to maintain more stable B stage and C stage conditions than before, especially from 1 megohm to 100 milliohm as the functional resistance value. The switching change of the intermediate curing conditions 70 to 8
It is realized under the conditions of 5 ° C and 5 to 20 minutes. Further, the amount of ionic impurities is set to 5 ppm or less to eliminate the migration tendency, and Zn (zinc) is added within 1 wt% on the conductor powder side to act as a migration suppression strengthening agent. Then, by applying a PCT of 2 atm and a DC voltage, the conventional time of less than 1 hour can be increased to 100 hours or more.

【0027】また、フリップチップ1のバンプ2の接合
部に、導電性ペイント9を穴8に注入し、その接続抵抗
を低め導通状態とする第1次硬化と、接合強度を得る第
2次硬化とを併用することにより、第1次硬化後に機能
的な電気特性の測定を行い、不良と判定したフリップチ
ップ1の取替を可能とし、多くの場合多層からなる高価
なプリント配線板6の再生使用を可能とする。
In addition, in the bonding portion of the bump 2 of the flip chip 1, the conductive coating 9 is injected into the hole 8 to lower the connection resistance thereof to make it conductive and the primary curing, and the secondary curing to obtain the bonding strength. The combined use of and makes it possible to replace the flip chip 1 that has been determined to be defective by measuring the functional electrical characteristics after the primary curing, and in many cases, to reproduce the expensive printed wiring board 6 composed of multiple layers. Enables use.

【0028】なお、アロマエポキシをアーラミド繊維か
らなる布または紙に含浸したものをプリント配線板6に
用いてもよい。
The printed wiring board 6 may be made by impregnating a cloth or paper made of aramide fiber with aromatic epoxy.

【0029】[0029]

【発明の効果】この発明のフリップチップの搭載方法に
よれば、アーラミド短繊維紙をラインフォースメントと
し、アロマティックアミンをアダクト性硬化剤として配
合したエポキシ系樹脂を含浸樹脂とするプリプレグシー
トを加熱してリジッド性を付与した後、孔を開けて形成
した孔あき基板は、温度および湿度による寸法変化が少
なく、孔の位置精度が安定し、フリップチップの配置精
度の向上をはかることができる。
According to the flip chip mounting method of the present invention, a prepreg sheet containing aramide short fiber paper as a line force and an epoxy resin as an impregnating resin containing an aromatic amine as an adduct hardening agent is heated. Then, the perforated substrate formed by forming the holes after providing the rigid property has little dimensional change due to temperature and humidity, the positional accuracy of the holes is stable, and the arrangement accuracy of the flip chip can be improved.

【0030】また、プリント配線板の表面に逆スパッタ
リングを行うことにより、孔あき基板とプリント配線板
との境界面の接合強度が向上し、フリップチップのバン
プとプリント配線板の導体との接合強度の向上がはかれ
る。また、温度および湿度に対して孔あき基板の厚さ方
向の伸縮率と同程度の厚さ方向の伸縮率を有し、樹脂バ
インダとしてアロマティックアミンをアダクトしたエポ
キシ系の樹脂からなる導電性ペイントを、フリップチッ
プのバンプとプリント配線板の導体との接合部に用いる
ことにより、接合強度が増大するとともに、マイグレー
ションなどの電気特性の向上をはかることができる。
Further, by performing reverse sputtering on the surface of the printed wiring board, the bonding strength at the interface between the perforated substrate and the printed wiring board is improved, and the bonding strength between the bumps of the flip chip and the conductors of the printed wiring board is improved. Can be improved. Further, a conductive paint made of an epoxy-based resin that has an expansion / contraction ratio in the thickness direction similar to the expansion / contraction ratio in the thickness direction of a perforated substrate with respect to temperature and humidity and that has an aromatic amine adduct as a resin binder. Is used for the joint between the bump of the flip chip and the conductor of the printed wiring board, the joint strength can be increased and the electrical characteristics such as migration can be improved.

【0031】さらに、上記導電性ペイントは第1次硬化
工程におけるBステージを維持することができ、この状
態でフリップチップの機能検査を行い、不良チップを良
品チップに取り替えたのち、第2次硬化工程を行うこと
により、プリント配線板の使用効率を高めることができ
る。
Furthermore, the conductive paint can maintain the B stage in the primary curing step, and in this state, the function test of the flip chip is performed, and the defective chip is replaced with a non-defective chip, and then the secondary cure is performed. By performing the process, the use efficiency of the printed wiring board can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一実施例のフリップチップの搭載方
法を示す工程断面図である。
FIG. 1 is a process sectional view showing a method of mounting a flip chip according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 フリップチップ 2 バンプ 3 プリプレグシート 4 孔 5 孔あき基板 6 プリント配線板 7 導体 8 穴 9 導電性ペイント 1 Flip Chip 2 Bump 3 Prepreg Sheet 4 Hole 5 Perforated Board 6 Printed Wiring Board 7 Conductor 8 Hole 9 Conductive Paint

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 バンプ構造の接続手段を有するフリップ
チップを、表面に導体を形成したプリント配線板へ搭載
するフリップチップの搭載方法であって、 アーラミド短繊維紙をラインフォースメントとし、アロ
マティックアミンをアダクト性硬化剤として配合したエ
ポキシ系樹脂を含浸樹脂とするプリプレグシートを加熱
してリジッド性を付与した後、前記フリップチップのバ
ンプ搭載位置に孔を開けて孔あき基板を形成する工程
と、 前記プリント配線板の表面に逆スパッタリングを行い、
前記孔あき基板を前記プリント配線板に圧接しながらB
ステージからCステージに加熱硬化して前記孔あき基板
を前記プリント配線板に接着する工程と、 温度および湿度に対して前記孔あき基板の厚さ方向の伸
縮率と同程度の厚さ方向の伸縮率を有し、樹脂バインダ
としてアロマティックアミンをアダクトしたエポキシ系
の樹脂からなるAステージの導電性ペイントを、前記孔
あき基板の孔に注入し、前記フリップチップのバンプを
前記孔に挿入する工程と、 前記導電性ペイントをBステージに加熱硬化して接触抵
抗値を前記プリント配線板の導体のレベルに下げる第1
次硬化工程と、 前記導電性ペイントをCステージに加熱硬化する第2次
硬化工程とを含むことを特徴とするフリップチップの搭
載方法。
1. A flip chip mounting method for mounting a flip chip having a bump structure connecting means on a printed wiring board having a conductor formed on the surface thereof, wherein aramide short fiber paper is used as a line force, and an aromatic amine is used. A step of forming a perforated substrate by forming a hole in the bump mounting position of the flip chip after heating a prepreg sheet containing an epoxy resin impregnated with an epoxy resin mixed as an adduct curing agent to provide rigid property, Performing reverse sputtering on the surface of the printed wiring board,
While pressing the perforated substrate against the printed wiring board, press B
A step of heat-curing from the stage to a C stage to bond the perforated substrate to the printed wiring board; and an expansion and contraction in the thickness direction of the perforated substrate with respect to temperature and humidity. And a step of injecting an A-stage conductive paint made of an epoxy-based resin adducting aromatic amine as a resin binder into the holes of the perforated substrate and inserting the bumps of the flip chips into the holes. And heat-curing the conductive paint on the B stage to lower the contact resistance value to the level of the conductor of the printed wiring board.
A method of mounting a flip chip, comprising: a secondary curing step; and a secondary curing step of thermally curing the conductive paint on a C stage.
JP6831992A 1992-03-26 1992-03-26 Flip chip mounting method Expired - Fee Related JP2774409B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6831992A JP2774409B2 (en) 1992-03-26 1992-03-26 Flip chip mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6831992A JP2774409B2 (en) 1992-03-26 1992-03-26 Flip chip mounting method

Publications (2)

Publication Number Publication Date
JPH05275490A true JPH05275490A (en) 1993-10-22
JP2774409B2 JP2774409B2 (en) 1998-07-09

Family

ID=13370386

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6831992A Expired - Fee Related JP2774409B2 (en) 1992-03-26 1992-03-26 Flip chip mounting method

Country Status (1)

Country Link
JP (1) JP2774409B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08250835A (en) * 1995-03-10 1996-09-27 Nec Corp Method for mounting lsi package having metallic bump
JP2014060279A (en) * 2012-09-18 2014-04-03 Nec Corp Semiconductor package inspection method, and mounting method and mounting structure using the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08250835A (en) * 1995-03-10 1996-09-27 Nec Corp Method for mounting lsi package having metallic bump
JP2014060279A (en) * 2012-09-18 2014-04-03 Nec Corp Semiconductor package inspection method, and mounting method and mounting structure using the same

Also Published As

Publication number Publication date
JP2774409B2 (en) 1998-07-09

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