JPH0281155A - Transfer system for width extension data - Google Patents

Abstract

PURPOSE:To attain the high-speed transfer of the data on the data width extension by sending a pattern designated in an extension bit width transfer mode via a data signal line while performing the designation of addresses via an address signal line and then carrying out the transfer of data via both signal lines. CONSTITUTION:In a normal state the address and data signals are transmitted and received between the transfer devices 70 and 71 via an address signal line 72 and a data signal line 73 respectively. When the extension is desired for the width of data that can be transferred at one time, the device 70 transmits first an address signal via the line 72 and at the same time sends a specific pattern designating that the data width is switched to an extended mode via the signal line 73. The specific pattern is detected by a transfer mode detecting circuit 76 and therefore a data transfer switch control circuit 77 switches the transfer mode to the data width extension mode. Then the device 70 uses both lines 72 and 73 as the data signal lines to extend the transfer data width and transfers the data to the device 71. The data having its extended width is stored in a data register 75.

Description

DETAILED DESCRIPTION OF THE INVENTION (Summary) This invention relates to a width-extended data transfer method for transferring data whose data width has been expanded between devices.

without increasing the number of signal lines or circuit scale between devices.
The purpose is to transfer data with expanded data width at high speed.

In a system that uses address signal lines and data signal lines to transfer data while specifying addresses between devices,
While specifying the address using the address signal line, a specific pattern specifying the extended bit width transfer mode is sent using the data signal line.
Thereafter, both the address signal line and the data signal line are used to transfer data whose data width has been expanded.

[Industrial application field]

The present invention relates to a width-extended data transfer method for transferring data whose data width has been expanded between devices.

[Conventional technology]

The fourth example is a system configuration using the conventional DMA transfer method.
As shown in the figure. In FIG. 4, 4 is an input/output channel device, 5 is a main storage device, and 6 is a channel control device, where the channel control device 6 is a control circuit 61. address register 6
2. It is configured to include a data register 63 and the like. 16 between the input/output channel device 4 and the channel control device 6.
Bint address lines, data lines, and control signal lines are connected, and 16-bit memory address lines, memory data lines, and control signal lines are connected between the main storage device 5 and the channel control device 6, respectively. .

The data transfer procedure by this conventional device will be explained below with reference to FIG. FIG. 5 shows input/output channel device 4.
Main memory 5. 5 is a time chart of signals transmitted and received between channel control devices 6. FIG.

First, the data transfer operation from the input/output channel device 4 to the main memory device 5 will be explained. Input/output channel device ff14
address ADD and data DATA are sent to the channel control device 6, and the service in (Service
e In) When SRV I is sent to the control circuit 61, the address register 62 stores the address ADD, the data register 63 stores the data DATA, and the control circuit 61 sends the bus return (ENA) to the main memory 5. do.

In response, the main storage device 5 returns a memory OK MOK to the control circuit 61. As a result, the channel control device 6
writes the memory address MADD from the address register 62 and the memory data MDATA from the data register 63 into the main storage device 5, respectively.

After that, the control circuit 61 stops sending the bus request ENA, and outputs a service out (Service 0ut) SRV O to the input/output channel device ff4. Then, the input/output channel device 4 becomes service in SR.
V [stop.

Next, the data transfer operation from the main storage device 5 to the input/output channel device W14 will be explained. The input/output channel device 4 specifies the address ADD to be read and sends the service manual input SRVI to the control circuit 61. The control circuit 61 sends a bus return request (ENA) to the main storage device 5, and in response, the main storage device 5 returns a memory OK MOK.

As a result, the channel control device 6 uses the address register 62.
The memory address MADD is read from the main memory device I5, and the memory data MDATA at that address is read from the main memory device I5 and stored in the data register 63.

The contents of this data register 63 are stored in the input/output channel device 4.
The control circuit 61 outputs service out 5RVO.
is output to the input/output channel device 4.

The human output channel device 4 stops the service in SRV l. As a result, the data at the desired address in the main memory device 5 is sent to the input/output channel device 4.

[Problem to be solved by the invention]

In conventional systems, when trying to expand the data width of data sent and received between devices at one time from, for example, 16 bits to 32 bits, the number of data lines (data buses) must be reduced from 16 to 32. In this method, the circuit scale of the data circuit section, which is the main element of the nine circuits, doubles, and the number of terminals of the interface section also increases. When the circuit scale and number of terminals increase in this way, it becomes difficult to convert the device into an LSI.

This increases the size of the device and increases the number of signal lines between devices, resulting in high costs.

Therefore, it is an object of the present invention to provide a width-extended data transfer method that can transfer data whose data width has been expanded at high speed without increasing the number of signal lines between devices or the circuit scale.

[Problem to be solved by the invention]

FIG. 1 is an explanatory diagram of the principle of the width expansion data transfer method according to the present invention. In FIG. 0, To, 71 is a transfer device, 72 is an address signal line, and 73 is a data signal line.

74 is an address register, 75 is a data register 76 is a transfer mode detection circuit, and 77 is a data transfer switching control circuit.

The width expansion data transfer method according to the present invention is applicable to a system in which data is transferred while specifying an address between devices 70 and 71 using an address signal line 72 and a data signal line 73. While doing so, a specific pattern specifying the extended bit width transfer mode is sent on the data signal line 73.

After that, both the address signal line 72 and the data signal line 73 are used to transfer data whose data width has been expanded.

is transferred to the device 71. The data whose data width has been expanded is stored in the data register 75.

[Effect]

Under normal conditions, the address signal line 72 is connected between the devices 70 and 71.
An address signal is sent and received via the data signal line 73, and a data signal is sent and received via the data signal line 73, thereby performing data transfer.

If you want to expand the data width that can be transferred at one time, first, the device 70 sends out an address signal via the address signal line 72 and at the same time switches to a mode in which the data width is expanded via the data signal line 73. Sends a specific pattern that specifies the This specific pattern is detected by the transfer mode detection circuit 76, and the data transfer switching control circuit 77 switches the transfer mode to the data width expansion mode accordingly.

Next, the device 70 expands the transfer data width by using both the address signal line 72 and the data signal line 73 as data signal lines. .

FIG. 2 shows a DMA transfer system using a wide width data transfer method as an embodiment of the present invention. In FIG. 2, 1 is a channel control device, 2 is an input/output channel device, and 3 is a main storage device.

In this system, a channel control device 1 mediates and controls data transfer between an input/output channel device 2 and an address register 13.

A control signal line 21 and a bus line 22 are stretched between the channel control device 1 and the input/output channel device 2. bus line 22
consists of an address bus 22^ and a data bus 22o.

Data bus 22o consists of 16 data signal lines (16 bits) and two parity signal lines (2 bits), and address bus 22^ consists of 16 address signal lines (16 bits). In addition, the channel control device 1 and the main storage device 3
A control signal line 31, a 16-bit memory address bus 32, and a memory data bus (+parity bus) 33 are stretched between them.

The channel control device l includes a control circuit 11. Transfer mode pattern detection circuit 12. Address register 13, data register 14. Selector 15. It is configured to include gates 61 to G7 and the like. The control circuit 11 includes an input/output channel device 2.
Control signal lines 21 and 31 for transmitting and receiving control signals between the main storage device 3 and the main storage device 3 are connected. The control circuit 11 performs various controls such as transmission and reception of control signals between the input/output channel device 2 and the main memory device 3, opening/closing of the game (Gl-07) in the channel control device ifl, and writing/continuation of registers.

A data bus 22o from the input/output channel device 2 is connected to the transfer mode pattern detection circuit 12 via a gate G7, and the transfer mode pattern detection circuit 12 is connected via this data bus 22o.

3 is a specific pattern that specifies the 32-bit transfer mode.
When the 2-bit transfer mode designation pattern is received, it is detected and transmitted to the control circuit 11.

In this embodiment, the transfer mode designation pattern is a bit pattern in which all bits (16 bits) are "F" and the parity pits are odd parities. Note 1
In the 6-bit transfer mode, the parity is assumed to be even parity.

Address register 13 has address bus 22a)
Gl, thereby setting the input/output channel device 2 to 7 addresses ADD. Channel control device 6 sends this address ADD to main memory device 3 via gate G2 and memory address bus 32.

The data register 14 is a register that can store 32-bit data, and has a data input section.

Data bus 2 via gate G3 and selector 15
In addition to the address bus 2o, an address bus 22 is also connected, so that a total of 32 bits of data can be input. That is, for example, the data bus 220 is assigned to the lower 16 bits of 32-bit data, and the address bus 220 is assigned to the upper 16 bits. This data register 14 also has a data input section. A 32-bit wide memory data bus 32 is connected from the main memory device 3 via a gate G5 and a selector 15.

The 32-bit data output section of the data register 14 is connected to the memory data bus 33 via a gate G6, and is also connected to the address bus 22 of the bus line 22 via a gate G4.
and the data bus 22o.

The operation of this embodiment device will be explained below with reference to FIG. FIG. 3 shows a channel control device 1.

Input/output channel device 2. 3 is a time chart of signals sent and received between the main storage devices 3. FIG.

First, the operation of specifying an address from the input/output channel device 2 to the main memory device 3 via the channel control device 1 and transferring 32 bits of data at once will be explained.

The input/output channel device 2 first sends the write address ADD to the address register 13 of the channel control device l via the address bus 22^, and also sends a 32-bit transfer mode designation pattern specifying switching to the 32-bit mode via the data bus 22o. (i.e. all “F” bits +
(pattern of odd parity bits).

The transfer mode pattern detection circuit 12 checks the input pattern from the data bus 22o, detects this 32-bit transfer mode designation pattern, and learns that the transfer mode has been expanded from 16-bit width data to 32-bit width data. The control circuit 11 is notified of this. Meanwhile, during this time, the address ADD from the input/output channel device 2 is stored in the address register 13.

The control circuit 11 sends the path return (ENA) to the main storage device 3 in response to the service-in SRVI.

During this time, the input/output channel device 2 uses the address bus 22 at the timing following the previous address specification and mode specification.
The 32-bit wide data is sent to the data register 14 of the channel controller 1 at one time using both the system and the data bus 22o, so that the 32-bit wide data is stored in the data register 14.

When the main storage device 3 receives the pass request request (ENA), it returns a memory OK MOK to the control circuit 11. As a result, the channel control device 6 receives the write memory address M from the address register 13 via the memory address bus 32.
ADD and 32-bit memory data MDATA from the data register 14 are sent to the main storage device 5 via the memory data bus 33, respectively, and the data is written at the address.

When the control circuit 11 receives the memory OK MOK, it stops the bus request ENA and sends a service out 5RVO to the input/output channel device W2.

Accordingly, the input/output channel device 2 is set to service in SR.
Stop V1 and end the transfer process.

Next, the operation of transferring 32 bits of data at once from the main memory device 3 to the input/output channel device 2 will be explained. First, the input/output channel device 2 sends the address ADD to the channel control device 1 via the address bus 22 and the 32-bit transfer mode designation pattern via the data bus 22o, as described above.

As a result, the control circuit 11 sends the bus request ENA to the main storage device 12F3 and also sends the address register 1
The memory address MADD is sent from 3. The main storage device 3 returns a memory OK MOK. Next, the channel control device I selects the memory address MADD of the main storage device 3.
memory data MDATA is read and stored in the data register 14.

The 32-pin data in the data register 14 is further transferred to the traffic channel device 2 via the bus line 22 using both the address bus 22^ and the data bus 22o. Finally, the control circuit 11 sends the service out 5RVO to the input/output channel device 2, and the input/output channel device 2 stops the service manual SRV■ and ends the transfer process.

Furthermore, when transferring 16-bit wide data as in the past, the input/output channel device 2 does not send out the 32-bit transfer mode specification pattern, but instead sends the address ADD via the address bus 22 as in the past. , data bus 2211
It is sufficient to send 16-bit data DATA via the data register 14, and in this case, the lower 16 bits of the data register 14 are treated as valid data.

In the above description, the opening and closing operations of each game Gl-07 have been omitted, but it is clear that these are opened and closed as appropriate by the control circuit 11 in accordance with each operation.

〔Effect of the invention〕

As explained above, according to the present invention, the data width (number of bits) of transfer data that can be transferred at one time can be increased without increasing the number of interface signal lines between devices, and the amount of transfer per unit access can be increased. This increases the data transfer rate, and reduces the frequency of channel device transfer accesses, thereby improving the CPU processing power. Furthermore, the transfer data width can be increased without increasing the size of the device.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a block diagram showing the configuration of a DMA transfer system using a width expansion data transfer method as an embodiment of the present invention. FIG. 3 is a time chart of signals in the system shown in FIG. FIG. 4 is a diagram showing the configuration of a DMA transfer signal according to a conventional transfer method; FIG. 5 is a system time chart in the system shown in FIG. In fig. 1.6--Channel control device 2.4--Person output channel device 3.5--Main storage device 11.61--Control circuit 12-Transfer mode pattern detection circuit 13.62--Address register 14゜21゜22mm 22゜63--Data register selector s 1-va@signal line/bus line Address bus (16 bits) Data bus (16 bits) Memory address bus (16 bits) Memory data bus (32 bits)

Claims (1)

[Claims] In a system in which data is transferred while specifying an address between devices using an address signal line (72) and a data signal line (73), the address signal line (72) is used to specify an address. while transmitting a specific pattern specifying the extended bit width transfer mode on the data signal line (73), and then transmitting data whose data width has been expanded using both the address signal line (72) and the data signal line (73). A method for transmitting width-extended data, which is characterized by transmitting .