JPH041544B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a signal transmitting and receiving device, and particularly to a signal transmitting and receiving device suitable for transmitting and receiving signals between control devices and between a control device and an input/output device of a computer. Many process controls, including conveyor control, machine tool control, water and sewage-related control, and chemical plant control, are becoming increasingly complex, and high reliability in high-speed processing is becoming increasingly important. Digital computer control is becoming more and more popular. In addition, in many cases, the device is connected to a minicomputer using a bidirectional bus line, processes are controlled by the minicomputer, and signals are exchanged with the minicomputer. In such a case, data in parallel word format received from the bidirectional data bus is converted to serial word format and transmitted to the peripheral device, and data in serial word format from the peripheral device is converted to parallel word format and transmitted to the corresponding device. A method of transmitting signals to a minicomputer may be used. Transmitting signals with peripheral devices in a serial word format is an effective method because the number of transmission lines provided is extremely reduced compared to the case where data transmission is performed in a parallel word format. The present invention relates to a signal transmitting/receiving device suitable for such signal transmission. Conventionally, this type of signal transmitter/receiver was an IC (Integ-
rated circuit), but even a normal-sized circuit uses 50 to 60 ICs.
This posed a major problem in miniaturizing the device. Furthermore, the configuration of the signal transmission circuit must be changed depending on the type of device to be connected, and there is an inherent problem that the wire logic method cannot cover a wide range. Microcomputers and their surrounding LSIs are known methods that have been used to solve these problems.
(Large Scale Integrated Circuit). It is US Patent No.3975712
“Asynchronous Communication Interface
Adapter” (Aug.17.1976), the so-called ACIA. It is connected to the microcomputer via a bus line. In this example, it is connected to the modem via conductor 109 as shown in FIG. 2. This ACIA is equipped with transmission means for converting parallel data into serial data and transmitting it, means for receiving serial data and converting it into parallel data format, and interface buffer means for controlling transmission and reception. The format is fixed at 8 bits, and there is no mention of the connection method for the control device connected to ACIA.In actual control, the bit configuration is also different.
It is not fixed to 8bit, and there are various connection methods for control devices. However, ACIA has the disadvantage of not being able to respond to these and is not versatile. Moreover, this is its biggest limitation,
ACIA is just an MPU (Micro Processing
It can only be used by connecting it with the unit) via a bus line. However, in actual application fields, there are devices that do not necessarily have a processor, and signals are often sent and received with them. From this point of view, ACIA has the disadvantage that it can only be used in conjunction with a CPU. SUMMARY OF THE INVENTION An object of the present invention is to provide a general-purpose signal transmitting/receiving device for transmitting and receiving signals between a bidirectional bus line and a serial data transmission path in digital data transmission. Another object of the present invention is that the signal transmitting/receiving device is
An object of the present invention is to provide a signal transmitting/receiving device capable of transmitting and receiving data in a parallel word format or a serial word format regardless of whether or not it is connected to a signal transmitting/receiving device. Another object of the present invention is to provide a signal transmitting and receiving device capable of transmitting and receiving signals without being subject to any restrictions due to the number of connections in the multi-drop connection method of control devices connected to the serial word data transmission line. It is about providing. In order to achieve the above object, the present invention includes a first buffer memory for storing data in parallel word format, and a signal in serial word format by converting the data in parallel word format read from the memory into serial word format. means for transmitting data to a transmission line; a second buffer memory for converting and storing received data in serial word format into parallel word format; and a transmitter for transmitting a read signal from the memory via a bidirectional bus line. It is characterized by having the means. In order to achieve the above object, the present invention makes effective use of the first buffer memory even when the word lengths stored in the first buffer memory are different.
The present invention is characterized in that word length designation means is provided and the word length is stored in the first buffer memory according to the designated word length. In order to achieve the above object, the present invention has one control device connected to the serial word format data transmission path for one signal transmitting/receiving device, or N (≧
2. A feature is that a means for specifying whether the number is a natural number is provided, and signals are transmitted and received based on the specification. In order to achieve the above object, the present invention transmits and receives signals when a CPU is connected via the bidirectional bus line, or when connected to a passive device that does not have a CPU. The feature is that a selection specifying means is provided for switching and transmitting and receiving signals. The present invention is characterized in that a conflict monitoring means is provided between the timing of writing data to the first buffer memory and the timing of reading data from the first buffer memory, and data is written and read at timings where there is no conflict. First, an outline of the signal transmission device targeted by the present invention will be described. FIG. 1a is a block configuration diagram when signals are transmitted and received between control devices 1a and 1b. A case is shown in which control devices 1a and 1b are connected by a signal transmission path STL and signals are transmitted between each control device. FIG. 1b shows one control device 1a and a plurality of control devices 2 (or input/output devices, 2a to 2).
An example is shown in which signals are transmitted and received between In this way, signals can not only be sent and received on a one-to-one basis between control devices, but also often connected in a one-to-N system, a so-called multi-drop system, as shown in FIG. 1B. The signals handled may be ON-OFF 1bit signals, such as signals from limit switches, or may be composed of 8bits, or 16bits.
There are cases such as. An object of the present invention is to provide a signal transmitting device that can be used in any of these cases. Figure 2 shows the circuit configuration used when using a microcomputer, where 3 is a microprocessor, 4 is a signal transmission LSI, 5 is an input/output adapter, 6 is a memory, 7 is a modulation circuit, and 7a is a transmission line. It is. For example, the above-mentioned ACIA has such a circuit configuration (see FIG. 2 of the above-mentioned USP.3975712). However, it cannot be used unless it is combined with a CPU. The present invention uses part of the functions of the microprocessor 3 and part of the functions of the memory 6 in FIG. 2 for signal transmission.
One of its characteristics is that it was integrated into an LSI to achieve high performance while also aiming for versatility. FIG. 3 shows a block diagram for explaining the signal transmitting/receiving device 8 of the present invention and its peripheral circuits. Table 1 summarizes the explanations of the symbols.

【table】

[Table] One side of the signal transmitting/receiving device (LSI) 8 is the control device 1
Or connected to the input/output device 2. This connection is used to write data to be transmitted or read transmitted data, and includes address ADR, data
DATA, R/W to distinguish between reading and writing;
It consists of a strobe signal STB that provides timing for reading and writing. In these cases, the signal transmission method differs depending on whether the connected circuit is an active circuit or a passive circuit; in the case of an active circuit, the signal is input/output to the signal transmitting/receiving device 8 in external control mode, and in the case of a passive circuit, input/output is in internal control mode. be done. This distinction is given by E/I, which distinguishes between external control and internal control. Also, word length WL is data DATA
The number of bits is specified depending on the type of control device 1 and input/output device 2. Connected to the other side of the signal transmission device 8 is a circuit that handles serial data, with serial outputs SO1,
SO2 is added to the driver 9 in a bipolar modulated form and connected to the transmission lines Ta and Tb through isolation transformers 11a and 11b. On the other hand, the input from the transmission path passes through the isolation transformer 11b and the receiver 10 and becomes a serial input SI. By the way, the serial output is bipolar modulated, and the details are as shown in Figure 4. Every time the unmodulated serial output (b, i in Figure 4) becomes 1, SO1 (in the same figure) and SO2
(same figure) alternately generate outputs. This output is connected to the driver 9 and the transmission line via the isolation transformer 11a.
Sent to Ta. 11a' and 11b' indicate those on the receiving side. In the transmission path, pulse signals alternating between positive and negative are obtained every time the unmodulated serial signal becomes 1. Therefore, on the receiving side, by full-wave rectifying and amplifying the output of the isolation transformer 11b, an unmodulated serial output can be obtained. This is represented as a luciver 10. The transmission mode TM is used to specify the connection form of the transmission path. The details are shown in FIG. In the 1:1 connection in FIG. 5a, it is sufficient to simply cross the input and output, but in the 1:N connection as shown in FIG. 5b, a bus T _aB and T _bB configuration is adopted. FIG. 6 shows the format of data on the transmission line. FIG. 6i shows the case of one-to-one connection. In a 1:1 connection, serial data is sent to block addresses A, SYC, and
A and 4-byte data D are transferred in two consecutive inversions. Since the data capacity is 256 bits,
Eight such blocks constitute one data frame, but the data is sent out cyclically and continuously, and the input and output are operated independently and asynchronously. Although the block address may actually be 3 bits, an 8-bit space is reserved to simplify the circuit. Note that 1 indicates the inverted value of A, and 1 indicates the inverted value of D. D is 8-bit data and SYC is a synchronization signal consisting of 24 bits (0, 1, 1, ... 1,
1,0). Figure 6 shows an example of signal transmission from a master station to a slave station in a 1-to-N connection, Figure 6 shows an example of signal transmission from a slave station to a master station, and Figure 6 is an explanatory diagram of FLAG signal transmission. be. On the other hand, in the 1:N connection, the configuration of serial data is the same as in the 1:1 connection, but the difference is that the input and output are synchronized. That is, the master station transmits data continuously, but the slave station transmits data to the master station while receiving data only when the block address matches its own address. In this case, as in the case of 1:1 connection, data from the master station is sent out cyclically, so the slave station responds once per frame. FIG. 7 shows the internal configuration of the signal transmitting/receiving device 8 implemented as an LSI for realizing these operations. First, I will give an overview. Address information ADR0 to 7 added from the outside in Figure 7
has two write and read buffer memories 12
It is added as the address of a, 12b.
DATA0-15 are applied to buffer memory 12a through gate circuit 13a. Here, the directions of the gate circuits 13a and 13b are reversed for writing and reading, but R/W is applied as a gate signal to one of them, and R/W is applied to the other through the inverter circuit. , one gate circuit is always open to control the direction of data. STB joins the write buffer memory 12a and provides write timing. By the way, among the above four types of signals, gate circuit 1 is used for ADR, R/W, and STB.
The output of the input/output scanner 15 is connected through 3c, d, and e. The input/output scanner 15 automatically accesses input/output sequentially, and the gate circuit 1
When 3c, d, and e open, the above 3
A seed signal is output. This should be determined depending on whether the control is external or internal, and the gates of gate circuits 13c, d, and e are controlled by E/I. On the other hand, the buffer memory 12a switches its internal decoder using WL to change the word length to be accessed. Further, the buffer memory 12a has independent input and output addresses and data, and can be arbitrarily accessed from the opposite side. Changing the word length by WL is described in detail in the earlier Japanese Patent Application No. 127958/1983 filed by the same applicant, so the explanation thereof will be omitted here. The upper two bits A of the bit counter 16a are stored at one address of the buffer memory 12a on the writing side.
3, A4 and the output 3 bits A5, A6, A7 of the block counter 17 are added to form a 5-bit address. A5-7 are also connected to the selector 18b and are selected by E/I between them and one input ADR5-7. This output becomes an input to another selector 18c, and is selected between the outputs D0 to D7 of the buffer memory 12a. This output is the shift register 19
This is the parallel input for a and 19b. The serial output of shift registers 19a and 19b is sent to selector 18.
a, and the inverter circuit 14,1
It becomes a serial input through 4'. Selector 18
One input of a is the output of the synchronization signal generation circuit 20, and the output SD is applied to the modulation circuit 21 to generate bipolar modulated outputs SO1 and SO2. On the other hand, the reference clock TCLK given externally is 1/
The frequency is divided by the 16 frequency divider circuit 22 and the transmit clock is
TCLK' and shift registers 19a, 19b,
The bit counter 16a serves as a clock for the synchronization signal generation circuit 20 and the modulation circuit 21. on the other hand,
TCLK' is also applied to the transmit timing circuit 23. The transmission timing circuit 23 also receives information on the transmission mode TM and generates a series of timing signals necessary for transmission. The load inputs of shift registers 19a and 19b are supplied as timing signals.
TT1, block counter 17 count input
TT2, selection input for two types of selectors 18a and b
TT4 and a reset signal TT5 of the synchronization signal generation circuit 20. Note that the transmission timing circuit 23 that generates these timings can be easily configured with a counter and a decoder. Serial input SI is applied to shift register 19c. This parallel output is the address register 29,
It is added to the comparator 24 and the buffer registers 12c and 12d of the buffer memory 12b for reading. On the other hand, the serial output is from inverter circuit 1
After passing through the bit counter 16b, the output of the address register 29 is added to the block counter 17 on the transmitting side and becomes the address of the buffer memory 12b together with the output of the bit counter 16b. The output of the shift register is compared with ADR5-7, and if they match, a block address match command BS is issued.
The serial input SI is connected to the clock recovery circuit 26 on the one hand.
RCLK is added to generate the reception clock RCLK. SI also joins the synchronization signal detection circuit 27 to generate a synchronization detection signal SY. The receiving clock
RCLK is used as a clock for the shift register 19b and the synchronization signal detection circuit 27, and is also applied to the reception timing circuit 28 to generate synchronization detection signals SY,
It generates the timing signals necessary for reception along with the address match command BS and transmission mode TM signals.
These timing signals are the write strobe signal RSTB to the receiving buffer memory 12b, the clock RT1 of the bit counter 16b, and the reset signal.
RT2, address register 29 set signal RT
3. Timing signal RT4 of collation circuit 25, start request signal RT5 to transmission timing circuit 23, 6
It is a kind. Note that the reception timing circuit 28 can also be configured with a counter and a decoder. Next, the operation of the circuit configuration shown in FIG. 7 will be explained. First, a case will be described in which data to be transmitted via the transmitting/receiving device 8 is written into the internal buffer memory 12a. There are two cases depending on the designation by signal E/I. That is, the external control mode E is a case where data is written into the buffer memory 12a by an external signal, and corresponds to this mode, for example, when a microprocessor is connected. In addition, in internal control mode I, when there is no active circuit such as a microprocessor, external data is transferred to the buffer memory 12 by the signal transmitting/receiving device.
This is the case when writing to a. The time chart for external control mode is 8th.
As shown in the figure. R/W, ADR0-7 signals (Fig. 8 a, b) are given from outside, DATA0-15
(FIG. 8c), write data corresponding to ADR0-7 is input. At this time, the output signal of the input/output scanner 15 is not outputted as a gate signal due to the action of the gates 13c, 13d, and 13e, which are selectively opened and closed by the E/I signal, and does not cause any interference with signals applied from the outside. In this state, the strobe signal
By applying STB (FIG. 8d), data is written to the buffer register 12a. Note that the output signal of the gate 13d indicates a floating state. A time chart for internal control mode I is shown in FIG. The input/output scanner 15 is a reference clock.
Based on BCLK (Figure 9a), signal 13c (Figure 9a)
Figure c), signal 13d (Figure 9b), signal 13e (Figure 9
Figure d) is output. Each of these signals
The LSI signal transmission/reception according to the present invention is input to the buffer register 12a as ADR0-7, R/W, and STB signals, and is also transmitted via the bidirectional terminal (Fig. 7, terminal double circle ◎ mark). It is output to the outside of the device 8. DATA0 to 15 are output to the outside of this device.
ADR0-7 and R/W are referenced externally and a predetermined signal is input to the buffer memory 12a. As a result, the input/output scanner 1 is stored in the buffer memory 12a.
Data D0 to D127 (FIG. 9e) corresponding to addresses A0 to A127 generated by 5 are written.
Note that FIG. 9a shows the reference clock signal BCLK. Next, we will discuss the selection of word length. The data word length is WL = 2 for three cases: 1-bit access (bit mode), 8-bit access (byte mode), and 16-bit access (word mode).
Switched by two signals (WL0, WL1).
An example is shown in Table 2. This is the same as the case of the earlier application mentioned above.

[Table] Here, we will discuss sharing data input/output terminals and address input/output terminals in connection with word length selection. FIG. 10 is an explanatory diagram of common use of terminals. The figure shows the case where the storage capacity is 256 bits. In 1-bit mode, an address of 8 bits (1 x 2 ⁷ = 256) is required, and in case of 8-bit mode, an address of 5 bits (8 bits) is required.
×2 ⁴ = 256) addresses are required, and in the case of 16-bit mode, 4 bits (16 × 2 ³ = 256) addresses are required. In FIG. 10, ADR0 to ADR3 (terminal numbers 12 to 15) in the 1-bit mode and ADR3 in the 8-bit mode are the common parts of the DATA terminal and the address terminal. Since they are not used simultaneously, the sharing described here is also possible. If not shared, four more terminals (10th
In the figure, 20 to 23) are required. Therefore, by sharing the terminals, the number of terminals can be saved, the LSI chip size can be reduced,
This has a great effect on miniaturizing LSI packages. The contents of buffer memory 12a can be read by specifying a read address.
This address is designated by the bit counter 16a and block counter 17. In this way, the data is transmitted while being read, and the transmitted signal is in the signal format shown in FIG. A transmission time chart is shown in FIG. That is, the reference clock signal TCLK is frequency-divided by the 1/16 frequency divider circuit 22 to generate TCLK'. The transmission timing circuit 23 which uses this as an input signal generates timing signals TT1 to TT5 (FIG. 11 b to f). The bit counter 16a and block counter 17 count the timing signal TT2 to obtain signals A3 to A7 (FIG. 11g to K).
The synchronization signal generation circuit 20 generates a synchronization pattern signal SYC (FIG. 11l) having a length of 3 bytes by referring to the signals A3 to A7, and also generates a synchronization pattern signal SYC (FIG. 11l)
and leads a synchronization signal (SYC) to the modulation circuit 21. Next, the selector 18c refers to the signals A3 to A7, and selector 18b selects only the address data sending period.
It plays a role of setting the output of 1 to the shift registers 19a and 19b. The address data thus set is converted into serial data by shift registers 19a and 19b and output. Following the address data, data D0 to D15 are selected by the selector 18c, and the shift register 1
9a and 19b. This data D0~
The timing for setting D15 is as follows. That is, the output signals A3 and A4 of the bit counter 16a, and the block counter output signals A5~
The shift register set timing signal DLOAD (FIG. 11o) generated by A7 and the timing signal sets the output signal of the buffer memory (RAM) 12a to the shift registers 19a and 19b, and also synchronizes with the write strobe signal STB to the buffer memory 12a. We also monitor whether there is any competition. FIG. 12 shows a time chart when this set timing signal DLOAD and the strobe signal of the buffer memory 12a do not conflict, and FIG. 13 shows a time chart when they conflict. The set timing signal DLOAD signal and the strobe signal STB are shown in FIGS. 12a, 13a, 12b, and 13b, respectively. In the case of FIG. 12, there is no conflict, that is, there is no overlap between the two signals, and the data set in the shift register is sent out in the same procedure as the address data. On the other hand, in the case of Figure 13, the signals DLOAD and STB conflict, that is, they overlap, and in such a case, the DLOAD signal is extended and set at a timing when there is no overlap, as shown by the dotted line in Figure 13a. Become. After being set, it is sent out in the same way as the address data as described above. Note that FIG. 13c is a circuit for obtaining the signal indicated by the dotted line in FIG. 13a, and is omitted in FIG. 7. FIG. 13c is composed of a logic circuit 61 which takes the logical product of the timing signal DLOAD' generated by the timing generation circuit and the strobe signal STB, a single-shot flip-flop 62, and an OR circuit 63. When a conflict occurs between the STB signal and the DLOAD' signal, the single-shot flip-flop operates and the DLOAD signal is extended for a certain period of time shown by the dotted line. The address is a block address, one to one
In the case of a master station in connection or 1-to-N connection, specify it using the block counter 17, but in the case of a slave station in 1-to-N connection, inputs of ADR5 to 7 are used for block specification, and this is used as the address. A selection is made to send. Also, shift register 1
When data is set, 9a and 19b output serial data the first time, invert it and use it as a serial input, and output it the second time. That is, this operation enables two consecutive reversal feedings.
Following the synchronization signal and address described above, data is selected and 4 bytes are sent out in two consecutive inversions, but this procedure is the same as for the address. 4
After the byte worth of data is sent out, a time period corresponding to 2 bytes, ie, the time indicated by E in the time chart of FIG. 11n, is provided, and one cycle ends here. The bit counter 16a and block counter 17 return to their initial states again, and the synchronizing signal SYC
Start sending from. As long as the basic clock is applied, it will be transmitted cyclically. On the other hand, the received data is transferred to the clock regeneration circuit 26.
The synchronization signal detection circuit 27 detects a synchronization signal from the data string. The operation of the receiving section starts with the detection of a synchronization signal, inputs the serial data to the shift register, and the parallel output becomes the address or data, but before this, a circuit compares the serial input with the inverted version of the serial output. 25 to detect the presence or absence of an error. Serial data is meaningful even if it consists of 16 bits, that is, 2 bytes, but since inversion double transmission verification is performed for each byte, parallel output data becomes valid only after 2 bytes are received in succession. Reception buffer registers 12c, 12d
are registers each having a size of 8 bits,
It is used to temporarily store the results of the two-byte inversion verification performed over two bytes until the timing RSTB at which 16 bits (two bytes) are collectively transferred to the buffer memory 12b. These reception time charts are shown in FIG. The first one to appear among the parallel signals is the address signal, which is written to the address register 29 and
If it is a slave station of 1-to-N connection method, ADR5 ~
7 and the comparator 24 to determine whether or not the local station is selected. If there is no error and the local station is selected as a slave station in the 1-to-N connection method, or if the local station is the master station in the 1-to-1 connection method or the 1-to-N connection method, the shift will continue. The output given from the register 19c is written into the buffer memory 12b as data. It is given by the address register 29 and bit counter 16b at this time. Next, reading out the contents of the buffer memory 12b written in the above manner will be described.
In the case of external control E, ADR is executed as shown in the read cycle shown in the time chart of Figure 8.
0 to 7, by specifying R/W from the outside,
It is possible to read data by outputting the data at the address to DATA0 to DATA15. In the case of internal control mode, the output signals of gate circuits 13c, 13d, and 13e generated from the reference clock signal are given as R/W, ADR0-7, and STB signals, respectively, as in the case of writing, and ADR0-7 are given as R/W, ADR0-7, and STB signals, respectively. the address data shown
Output to DATA0~15. At the same time ADR0~
7. R/W and STB signals are also output to the outside of this device. 13f is also a gate circuit. Next, a method of switching transmission modes will be explained.
Switching of the transmission mode is controlled by a transmission timing circuit 23 and a reception timing circuit 28. In the case of 1:1 first, and in the case of 1:N master station, the 6th
Data is repeatedly sent in the format shown in the figure. That is, in the case of 1:1, both parties transmit data completely independently, and in the case of 1:N, the master station has the initiative. On the other hand, among the 1:N slave stations, only those having the same block address as the one specified by the master station transmit data. That is, when the comparator 24 issues the block address matching command BS, this is applied to the reception timing circuit 28,
RT5 if TM specifies a 1:N slave station
emits. RT5 is input to the block counter 17 and sets the address stored in the address register 29. At the same time, RT5 joins the transmission timing circuit 23 to start the transmission operation and send out data in the format shown in FIG. That is, in a 1:N slave station, the transmission operation is activated when the received address matches the block address, and is stopped when the transmission of one block of data is completed. By doing this, output competition between slave stations is prevented in a 1:N connection. Next, we will discuss the simulation mode.
In the case of the external control mode (E is selected in E/I), writing to the buffer memory 12a and reading from the buffer memory 12b have already been described.
Here, a case will be described in which data is written to the buffer memory 12b using the ADR0-7, DATA0-15, and STB signals in the same manner as in the case of the buffer memory 12a. That is, this is a case where simulation data is written to 12b regardless of the received serial signal. The ADR signal and the R/W signal specify which buffer memory is to be accessed, and whether it is writing or reading. Furthermore, the signal SIM is input to the selector 30 to switch to the write mode to the buffer memory 12b. In addition, buffer memory 12
The address line and write strobe signal line of b are also switched by selectors 33 and 32. By this switching, even if serial data is being received, the buffer memory 12
It is possible to write to b. memory 1
Simulation data is written in 2a and 12b. The read operation is similar to the read operation described above. Next, the FLAG operation will be explained. FLAG bits are transmitted using empty bits in the address transmission byte. In FIG. 7, when the signal FLAG IN is applied, the FLAG bit in the transmission format shown in FIG. 6 is set to "1" and serial transmission is performed. On the other hand, the receiving circuit that receives the serial data whose FLAG bit is set to "1" writes "1" to the FLAG register 31, and
The FLAG register 31 outputs to the outside as FLAG OUT. When the FLAG signal is applied on the transmitting side in this way, the receiving side that receives it can identify it and output it to the outside. In the case of FLAG, signals can be transmitted without going through the buffer memories 12a and 12b, so it is often used when urgent data transmission is required. Next, we will discuss the signal disconnection detection function. It is necessary to detect when the signal is interrupted due to a failure of the transmitter, a disconnection of the transmission line, etc.
This transmitting/receiving device detects whether synchronization signals are received periodically. However, even when using a 1-to-N connection method like this device, the maximum number of connections N may not be reached. I decided to talk about the subsidiary stations. This will be explained using the embodiment shown in FIG. First, the case of the one-to-one connection method will be described. When a synchronizing signal is detected by the synchronizing signal detection circuit 27, a signal SY is outputted and inputted to the decoder 40a. In the one-to-one connection system, the decode value of the decoder 40a is uniquely determined by the mode switching signal TM, and the signal SY is derived only to the register 41a.
Register 41a is set by this SY signal,
After that, the set state is maintained unless a GR (General Reset) signal is applied from outside. In this way, it is stored in the register 41a that the synchronization signal has been detected once. The signal SY is also input to the decoder 40b, and the transmission mode is 1.
In the case of the one-to-one connection method, the counter 42a
An output signal is derived only when Counter 42a generates an output signal SYERR when signal SY is never detected during the time interval _TSYERR . In the example shown in Figure 16, T _SYERR is given by the period T _SYINT of the signal SY.
Since it is set to 3T _SYINT ≒ T _SYERR , signal discontinuation is detected only when the synchronization signal is not detected three or more times in a row. Next, a case of a 1-to-N (N=4 in the embodiment) connection method will be described. Serial signals are cyclically transmitted from the master station to the slave stations in address order (FIG. 17a). Repeated transmissions of #0 to #3 are performed. Serial data (SI) is returned from each address that received this signal, that is, the four stations #0 to #3 (FIG. 17b). However, here it is assumed that slave station #1 is not connected. The synchronization signal detection signal SY is obtained by receiving the reply signal from the slave station shown in FIG. 17b and detecting the synchronization signal. The signal SY is input to the decoder 40a and distributed to the registers 41a, 41b, 41c, and 41d according to the decoder addresses AD5 and AD6. The signal obtained by detecting the periodic signal from the reply signal from slave station #0, that is, the signal SY in FIG. 17c (signal at time _t1 ), is input to the register 41a, and the register 41a is set. This register 41a is not reset unless the signal GR is applied from outside, as in the case of the one-to-one connection method described above. At time t ₂ , slave station #1 is not connected, so the signal is
Since SY is not generated, register 41b is not set. Subsequently, at times t ₃ and t ₄ , slave stations #2 and #3
The registers 41c and 41d are set by the signal SY. In this way, registers 41a, 41c, and 41d are set for slave stations #0, #2, and #3 for which a synchronization signal is detected at least once for the first time. On the other hand, the signal SY is distributed to each address #0 to #3 by the decoder 40b, and is distributed to each address #0 to #3 by the counter 42.
a, 42b, 42c, and 42d. Each counter detects that the signal SY is never input during T _SYERR and outputs it. In the example of FIG. 17, the signal SY of slave station #3 was never input between t ₄ and t ₁₆ , so the counter 42c generates an output signal at t ₁₆ . For slave station #1 that was not connected from the beginning, counter 4 is activated at t ₁₀ .
2b generates an output signal. As a result, an output signal is generated in the AND gates 43a to 43d for slave station #3, which is among the slave stations that first detected a synchronization signal once, and for which a synchronization signal was not detected three times in a row. That is,
The AND gate 43d outputs, and the OR gate 44 generates an output signal ALARM. This signal becomes a signal interruption signal for other slave stations excluding the unconnected slave station,
Signal abnormalities can be detected once the synchronization signal is received. FIG. 18 shows an example of the configuration of a system to which the semiconductor integrated circuit for signal transmission according to the present invention is applied. transfers the state of one input to the output of the other, and the operating mode is 1:1 and both 80a and 80b are internally controlled. This is a type of device that uses the input/output status of a control device directly from a distance, and is called a remote input/output device. In this case, the control device side 80a is 1:1
external control, and 1:1 internal control on the input/output device side 80b. This type of input/output device is distributed in a distributed manner, and is called a distributed input/output device. In this case, the control device side 80a is a 1:N master station and performs external control, and the input/output control side 80b is a 1:N slave station and performs internal control. Both 80a and 80b are used for 1:1 external control in signal transmission between control devices. Note that in the above system, it is also possible to change the word length depending on the type of control device or input/output device. shows the basic configuration of 80a or 80b. Furthermore, in this embodiment, the signal transmission format is inverted double transmission, but the signal transmission format is not limited to this. BCH (Bose Chaubhuri
Hocquemghem) code may be used. As explained above, this signal transmitting/receiving device consolidates the functions for transmitting and receiving signals, and by attaching one device to each type of control device, it is possible to easily transmit and receive signals between them. This has the effect of simplifying and downsizing the control device.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining the outline of signal transmission. FIG. 1a shows a 1:1 case, and FIG. 2b shows a 1:N case. FIG. 2 is a diagram schematically showing connection with peripheral devices when a microcomputer is used. FIG. 3 is a diagram schematically showing how the signal transmitting/receiving device according to the present invention is coupled with other devices. FIG. 4 is an explanatory diagram of an example of data in serial word format. Figure 5 shows an example of a one-to-one connection for serial word format data transmission (Figure 5a),
An example of a 1-to-N connection (FIG. 5b) is shown. Figure 6~
FIG. 5 shows an example of a transmission data format in a 1-to-1 connection and a 1-to-N connection, and FIG. 6 shows an example of the FLAG transmission mode. FIG. 7 is a block diagram of the signal transmitting/receiving device in FIG. 3. 8a to 8e show time charts in the external control mode. FIGS. 9a to 9e show time charts in the internal control mode. 10th
The figure is an explanatory diagram of partially sharing address terminals and data terminals. FIGS. 11a to 11o are explanatory diagrams of the transmission timing of serial word format signals from the signal transmitting device. Figure 12 a, b, Figure 13 a, b, c are the first
FIG. 3 is an explanatory diagram of the timing of writing to a buffer memory and reading from a first buffer memory. 14th
Figures a to k are explanatory diagrams of the reception timing of serial word format signals. FIG. 15 shows a synchronization signal abnormality detection circuit. FIG. 16 shows the time chart of FIG. 15. FIG. 17 is a time chart for explaining signal interruption detection in the case of 1-to-4 connection. 18th
The figure shows an example of how signal transmitting and receiving devices are connected. 1, 1a, 1b, 2, 2a...2n...control device, 3...microprocessor, 4...signal transmission LSI, 6...memory, 7, 21...modulation circuit,
7a, Ta, Tb, T _aB , T _bB ...Transmission line, 8...Signal transmitting/receiving device, 9...Driver, 10...Receiver, 11a, 11b...Isolation transformer, 12a,
12b...Buffer memory, 15...I/O scanner, 16a...Bit counter, 17...Block counter, 19a, 19b, 19c...Shift register, 20...Synchronization signal generation circuit, 23...
...Transmission timing circuit, 27...Synchronization signal detection circuit, 26...Clock regeneration circuit, 28...Reception timing circuit, 25...Verification circuit, 62...Single shot flip-flop, 40a, 40b
...Decoder, 41a, 41b..., 42a, 42
b...Register, 80a, 80b, 80b ₁ , 80
b ₂ ...Semiconductor integrated circuit for signal transmission.

Claims (1)

[Scope of Claims] 1. A device for transmitting and receiving signals between a bus line that transmits signals in parallel word format and a device that transmits and receives signals in serial word format, comprising the following means on an LSI chip. A signal transmitting/receiving device characterized by: (b) The first unit that stores the input parallel word format signal.
(b) a serial signal transmission circuit that reads the parallel word format signal stored in the first memory, converts it into a serial word format signal, and outputs the signal; (c) an input serial word format signal; a serial signal receiving circuit that converts the signal into a parallel word format signal; (d) a second memory that stores the parallel word format signal from the serial signal receiving circuit; and (e) a read/write control signal based on the clock signal. and an input/output scanner circuit that outputs an address signal to control cyclic input/output of parallel word format signals to the first memory and the second memory, (f) signals of the signal transmitting/receiving device and the bus line. Specifies whether the input/output control of the controller is to be performed in an external control mode or an internal control mode, and when the external control mode is designated, the input/output control of the controller is controlled by read/write control signals and address signals sent via the bus line. A control mode switching circuit that switches to control input/output of parallel word format signals to the first memory and the second memory. 2. A device for transmitting and receiving signals between a bus line that transmits signals in parallel word format and a device that transmits and receives signals in serial word format, and is characterized by comprising the following means on an LSI chip. A signal transmitting and receiving device. (b) The first unit that stores the input parallel word format signal.
(b) a serial signal transmission circuit that reads the parallel word format signal stored in the first memory, converts it into a serial word format signal, and outputs the signal; (c) an input serial word format signal; a serial signal receiving circuit that converts the signal into a parallel word format signal; (d) a second memory that stores the parallel word format signal from the serial signal receiving circuit; and (e) a read/write control signal based on the clock signal. and an input/output scanner circuit that outputs address signals to control cyclic input/output of parallel word format signals to and from the first memory and the second memory; (f) the first memory and/or the second memory; A write/read word length setting circuit sets the word length for accessing memory No. 2 to a predetermined value. 3 Signals are transmitted and received between a bus line that transmits signals in parallel word format and multiple slave stations that transmit and receive signals in serial word format, and the following means are used.
A signal transmitting/receiving device characterized by being configured on an LSI chip. (b) A number-of-slave station designation circuit that specifies the number of slave stations that transmit and/or receive signals in serial word format from the master station using the signal transmitting/receiving device as a master station; (b) Parallel input circuit; The first to memorize the word form signal
(c) reading the parallel word format signal stored in the first memory, converting it into a serial word format signal, and time-sharing the signal according to the number specified by the slave station number designation circuit; a serial signal transmitting circuit that sequentially transmits the signal converted into the serial word format to each slave station in synchronization with the generated transmission timing signal; a serial signal receiving circuit that converts serial word format signals sequentially input from a specified number of slave stations in a designated circuit into parallel word format signals; (e) storing parallel word format signals from the serial signal receiving circuit; (f) outputting a read/write control signal and an address signal based on a clock signal to control cyclic input/output of parallel word format signals to and from the first memory and the second memory; input/output scanner circuit.