JPH0277158A - Solid image pick-up device - Google Patents

Abstract

PURPOSE:To prevent signal charge from mixing with that in a charge transfer part by a method wherein a read-out gate electrode and transfer electrodes are formed to be electrically isolated. CONSTITUTION:Transfer electrodes 7 (7a) cover only the upper part of an n type impurity layer 5 of a charge transfer part while a read-out gate electrode 10 electrically isolated from the transfer electrodes 7 (7a) is formed on the upper part of a read-out channel 8. The voltage of the read-out gate electrode 10 can be set up to make the potential (a) of the read-out channel 8 lower than PHIOFD and PHIL so that the signal charge in a photodiode 3 may be prevented from mixing with the signal charge below the transfer electrode 7 during charge transfer process. Furthermore, the transfer electrodes 7 (7a) being electrically isolated from the gate electrode 10 can augment values regardless of PHIOFD values, thereby preventing the signal mixture and increasing the transfer capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a solid-state imaging device, and particularly to an incline transfer type solid-state imaging device.

(Prior Art) The solid-state imaging device is generally configured as shown in FIGS. 7 to 9.

That is, a p-type well layer 2 having a thin layer portion 2a is formed on the upper surface of an n-type substrate 1 as a semiconductor substrate, and by laminating an n-type impurity layer 3 above this thin layer portion 2a, A pn junction photoelectric conversion element (photodiode) is formed that photoelectrically converts incident light and stores it for a predetermined period of time.

The thin layer portion 2a of the p-type well layer 2 is formed shallowly, and by applying a reverse bias voltage 4 between the thin layer portion 2a and the n-type substrate 1, excess signal charges generated in the n-type impurity layer 3 are eliminated. A vertical overflow drain is formed.

Further, an n-type impurity layer 5 is formed on the upper surface of the p-type well layer 2, and a signal transfer electrode 7 (7) is formed on this upper surface with an insulating film 6 interposed therebetween.
A to 7d) form a charge transfer section that transfers signal charges.

The transfer electrodes 7 (7a to 7d) also serve as gate electrodes for transferring signal charges generated and accumulated in the photodiode 3 to the n-type impurity layer 5 of the charge transfer section. It extends up to and overlies the readout channel 8 between 3 and 5. The channel snaps 9 on the sides of the n-type impurity layer 3.5 are element isolation layers.

FIG. 10 is a timing diagram of input pulses applied to the transfer electrodes 7a to 7d of the charge transfer section, where φ is applied to the transfer electrode 7a, φ5 is applied to the transfer electrode 7b, and φ is applied to the transfer electrode 7.
C and φ6 are applied to the transfer electrodes 7d, respectively, using a well-known four-phase drive system.

FIG. 11 shows a potential diagram of the plane Y 1 - Y 2 Y 3 in FIG. 8 corresponding to times 11.12 and t3 shown in FIG. 10.

In the figure, time t1 indicates a state in which the light incident on the photodiode 3 is charged and converted and signal charges are accumulated, and Q is the maximum storage capacity of the photodiode determined by the potential of the vertical over PDa+ax flow drain. be. At 12 o'clock, vH shown in FIG. 10 is applied, the readout channel 8 becomes a high potential, and the signal charge accumulated in the photodiode 3 is read out to the charge transfer section. This operation is called field shift operation). At time t, vM is applied, the potential of the read channel 8 becomes low, and signal charges are read out to the charge transfer section. After time t3, signal charges are transferred in the vertical direction shown in FIG. 7 by a well-known four-phase drive operation.

FIG. 12 shows the first section in the Pl-22 section shown in FIG.
11 shown in Figure 0 and t5 timing 3' 4 shows a potential diagram at the time of jig.

This figure shows the basic transfer operation of four-phase drive, and in the figure, QTfflax is the maximum transfer capacity of transfer charges. As is clear from the figure, this QTmax is determined by the potential ΦM when vM is applied to two adjacent electrodes and the potential Φ when VL is applied to the electrode sandwiching the two electrodes. proportional to the difference. That is,
Maximum transfer capacity in 4-phase drive Q11. lax is VM-
It is proportional to V.

(Problems to be Solved by the Invention) In FIG. 13, (a) shows a static characteristic graph of the potential of the read channel 8 with respect to the gate voltage (6), and (b) shows that of the n-type impurity layer 5.

Conventionally, the maximum transfer capacity QT1. Even if the value of ■ is lowered in order to increase laX, as can be seen from the graph in (b), this potential does not decrease below VTH. Also, on the contrary, even if the value of vM is increased □, (
The potential Φ (
(Fig. 14) also increases in proportion to v6 in the region S where vG>0. And the 14th
As shown in the figure, when this potential ΦFS exceeds the potential ΦOFD of the vertical overflow drain, for example, the signal charge photoelectrically converted by the photodiode 3 during signal charge transfer is transferred under the transfer electrode 7 (7a). It mixes into the signal charge that is present. Therefore, the value of this VM cannot be greater than the voltage vMOFD corresponding to the value of ΦOPD. However, the QT, ax, is vM
-VMOFD'VL"vTll is the maximum.

As described above, in the conventional example, the maximum transfer capacity QTlla depends on the amplitude of the applied voltage during transfer such as four-phase drive.
There is also a limit when x is proportional, and if a larger transfer capacity is required, a means unsuitable for miniaturization, such as widening the area of the n-type impurity layer 5, becomes necessary.

Furthermore, as shown in FIG. 13, in the n-type impurity layer 5, the degree of modulation (potential/vG) is
is lower than the region of VG〉0, the region of high modulation degree is defined as v
Can only be used with M<VMoDF. Figure 15 shows the Q
A graph of VL dependence of TIllax is shown.

FIG. 16 shows an electrical equivalent circuit diagram for grounding, etc. of the solid-state imaging device. Since the channel stop 9 is grounded only at the periphery of this device, the p-type well layer 2 has resistors RPa', RPb, and the transfer electrode 7a.
, 7b... and the p-type well layer 2, there are capacitances CGa, C
Gb . . . exists between the p-type well layer 2 and the n-type substrate 1, respectively.

By the way, when a VH level pulse is applied to the transfer electrode 7 (7a) during the field shift operation, the potential of the p-type well layer 2 instantly increases due to the capacitance as follows: ΔV pv −Cc, / (Cc, + Cp,) Xv
H... fluctuates by (1).

Since the start of the field shift operation, this amount of variation Δv
Pw recovers to the ground level, and the recovery time is determined by a constant time determined by a distributed constant circuit that is related to the position of the p-type well layer 2 and the distance from the ground point. Therefore, the recovery time differs depending on the position of the photodiode 3.

FIG. 17 shows that as the potential of the p-type well layer 2 changes, a residual charge Q is generated, and Q is
The case where PDmax Q' is decreased is shown.

PDmax In this case, the field shift time tF shown in FIG.
Since s was shorter than the constant time, the p-type well layer 2 could not be recovered sufficiently and a residual charge QLAG was generated.

FIG. 18 shows the above Q with respect to field shift time tFs.
', and shows that this recovery time differs depending on the position of the photodiode Dmax3. In this way, if the field shift time tFS is not sufficient, depending on the position of the photodiode 3, QP, ax
Because of this, for example, even if a - amount of strong light is incident on the photodiode, -
In some cases, a similar output cannot be obtained, that is, shading may occur.

Furthermore, in the manufacturing process, the mouth-type impurity layer 5 of the charge transfer section is generally formed by implanting impurity ions using a photomask. An error occurs in the gate length, and, for example, when the gate length becomes short, an abnormality may occur in the potential static characteristics due to the well-known short channel effect.

FIG. 19 shows a state where the n-type impurity layer 5 is closer to the readout channel 8 side and the gate length of the readout channel 8 is shortened.The potential diagram when the voltage of the transfer electrode 7 at this time is 0. is shown in Fig. 21. As shown in Fig. 21, a potential drop of ΔΦ8 occurs in the readout channel 8 due to the Schillert channel effect.

Further, FIG. 20 shows potential static characteristics similar to those shown in FIG. 13. As shown in the figure, readout channel 8
The static characteristic (a) is a depletion type characteristic due to the short channel effect. In the case of a structure with such characteristics, the value of ΦOPD "MOFD" becomes low, the maximum value of the maximum transfer capacity QTmax becomes low, and the same problem as described above occurs.

In view of the above, the present invention aims to increase the transfer capacity and expand the dynamic range without increasing the planar area of the charge transfer section that transfers signal charges, and to adjust the position of the photodiode with the maximum readout charge amount. It is an object of the present invention to provide a device in which shading is reduced by suppressing non-uniformity in each case.

[Structure of the invention]

(Means for solving the problem) In order to achieve the above object, the solid-state imaging device according to the present invention includes a plurality of photoelectric conversion elements and a device that temporarily stores and transfers signal charges generated by the photoelectric conversion elements. A solid-state imaging device including a charge transfer section formed by a MO5IJ1 electrode adjacent to a photoelectric conversion element, and an overflow drain that discharges excess charges generated in the photoelectric conversion element to a semiconductor substrate. A readout gate electrode for reading out signal charges to the charge transfer section is constituted by an electrode that is electrically separated from a transfer electrode that covers the impurity layer of the charge transfer section.

Alternatively, a gate electrode for reading out the signal charge to the charge transfer section may be formed in advance, and the impurity layer of the charge transfer section may be formed by implanting impurity ions through self-alignment of this electrode.

(Function) According to the present invention configured as described above, since the readout gate electrode and the transfer electrode are formed electrically separated, different arbitrary pulses can be applied to the readout gate electrode and the transfer electrode, respectively. This allows the potential of the readout channel under the readout gate electrode ΦF
In addition to arbitrarily setting s, it is possible to arbitrarily set the potentials Φ and Φ of the n-type impurity layer in the electrical transfer section below when a pulse is applied to the transfer electrode so that there is no relationship M with this potential ΦFs. can. This makes it possible to increase charge transfer capacity and improve amplitude efficiency while preventing signal charges from being mixed in.

Further, the pulse applied during field shift can be applied only to the readout gate electrode, thereby reducing the capacitance generated between the transfer electrode and the well layer.

Furthermore, by forming a readout gate electrode in advance and implanting impurity ions through self-alignment of this electrode to form an n-type impurity layer in the charge transfer section, encroachment of this n-type impurity layer into the readout channel is minimized. This can be prevented so that the gate length is always approximately constant.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

1 to 5 show a first embodiment, in which, similarly to the conventional example, a p-type well layer 2 with a thin layer portion 2a is formed on the upper surface of an n-type substrate 1 as a semiconductor substrate. By laminating an n-type impurity layer 3 above this thin layer portion 2a, a pn junction photoelectric conversion element (photodiode) that photoelectrically converts incident light and stores it for a predetermined period is formed.

The thin layer portion 2a of the p-type well layer 2 is formed shallowly, and by applying a reverse bias voltage 4 between the thin layer portion 2a and the n-type substrate 1, excess signal charges generated in the n-type impurity layer 3 are eliminated. A vertical overflow drain is formed.

Further, an n-type impurity layer 5 is formed on the upper surface of the p-type well layer 2, and a signal transfer electrode 7 (7) is formed on this upper surface with an insulating film 6 interposed therebetween.
A to 7d) form a charge transfer section that transfers signal charges.

Up to this point, the configuration is the same as that of the conventional example, but the present example has the following configuration.

That is, the transfer electrode 7 (7a) covers only the upper part of the n-type impurity layer 5 of the charge transfer section, and the readout channel 8 is provided above the readout channel 8, which is electrically separated from the transfer electrode 7 (7a). A gate electrode 10 is formed.

FIG. 2 shows a timing chart of input pulses corresponding to FIG. 10. In the same figure, S is an input pulse applied to the readout gate electrode 10, and only the VH during the a C field shift period that existed at φ and φ in FIG. 10 is applied to the readout gate electrode 10, and this φ and φ has a
C Va does not exist.

The first at the timing of t and t3 shown in this figure.
FIG. 3 shows a potential diagram of the three planes Y i -Y 2 - Y in the figure.

In the figure, time t2 is a field shift period, in which VH is applied to the readout gate electrode 10, the readout channel 8 becomes deeper, and signal charges are read out to the charge transfer section.

At time t3, the read channel 8 becomes shallow, indicating a state in which signal charges are temporarily accumulated in the charge transfer section.

FIG. 4 shows a state in which signal charges are transferred, which corresponds to FIG. 14.

As shown in the figure, the voltage of the read gate electrode 10 is
By setting the readout channel 8 potential to be less than ΦOPD and shallower than Φ□,
It is possible to prevent the signal charge in the photodiode 3 from being mixed into the signal charge under the transfer electrode 7 during charge transfer.

Further, since the transfer electrode 7 (7a) is electrically isolated from the read gate electrode 10, the value of VM is set to Φ. F,
It is possible to increase the transfer capacity without being limited to the value of , thereby increasing the transfer capacity while preventing signal mixing.

Since the value of ■ can be used with V M > V opo, the region V has a high degree of modulation. >0 can be used in large numbers, and the amplitude efficiency can be increased.

Further, since the read gate electrode 10 and the transfer electrode 7 (7a) are electrically isolated, Vn is applied only to the read gate electrode 10 during field shift. Since the readout gate electrode 10 covers only the readout channel 8, the capacity between the transfer electrode 7 (7a) and the p-type well layer 2 is
' is smaller than the conventional capacitance cG (FIG. 16). Therefore, the potential fluctuation ΔVPW of the p-type well layer 2 at the time of field shift is proportional to this capacitance CGa, and therefore becomes small. Then, the graph of the dependence of Q' on field shift time tFS on Dmax, which corresponds to FIG. 18, becomes as shown in FIG.

As shown in the figure, the photodiode PDI of Q'
Since the difference depending on the position of the Ilax-domain 3 is reduced, the occurrence of the shading can be reduced.

FIG. 6 shows a second embodiment, which differs from the first embodiment in that the readout gate electrode 10' is formed of a first layer gate, and the transfer electrode 7'(7'
The n-type impurity layer 5 of the charge transfer portion was formed by implanting impurity ions into the readout gate electrode 10' by the self-alignment method in the molding process before forming the readout gate electrode 10'.

With this configuration, the encroachment of the n-type impurity layer 5 into the readout channel 8 can be suppressed to only a certain amount of lateral diffusion of the impurity. It is possible to prevent the gate length of the read channel 8 from becoming short due to the deviation, thereby preventing the short channel effect from occurring.

Note that if the n-type impurity layer 5 can be formed by the self-alignment method of the readout gate electrode 10', the readout gate 10' is not limited to the first layer gate.

Further, although each of the above embodiments shows a structure in which a p-well layer is provided on an n-type substrate, the structure is not limited to this, and a horizontal overflow drain may be used instead of a vertical overflow drain. Of course.

〔Effect of the invention〕

Since the present invention has the above-mentioned configuration, the charge transfer section can be improved without increasing the planar area of the charge transfer section that transfers signal charges, and without increasing the amplitude of the pulse applied to the charge transfer section. Maximum transfer capacity can be increased.

Moreover, it is possible to reduce fluctuations in the potential of the well when reading signal charges, reduce non-uniformity of the maximum readout charge amount of signal charges at each position of the photodiode, and reduce shading.

In addition, by forming an impurity layer in the charge transfer section by self-aligning the gate electrode that reads out the signal charges, shorting of the readout channel can be prevented and signal charges can be mixed into the charge transfer section. It has the effect of being able to prevent

[Brief explanation of the drawing]

1 to 5 show a first embodiment of the present invention.
The figure is a longitudinal cross-sectional view (corresponding to Figure 8), Figure 2 is a timing diagram of drive pulses, and Figures 3 (A) and (B) are Yl- of Figure 1 at times t and t3 shown in Figure 2. Figure 4 is a potential diagram of the Y1-Y2-Y3 section during transfer operation, and Figure 5 is a potential diagram of the field shift time 'PS of potential Q'.
FIG. 6 is a graph showing the dependence of Dmax on the second embodiment.
7 to 18 show the conventional example, FIG. 7 is a plan view, FIG. 8 is a sectional view taken along line Xl-X2 in FIG. 7, and FIG. 9 is a 21-22 sectional view shown in FIG. 7. Figures 10 and 10 are timing diagrams of drive pulses, and Figures 11 (a), (b), and (c) are the timing diagrams of the driving pulses.
ti shown in Figure 0. The potential diagram of YI Y2-Y3 cross section of FIG. 8 at times t and t3, and the potential diagram of FIG. 11 and 13 are graphs showing the static characteristics of the readout channel (a) and the n-type impurity layer (b) with respect to the gate voltage ■G, respectively.
The figure is equivalent to Figure 4, and Figure 15 is the potential QTIll.
A graph showing the dependence on axovL, Fig. 16 is an electrical equivalent circuit, and Fig. 17 is a graph showing the dependence on axovL.
1(B), FIG. 18 is a diagram equivalent to FIG. 5, FIGS. 19 to 21 show other different conventional examples, FIG. 19 is a diagram equivalent to FIG. 8, and FIG. FIG. 21 is a diagram equivalent to FIG. 14 when the voltage of the transfer electrode is Ov. 1... N-type substrate (semiconductor substrate), 2... P-type well layer, 2a... Thin layer portion, 3... N-type impurity layer (photodiode), 5... N-type impurity layer (charge transfer section), 7 (7a to 7d)...transfer electrode (charge transfer section),
8... Readout channel, 10... Readout gate electrode. Applicant's agent Sato - Yu ΦM Figure 1 Figure 4 Tsuta 2 Figure (tzl (13) (
b) (0
) Trap 3 figure Q'POrmx Tame 5 figure Ima 6 figure Trap 9 figure (a)
(B) (Irishima map 12 jl') Figure 16 Akira old map Tame 19 map 2Q map

Claims (1)

[Scope of Claims] 1. A charge transfer section formed by a plurality of photoelectric conversion elements and a MOS type electrode adjacent to the photoelectric conversion elements that temporarily stores and transfers signal charges generated by the photoelectric conversion elements; In a solid-state imaging device including an overflow drain for discharging excess charge generated in the photoelectric conversion element to a semiconductor substrate, a readout gate electrode for reading signal charges generated in the photoelectric conversion element to the charge transfer section is connected to the charge transfer section. What is claimed is: 1. A solid-state imaging device comprising a transfer electrode covering an upper part of an impurity layer and an electrically separated electrode. 2. A readout gate electrode for reading out the signal charge to the charge transfer section is formed in advance, and the impurity layer of the charge transfer section is formed by implanting impurity ions through self-alignment of this electrode. The solid-state imaging device described.