JPH09139490A - Solid state image pick up apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image pick up apparatus for enlarging dynamic range by increasing a transfer capacity without increasing a plane area of a signal charge transfer means and reducing shading by controlling ununiformity in the maximum read amount of charge of each position of a photoelectric converting element. SOLUTION: The image pick up apparatus comprises a plurality of photoelectric converting elements 3, a charge transfer means 5 formed of an n-type impurity layer formed of a transfer electrode 7 for temporarily storing and transferring the signal charges generated by the element 3 and a vertical type overflow drain for exhausting excessive charges generated by the photoelectric converting element 3 to a semiconductor substrate 1. A read gate electrode 10 for reading signal charges generated by the element 3 to the charge transfer means 5 is formed of an electrode electrically isolated from a transfer electrode 7 covering the upper part of the impurity layer of the charge transfer means 5 and sets the potential of the read gate electrode 10 to the potential lower than the vertical type overflow drain potential under the condition that a high level voltage is applied to the transfer electrode 7 during the period other than the transfer period for transferring the generated signal charges to the charge transfer means 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to an interline transfer type solid-state image pickup device.

[0002]

2. Description of the Related Art The solid-state image pickup device is generally constructed as shown in FIGS.

That is, a p-type well layer 2 having a thin layer portion 2a is formed on the upper surface of an n-type substrate 1 as a semiconductor substrate, and an n-type impurity layer 3 is laminated above this thin layer portion 2a. As a result, a pn-junction photoelectric conversion element (photodiode) that photoelectrically converts incident light and accumulates it for a predetermined period is formed.

The thin layer portion 2a of the p-type well layer 2 is formed shallow, and by applying a reverse bias voltage 4 between it and the n-type substrate 1, excess signal charge generated in the n-type impurity layer 3 is generated. A vertical overflow drain is formed to eliminate the.

An n-type impurity layer 5 is formed on the upper surface of the p-type well layer 2, and transfer electrodes 7 (7a to 7d) are formed on the upper surface of the n-type impurity layer 5 via an insulating film 6 to transfer signal charges. And a charge transfer section that operates. The transfer electrodes 7 (7a to 7d) also serve as gate electrodes for transferring the signal charges generated and accumulated in the photodiode 3 to the n-type impurity layer 5 of the charge transfer section, and the n-type impurity layer. It extends to the read channel 8 between 3 and 5 and covers it above. The channel stop 9 on the side of the n-type impurity layers 3 and 5 is an element isolation layer.

FIG. 10 shows the transfer electrode 7 of the charge transfer section.
FIG. 6 is a timing chart of input pulses applied to a to 7d, where φa is to the transfer electrode 7a, φb is to the transfer electrode 7b, and φ is
c is a well-known four-phase drive system in which the transfer electrode 7c and φd are applied to the transfer electrode 7d, respectively.

FIG. 11 shows a potential diagram of a cross section taken along the line Y1-Y2-Y3 of FIG. 8 corresponding to times t1, t2 and t3 shown in FIG.

In the figure, at t1, the light incident on the photodiode 3 is photoelectrically converted and signal charges are accumulated, and QPDmax is the maximum storage capacitance of the photodiode determined by the potential of the vertical overflow drain. Is. At t2, VH shown in FIG.
Is applied, the read channel 8 has a high potential, and the signal charge accumulated in the photodiode 3 is being read to the charge transfer portion (hereinafter, this operation is referred to as a field shift operation). VM at t3
Is applied, the potential of the read channel 8 becomes low, and the signal charge is read to the charge transfer section. After t3, the signal charge is transferred in the vertical direction shown in FIG. 7 by the well-known four-phase driving operation.

FIG. 12 shows a potential diagram at timings t4, t5 and t6 shown in FIG. 10 in the P1-P2 portion shown in FIG.

This figure shows a basic transfer operation of four-phase drive, and in the figure, QTmax is the maximum transfer capacity of transfer charges. As is clear from the figure, QTmax is the difference between the potential ΦM when VM is applied to two adjacent electrodes and the potential ΦL when VL is applied to the electrodes sandwiching the two electrodes. Proportional to. That is,
The maximum transfer capacity QTmax in four-phase driving is proportional to VM-VL.

[0011]

FIG. 13 shows a static characteristic graph of the potential of the read channel 8 with respect to the gate voltage VG in (a) and that of the n-type impurity layer 5 in (b).

Conventionally, even if the value of VL is lowered in order to increase the maximum transfer capacity QTmax, this potential does not become lower below VTH, as can be seen from the graph of (b). On the contrary, even if the value of VM is increased,
Potential ΦFS of read channel 8 shown in (a)
Also in FIG. 14), in the region of VG> 0, it becomes higher in proportion to VG. Then, as shown in FIG. 14, when this potential ΦFS exceeds the potential ΦOFD of the vertical overflow drain, for example, the signal charges photoelectrically converted by the photodiode 3 at the time of the transfer of the signal charges are below the transfer electrode 7 (7a). Will be mixed in with the signal charges being transferred by. Therefore, the value of VM cannot exceed the voltage VMOFD corresponding to the value of ΦOFD. However, QTmax is maximum when VM = VMOFD and VL = VTH.

As described above, there is a limit to the case where the maximum transfer capacitance QTmax is proportional to the amplitude of the applied voltage at the time of transfer such as the four-phase drive in the conventional example, and a transfer capacitance higher than that is required. In that case, a means unsuitable for miniaturization such as widening the region of the n-type impurity layer 5 is required.

As shown in FIG. 13, in the n-type impurity layer 5, the modulation degree (potential / VG) is lower in the region of VG <0 than in the region of VG> 0. Can only be used with VM <VMOFD. FIG. 15 is a graph showing the VL dependence of QTmax.

FIG. 16 shows an electrical equivalent circuit diagram of the solid-state image pickup device such as grounding. Since the channel stop 9 is grounded only in the periphery of this device, the p-type well layer 2 has resistors RPa, RPb ... And the transfer electrode 7
Between the a, 7b ... And the p-type well layer 2 the capacitances CGa, CGb ...
Between the p-type well layer 2 and the n-type substrate 1 having capacitances CPa and C
Pb ... will exist respectively.

When a VH level pulse is applied to the transfer electrode 7 (7a) during the field shift operation,
The potential of the p-type well layer 2 instantaneously changes by ΔVPW = CGa / (CGa + CPa) × VH (1) due to the capacitance.

After the field shift operation is started, the variation ΔVPW is restored to the ground level. The recovery time depends on the distributed constant circuit related to the position of the p-type well layer 2 and the distance from the ground point. It is decided by a fixed number of times. Therefore, the recovery time varies depending on the position of the photodiode 3.

FIG. 17 shows a case where the residual charge QLAG is generated with the change in the potential of the p-type well layer 2 and QPDmax is reduced to Q'PDmax.

In this case, since the field shift time tFS shown in FIG. 10 was shorter than the fixed time, the p-type well layer 2 could not be fully recovered and the residual charge QLAG was generated.

FIG. 18 shows the relation between the Q'PDmax and the field shift time tFS.
It is shown that the recovery time differs depending on the position of. When the field shift time tFS is not sufficient as described above, QPDmax may not be obtained depending on the position of the photodiode 3, and even if a strong light of a uniform quantity is incident on the photodiode, QPDmax may not be obtained. , When uniform output cannot be obtained, that is, shading may occur.

Further, in the manufacturing process, the n-type impurity layer 5 of the charge transfer portion is generally formed by implanting impurity ions with a photomask. In that case, depending on the amount of misalignment with the transfer electrode 7, the read channel is read. An error occurs in the gate length of the area 8 and, for example, this gate length is shortened, and due to the well-known short channel effect,
Abnormalities may occur in the static potential characteristics.

FIG. 19 shows a state in which the n-type impurity layer 5 is closer to the read channel 8 side and the gate length of the read channel 8 is shorter. Then, FIG. 21 shows a potential diagram when the voltage of the transfer electrode 7 at this time is 0V. As shown in the figure, in the read channel 8, the potential decrease of ΔΦS occurs due to the short channel effect.

Further, FIG. 20 shows a potential static characteristic similar to that shown in FIG. As shown in the figure, the static characteristic (a) of the read channel 8 is a depletion type characteristic due to the short channel effect.
In the case of the structure having such characteristics, the value of VMOFD which is ΦOFD becomes low and the maximum value of the maximum transfer capacity QTmax becomes low, and the same problem as described above occurs.

In view of the above, the present invention increases the transfer capacitance without increasing the planar area of the charge transfer portion for transferring the signal charge, thereby expanding the dynamic range and increasing the maximum read charge amount. An object of the present invention is to provide a device in which the shading is reduced by suppressing nonuniformity of each diode position.

[0025]

In order to achieve the above object, a solid-state image pickup device according to the present invention is provided with a plurality of photoelectric conversion elements and a photoelectric conversion element for temporarily accumulating and transferring signal charges generated by the photoelectric conversion elements. In a solid-state imaging device including a charge transfer section formed by a MOS electrode adjacent to a conversion element and an overflow drain for discharging excess charges generated in the photoelectric conversion element to a semiconductor substrate, the overflow drain is a vertical overflow. A read gate electrode, which is a drain and reads out the signal charge generated in the photoelectric conversion element to the charge transfer unit, is constituted by an electrode electrically separated from a transfer electrode covering the impurity layer of the charge transfer unit, The signal charges generated in the photoelectric conversion element are transferred to the transfer electrodes during a period other than the transfer timing for transferring the signal charges to the charge transfer unit. In which the potential of the readout gate electrode level voltage (VM) while applying were constructed in the lower potential than the potential (ΦOFD) of the vertical overflow drain.

The vertical overflow drain is formed by providing a p-well layer on an n-type substrate and applying a reverse bias voltage between the p-well layer and the n-type substrate.

It is also possible to previously form a gate electrode for reading out the signal charge to the charge transfer portion and form the impurity layer of the charge transfer portion by implanting impurity ions by self-alignment of this electrode. .

According to the present invention configured as described above, the read gate electrode and the transfer electrode are electrically separated from each other, so that different arbitrary pulses are applied to the read gate electrode and the transfer electrode, respectively. Accordingly, the potential ΦFS of the read channel below the read gate electrode is arbitrarily set, and the potentials ΦL and ΦM of the n-type impurity layer of the charge transfer portion below this when the pulse is applied to the transfer electrode. This potential ΦFS
It can be arbitrarily set regardless of. As a result, it is possible to increase the charge transfer capacity and improve the amplitude efficiency while preventing the signal charges from being mixed.

Further, the pulse applied during the field shift can be applied only to the read gate electrode, which can reduce the capacitance generated between the transfer electrode and the well layer.

Further, a read gate electrode is formed in advance,
By implanting impurity ions by self-alignment of this electrode, an n-type impurity layer of the charge transfer portion is formed to prevent the n-type impurity layer from biting into the read channel as much as possible, so that the gate length is always substantially constant. Can be

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

1 to 5 show the first embodiment,
Similar to the conventional example, a p-type well layer 2 having a thin layer portion 2a is formed on the upper surface of an n-type substrate 1 as a semiconductor substrate, and an n-type impurity layer 3 is formed above the thin layer portion 2a. By stacking the layers, a pn-junction photoelectric conversion element (photodiode) that photoelectrically converts incident light and accumulates it for a predetermined period is formed.

The thin layer portion 2a of the p-type well layer 2 is formed shallow, and by applying a reverse bias voltage 4 between it and the n-type substrate 1, excess signal charge generated in the n-type impurity layer 3 is generated. A vertical overflow drain is formed to eliminate the.

Further, the n-type impurity layer 5 is formed on the upper surface of the p-type well layer 2, and the transfer electrodes 7 (7a to 7d) are formed on the upper surface via the insulating film 6 to transfer the signal charges. Is formed.

Up to this point, the process is similar to that of the conventional example,
This embodiment has the following configuration.

That is, the transfer electrode 7 (7a) covers only the upper portion of the n-type impurity layer 5 of the charge transfer portion, and the upper portion of the read channel 8 is electrically separated from the transfer electrode 7 (7a). The read gate electrode 10 thus formed is formed.

FIG. 2 shows a timing chart of the input pulse corresponding to FIG. In the figure, φFS is an input pulse applied to the read gate electrode 10, and only VH in the field shift period existing in φa and φc in FIG. 10 is applied to the read gate electrode 10, and these φa and φc There is no VH.

FIG. 3 shows a potential diagram of a cross section taken along the line Y1-Y2-Y3 of FIG. 1 at the timing of t2 and t3 shown in this figure.

In the figure, t2 is a field shift period, in which VH is applied to the read gate electrode 10, the read channel 8 is deepened, and signal charges are read out to the charge transfer portion. At t3, the reading channel 8 becomes shallow, and the signal charge is temporarily stored in the charge transfer portion.

FIG. 4 shows a state in which the signal charges are being transferred, which is equivalent to FIG.

As shown in the figure, the read gate electrode 1
0 voltage, the potential of the read channel 8 is Φ
By setting the depth shallower than OFD and shallower than ΦL, it is possible to prevent the signal charge in the photodiode 3 from being mixed with the signal charge under the transfer electrode 7 at the time of charge transfer.

Further, since the transfer electrode 7 (7a) is electrically separated from the read gate electrode 10, the value of VM can be increased without being restricted by the value of ΦOFD, thereby mixing the signal. The transfer capacity can be increased while preventing it.

Since the value of VM can be used with VM> VOFD, a large area VG> 0 with a high degree of modulation can be used,
Amplitude efficiency can be increased.

Further, since the read gate electrode 10 and the transfer electrode 7 (7a) are electrically separated from each other, VH is applied only to the read gate electrode 10 during the field shift. Since the read gate electrode 10 covers only the read channel 8, the capacitance CGa ′ between the transfer electrode 7 (7a) and the p-type well layer 2 is the same as the conventional capacitance CGa (see FIG. 16). ) Becomes smaller. Therefore, the potential fluctuation ΔVPW at the time of field shift of the p-type well layer 2 is small because it is proportional to the capacitance CGa. Then, the graph of the dependence of Q'PDmax on the field shift time tFS corresponding to FIG. 18 is shown in FIG.

As shown in the figure, since the difference in Q'PDmax depending on the position of the photodiode 3 becomes small, the occurrence of shading can be reduced.

FIG. 6 shows a second embodiment. The difference from the first embodiment is that the read gate electrode 1 is used.
0'is formed by the gate of the first layer, and in the formation process before the transfer electrode 7 '(7'a) is formed, by implanting impurity ions by the self-alignment method of the read gate electrode 10', The point is that the n-type impurity layer 5 of the charge transfer portion is formed.

With such a structure, the bite of the n-type impurity layer 5 into the read channel 8 can be suppressed to only a certain amount of lateral diffusion of impurities, whereby the photo of the n-type impurity layer 5 can be suppressed. It is possible to prevent the short channel effect from occurring due to the gate length of the read channel 8 being shortened due to the mask misalignment.

If the n-type impurity layer 5 can be formed by the self-alignment method of the read gate electrode 10 ', the read gate 10' is not limited to the first layer gate.

Further, in each of the above-mentioned embodiments, p is formed on the n-type substrate.
Although the structure in which the well layer is provided is shown, the present invention is not limited to this, and it goes without saying that a horizontal overflow drain may be used instead of the vertical overflow drain.

[0050]

Since the present invention has the above-mentioned structure,
It is possible to increase the maximum transfer capacity of the charge transfer unit without increasing the planar area of the charge transfer unit that transfers the signal charge and without increasing the amplitude of the pulse applied to the charge transfer unit.

In addition, the fluctuation of the potential of the well at the time of reading the signal charge can be reduced, the non-uniformity of the maximum read charge amount of the signal charge at each position of the photodiode can be reduced, and the shading can be reduced. .

Further, by forming the impurity layer of the charge transfer section by self-alignment of the gate electrode for reading out the signal charge, it is possible to prevent the read channel from being short-circuited and to send the signal to the charge transfer section. There is an effect that the mixture of charges can be prevented.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view (equivalent to FIG. 8) showing a first embodiment of the present invention.

FIG. 2 is a timing chart of drive pulses according to the first embodiment of the present invention.

3 (a) and (b) are t2 and t3 shown in FIG.
Potential diagram of Y1-Y2-Y3 section of FIG.

FIG. 4 is a potential diagram of a cross section of the Y1-Y2-Y3 portion during a transfer operation.

FIG. 5 is a graph showing the dependence of the potential Q′PDmax on the field shift time tFS.

FIG. 6 is a view corresponding to FIG. 1 showing a second embodiment.

FIG. 7 is a plan view showing a conventional example.

8 is a sectional view taken along line X1-X2 of FIG. 7.

9 is a Z1-Z2 sectional view of FIG. 7;

FIG. 10 is a timing chart of drive pulses showing a conventional example.

11 (a), (b) and (c) are t shown in FIG.
Y1-Y2-Y3 of FIG. 8 at 1, t2 and t3.
Potential diagram of cross section.

12 (a), (b) and (c) are t shown in FIG.
4, potential diagrams of P1-P2 portion of FIG. 9 at t5 and t6.

FIG. 13 is a graph showing static characteristics of the read channel (a) and the n-type impurity layer (b) with respect to the gate voltage VG.

FIG. 14 is a view showing a conventional example corresponding to FIG.

FIG. 15 is a graph showing the dependency of the potential QTmax on VL showing a conventional example.

FIG. 16 is an electrical equivalent circuit showing a conventional example.

FIG. 17 is a view corresponding to FIG. 11B when the p-type well layer is changed, showing the conventional example.

FIG. 18 is a view showing a conventional example corresponding to FIG.

FIG. 19 is a view showing another conventional example corresponding to FIG.

FIG. 20 is a view showing another conventional example corresponding to FIG.

FIG. 21 is a diagram showing another conventional example corresponding to FIG. 14 when the voltage of the transfer electrode is 0V.

[Explanation of symbols]

 1 n-type substrate (semiconductor substrate) 2 p-type well layer 2a same thin layer portion 3 n-type impurity layer (photodiode) 5 n-type impurity layer (charge transfer part) 7 (7a to 7d) transfer electrode (charge transfer part) 8 readout channel 10 readout gate electrode

Claims (3)

[Claims] 1. A photoelectric transfer element, a charge transfer section formed by a MOS type electrode adjacent to the photoelectric conversion element for temporarily storing and transferring signal charges generated in the photoelectric conversion element, and the photoelectric conversion element. In a solid-state imaging device including an overflow drain that discharges excess charges generated in an element to a semiconductor substrate, the overflow drain is a vertical overflow drain, and the signal charge generated in the photoelectric conversion element is read to the charge transfer unit. The read gate electrode is constituted by an electrode electrically separated from the transfer electrode covering the impurity layer of the charge transfer section, and the signal charge generated in the photoelectric conversion element is transferred to the charge transfer section except at the transfer timing. During the period, the potential of the read gate electrode is set to the above while the high level voltage (VM) is applied to the transfer electrode. The solid-state imaging device, characterized in that the from the low-potential type overflow drain potential (ΦOFD). 2. The vertical overflow drain is formed by providing a p-well layer on an n-type substrate and applying a reverse bias voltage between the p-well layer and the n-type substrate. The solid-state imaging device according to claim 1. 3. A read gate electrode for reading the signal charge to a charge transfer portion is formed in advance, and impurity ions are implanted by self-alignment of the electrode to form the impurity layer of the charge transfer portion. The solid-state imaging device according to claim 1.